UNIT 4: Digital Electronics Logic Design - Comprehensive Short Notes

Based on RGPV Past Papers (2022-2025)

1.0 Number Systems & Code Conversions

1.1 Conversion between Bases (2, 8, 10, 16)

• Integer Part: Repeated division by new base. Remainders read bottom to top.

• Fractional Part: Repeated multiplication by new base. Integer parts collected top to bottom.

  [!TIP] For mixed bases (e.g., base-6), first convert each digit to decimal/binary, then combine.

1.2 Binary, Octal, Hexadecimal Inter-conversions

• Binary ↔ Octal: Group 3 bits (pad with leading/trailing zeros).

• Binary ↔ Hexadecimal: Group 4 bits.

• Octal/Hex → Decimal: Expand using positional weights.

1.3 Binary ↔ Gray Code Conversion

• Binary to Gray (G): $$\displaystyle G_n = B_n \oplus B_{n+1} $$ (MSB same, XOR successive bits).

  Example: $$\displaystyle 10110_2 \rightarrow 11101_{Gr} $$

• Gray to Binary (B): $$\displaystyle B_n = G_n \oplus B_{n+1} $$ (MSB same, XOR with previously computed bit).

  Example: $$\displaystyle 11101_{Gr} \rightarrow 10110_2 $$

1.4 Conversion of Mixed-Radix Numbers

• Convert each digit to decimal using its positional weight (base varies per position).

• Example: $$\displaystyle (AB33)_6 $$ where A=10, B=11.

  • Decimal = $$\displaystyle 10 \times 6^3 + 11 \times 6^2 + 3 \times 6^1 + 3 \times 6^0 $$

  • Then convert decimal to binary/Gray.

1.5 BCD Code Conversions

• Decimal → BCD: Convert each decimal digit to its 4-bit binary equivalent.

• BCD → Decimal: Group 4 bits, convert each group to decimal digit.

• Invalid BCD codes: 1010–1111 (10–15).

2.0 Boolean Algebra & Function Simplification

2.1 Boolean Theorems & Laws

• De Morgan's Theorems:

  • $$\displaystyle (A + B + C + ...)' = A'B'C'... $$

  • $$\displaystyle (ABC...)' = A' + B' + C' + ... $$

  [!TIP] Proof via truth table for 2/3 variables. Apply repeatedly for complex expressions.

2.2 Minimization Techniques

• Karnaugh Map (K-Map):

  • Up to 4 variables (2^4 = 16 cells).

  • Grouping: Powers of 2 (1,2,4,8,16). Adjacent cells (including wrap-around).

  • Don't Cares (d): Treat as '1' if helpful, else ignore.

  • SOP: Sum of prime implicants (largest groups).

  • POS: Product of prime implicants of $F'$ (group 0s).

• Quine-McCluskey (Tabulation Method):

  1. List minterms in binary, group by number of 1s.

  2. Combine adjacent groups (differ by 1 bit), mark combined terms.

  3. Repeat until no more combinations → Prime Implicants (PIs).

  4. Construct Prime Implicant Chart (rows: PIs, columns: minterms).

  5. Identify Essential Prime Implicants (EPIs) (columns covered by only one PI).

  6. Use Petrick's Method for remaining minterms if needed.

  [!TIP] With don't cares, include them in initial list but exclude from final cover.

2.3 Canonical Forms

• Sum of Minterms (SOP): $$\displaystyle F = \Sigma m(\text{minterm numbers}) $$

  • Minterm: Product term with all variables (e.g., $A'B'C$ for minterm 1).

• Product of Maxterms (POS): $$\displaystyle F = \Pi M(\text{maxterm numbers}) $$

  • Maxterm: Sum term with all variables (e.g., $A+B+C'$ for maxterm 1).

• Relationship: $$\displaystyle m_i = M_i' $$ and $$\displaystyle M_i = m_i' $$.

3.0 Logic Gates & Universal Gates

3.1 NAND & NOR as Universal Gates

• NAND Implementation:

  • NOT: $$\displaystyle A' = A \cdot A $$ (1-input NAND)

  • AND: $$\displaystyle AB = (AB)' ' = ((A \cdot B)' )' $$

  • OR: $$\displaystyle A+B = (A' \cdot B')' $$ (De Morgan)

  • XOR: $$\displaystyle A \oplus B = (A \cdot B')' \cdot (A' \cdot B)' $$

  • XNOR: $$\displaystyle (A \oplus B)' = (A \cdot B) + (A' \cdot B') $$

• NOR Implementation: Similar using NOR and De Morgan.

  Example: OR = $(A+B)' '$, AND = $((A'+B')')'$.

3.2 Conversion of Multilevel AND-OR to All-NAND

• Rule 1: Convert all AND-OR to NAND-NAND by replacing:

  • AND → NAND (add bubble if needed).

  • OR → NAND (add bubbles at inputs).

  • Inverters: Use 1-input NAND or pair of NANDs.

• Rule 2: Ensure single inversion between any two levels.

4.0 Combinational Logic Circuits

4.1 Arithmetic Circuits

• Half Adder (HA):

  • Sum = $A \oplus B$, Carry = $AB$.

  • IC: None standard (built from gates).

• Full Adder (FA):

  • Sum = $$\displaystyle A \oplus B \oplus C_{in} $$

  • Carry = $$\displaystyle AB + BC_{in} + AC_{in} $$

  • IC 7483: 4-bit full adder (ripple carry).

• Half Subtractor (HS):

  • Difference = $A \oplus B$, Borrow = $A'B$.

• Full Subtractor (FS):

  • Difference = $$\displaystyle A \oplus B \oplus B_{in} $$

  • Borrow = $$\displaystyle A'B + B_{in}(A' + B) $$

• BCD Adder:

  • Add two BCD digits. If sum > 9 or carry = 1, add 6 (0110) to correct.

  • Correction logic: $$\displaystyle C_{out} = C_{out,FA} + (S_3 S_2) + (S_3 S_1) $$.

4.2 Data Processing Circuits

• Multiplexer (MUX):

  • $$\displaystyle 2^n:1 $$ MUX has $n$ select lines, $$\displaystyle 2^n $$ data inputs.

  • Implementation: Use select lines as variables, data inputs as constants (0/1) or literals.

  • Example: 4:1 MUX for 4-variable function → $$\displaystyle S_1S_0 $$ as two variables, D0-D3 as function of other two.

• Demultiplexer (DEMUX) & Decoder:

  • Decoder: $n$-input → $$\displaystyle 2^n $$ outputs, one-hot. Enable input active-high.

  • 2:4 Decoder: $$\displaystyle E, A_0, A_1 $$ → $$\displaystyle Y_0 $$ to $$\displaystyle Y_3 $$ ($$\displaystyle Y_i = E \cdot A_0' A_1' $$ etc.).

  • Binary-to-Gray Decoder: Outputs Gray code for given binary input.

• Encoder:

  • Priority Encoder: Multiple inputs, highest-priority input encoded. Outputs valid flag if any input active.

  • 4:2 Priority Encoder: Inputs $$\displaystyle I_3...I_0 $$ (I3 highest). $$\displaystyle Y_1Y_0 = \text{encode}(I) $$, $$\displaystyle V = I_3+I_2+I_1+I_0 $$.

  • Limitation: Simple encoder fails with multiple inputs active.

4.3 Comparison & Error Detection

• Magnitude Comparator:

  • 1-bit: $$\displaystyle A>B $$: $A B'$; $$\displaystyle A<B $$: $A' B$; $$\displaystyle A=B $$: $A \odot B$ (XNOR).

  • n-bit: Cascaded using $$\displaystyle A>B $$, $$\displaystyle A<B $$, $$\displaystyle A=B $$ from previous stage.

  • 4-bit: $$\displaystyle A>B = A_3 B_3' + (A_3 \odot B_3) A_2 B_2' + ... $$

• Parity Generator & Checker:

  • Even Parity: Generator XORs all data bits. Checker XORs all received bits (including parity) → 0 if even.

  • Odd Parity: Generator XORs all data bits and inverts output. Checker XORs all bits → 1 if odd.

  • Error Detection: Single-bit error flips parity.

  Example: ASCII 'B' = 01000010 (binary). For odd parity, add parity bit $P$ such that $$\displaystyle P \oplus 0 \oplus 1 \oplus 0 \oplus 0 \oplus 0 \oplus 0 \oplus 1 \oplus 0 = 1 $$ → $$\displaystyle P=0 $$. Transmitted: 0 01000010.

5.0 Sequential Circuits Fundamentals

5.1 Latches vs. Flip-Flops

5.2 Flip-Flop Types & Characteristics

• SR Flip-Flop (NOR/NAND):

  • NOR-based: $$\displaystyle S=1,R=0 $$ → $$\displaystyle Q=1 $$; $$\displaystyle S=0,R=1 $$ → $$\displaystyle Q=0 $$; $$\displaystyle S=R=0 $$ → no change; $$\displaystyle S=R=1 $$ → invalid.

  • NAND-based: Active-low inputs ($S',R'$), $$\displaystyle S'=R'=1 $$ no change, $$\displaystyle S'=R'=0 $$ invalid.

• JK Flip-Flop:

  • Eliminates invalid state: $$\displaystyle J=K=1 $$ toggles.

  • Master-Slave: Two latches (master on +ve clock, slave on -ve clock). Prevents race-around.

  • Characteristic Equation: $$\displaystyle Q_{next} = JQ' + K'Q $$

  • Excitation Table:

    | $$\displaystyle Q_n $$ | $$\displaystyle Q_{n+1} $$ | J | K | |-------|-----------|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | X | | 1 | 0 | X | 1 | | 1 | 1 | X | 0 |

• D Flip-Flop:

  • $$\displaystyle Q_{next} = D $$ (single input, no race).

  • Characteristic Equation: $$\displaystyle Q_{next} = D $$

  • Excitation: $$\displaystyle D = Q_{next} $$.

• T Flip-Flop:

  • Toggles when $$\displaystyle T=1 $$.

  • Characteristic Equation: $$\displaystyle Q_{next} = T \oplus Q $$

  • Excitation: $$\displaystyle T = Q \oplus Q_{next} $$.

5.3 Flip-Flop Conversion

• Convert by deriving input equations from excitation table.

• Example: SR to JK

  • From JK excitation: $$\displaystyle J=1,K=1 $$ → toggle → need $$\displaystyle S=1,R=1 $$? But SR invalid.

  • Actual: $$\displaystyle S = JQ' $$, $$\displaystyle R = KQ $$ (ensures $$\displaystyle S=R=0 $$ when $$\displaystyle J=K=1 $$).

6.0 State Machine Design

6.1 Fundamental Definitions

• State Diagram: Circles (states) with labeled transitions (input/output).

  • Moore: Output depends only on present state.

  • Mealy: Output depends on present state and input.

• State Table: Columns: Present State (PS), Input (X), Next State (NS), Output (Z).

• State Equation: Boolean expression for $NS$ in terms of $PS$ and $X$.

• State Assignment: Binary (natural), Gray (minimize transitions), One-hot (one FF per state).

6.2 Analysis & Design Procedure

1. Design from Spec:

   • Draw state diagram (Moore/Mealy).

   • Choose state assignment.

   • Create state table.

   • Derive excitation equations (using JK/D/T tables).

   • Draw logic diagram.

2. Analysis of Given Circuit:

   • Write flip-flop input equations and output equation.

   • Create state table (list all PS, compute NS, output).

   • Draw state diagram.

7.0 Counters

7.1 Asynchronous (Ripple) Counters

• 4-bit UP Counter: FF0 toggles on every clock. FF1 toggles on FF0's 1→0 transition (negative edge). FF2 on FF1's 1→0, etc.

• Waveform: Each FF delayed by flip-flop propagation → ripple.

• Timing Issue: Cumulative delay limits speed.

7.2 Synchronous Counters

• All FFs clocked simultaneously.

• Design Steps:

  1. State diagram (sequence).

  2. State table (PS, NS).

  3. Choose FF (JK/D/T). Use excitation table to find input equations.

  4. Simplify equations (K-map).

  5. Draw circuit.

• Example: 0-1-2-4-5-6-0 (3-bit)

  • States: 000,001,010,100,101,110.

  • Use JK FFs: $$\displaystyle J=K=NS \oplus PS $$ for each bit.

7.3 Special Counter Types

• Ring Counter: $n$ FFs in shift register, output of last FF fed to first. Only one '1' circulates.

  • Waveform: Single pulse rotates.

• Johnson (Twisted Ring) Counter: Complement of last FF output fed to first.

  • n-bit: $2n$ states. Sequence: 000...0 → 111...1 → 011...1 → ... → 100...0.

• BCD Counter (Decade): Counts 0–9, then resets to 0.

  • Use detection: when state = 1010 (10), async clear or preset to 0000.

7.4 Counter Applications & Decoding

• Decoding: Generate one-hot pulse for each state.

  • Combinational Decoder: Outputs = $f(\text{state bits})$.

  • Glitch Issue: Asynchronous counters cause glitches. Use registered outputs (FF outputs) or synchronous counters.

  • Example: 3-bit counter, decode state 5 (101): $$\displaystyle Y_5 = Q_2 Q_0' $$.

8.0 Shift Registers

8.1 Basic Types & Operations

8.2 Directional Shift Registers

• Shift Right: $$\displaystyle Q_i^{next} = Q_{i-1} $$ (MSB gets SI).

• Shift Left: $$\displaystyle Q_i^{next} = Q_{i+1} $$ (LSB gets SI).

• Mode Control: $$\displaystyle S=0 $$: shift right; $$\displaystyle S=1 $$: shift left.

8.3 Universal Shift Register

• Control Inputs: $$\displaystyle S_1, S_0 $$ (00: hold, 01: shift right, 10: shift left, 11: parallel load), $SHIFT/\overline{LOAD}$.

• Block Diagram:

  
  Parallel Data (D3..D0) → MUXes → FFs → Outputs Q3..Q0
  
  SI, SO for shift.
  
  

9.0 Memory Devices

9.1 Read-Only Memory (ROM)

• Internal Organization: Decoder (AND array) → OR array (fuse-based).

  • Address lines → Decoder → Word lines → OR gates → Data outputs.

• Types:

  • PROM: Programmable once (fuse blow).

  • EPROM: Erasable by UV light.

  • EEPROM: Electrically erasable byte-wise.

  • Flash: Block-wise erase, non-volatile.

• ROM as Combinational PLD: Fixed AND, programmable OR.

9.2 Random Access Memory (RAM)

• SRAM (Static): 6-transistor cell (bistable). Fast, power-hungry, volatile.

• DRAM (Dynamic): 1-transistor + 1-capacitor. Needs refresh (every few ms). Dense, slow.

• Read/Write Cycles:

  • Control Signals: $\overline{CS}$ (Chip Select), $\overline{WE}$ (Write Enable), $\overline{OE}$ (Output Enable).

  • Write: $$\displaystyle \overline{CS}=0 $$, $$\displaystyle \overline{WE}=0 $$, address stable, data in.

  • Read: $$\displaystyle \overline{CS}=0 $$, $$\displaystyle \overline{WE}=1 $$, $$\displaystyle \overline{OE}=0 $$, address stable, data out after $$\displaystyle t_{access} $$.

9.3 Memory Organization & Decoding

• Two-Dimensional (2D) Decoding:

  • Split address lines into row ($$\displaystyle A_r $$) and column ($$\displaystyle A_c $$).

  • Row decoder selects word line (activates entire row).

  • Column decoder selects specific bits within word.

  • Advantage: Reduces decoder size (e.g., 1K×8: 10 address lines → 5 for row, 5 for column → two 32× decoders instead of one 1024×).

  • Address Mapping: $$\displaystyle Address = Row\_bits \parallel Column\_bits $$.

10.0 Programmable Logic Devices (PLDs)

10.1 Combinational PLDs

• PLA (Programmable Logic Array):

  • Both AND and OR planes programmable.

  • Implements SOP: Product terms (AND) → Sum terms (OR).

  • Flexible but slower (two programmable fuses).

  • Example: Implement $$\displaystyle F_1 = \Sigma m(3,5,7) $$, $$\displaystyle F_2 = \Sigma m(4,5,7) $$ with 3 inputs, 3 product terms.

• PAL (Programmable Array Logic):

  • Programmable AND plane, Fixed OR plane.

  • Faster than PLA (only one programmable fuse per output).

  • Each OR gate gets fixed set of product terms.

  • Comparison: PAL faster, less flexible; PLA more flexible, slower.

10.2 Sequential PLDs

• Basic Microcell: Flip-flop (register) + combinational logic (AND/OR array).

• Operation: Next state from combinational logic, stored in FF on clock. Output from FF or combinational logic.

• Sequential Programmable Devices: PLD with registered outputs (e.g., PAL with flip-flops).

11.0 Data Conversion Circuits

11.1 Digital-to-Analog Converter (DAC)

• R-2R Ladder DAC:

  • Circuit: Repeated R and 2R resistors, switches controlled by digital bits.

  • Operation: Each bit controls a current into summing node. Output voltage $$\displaystyle V_o = -\frac{R_f}{R} \cdot (D_{n-1}2^{n-1} + ... + D_0 2^0) \cdot V_{ref} $$.

  • Advantages: Only two resistor values, easy to fabricate, good accuracy.

  • Disadvantage: Switch resistance mismatch causes nonlinearity.

11.2 Analog-to-Digital Converter (ADC)

• Successive Approximation ADC (SAR):

  • Block Diagram: SAR register, comparator, DAC, control logic.

  • Operation Steps:

    1. Set MSB of SAR to 1, others 0 → DAC output.

    2. Compare with analog input.

    3. If $$\displaystyle V_{DAC} > V_{in} $$, clear MSB; else keep.

    4. Repeat for next bit (down to LSB).

    5. After $n$ cycles, SAR holds digital equivalent.

  • Timing: $n$ clock cycles for $n$-bit conversion.

  • Advantages: Fast (medium), good accuracy, no integrator drift.

  • Disadvantages: Conversion time proportional to bits, glitches from DAC.

12.0 Special Topics & Short Notes

12.1 Error Detection & Correction (Parity Method)

• Parity Bit: Extra bit to make total number of 1s even (even parity) or odd (odd parity).

• Generator: XOR all data bits. For even parity, $$\displaystyle P = D_1 \oplus D_2 \oplus ... $$. For odd, invert.

• Checker: XOR all received bits (including parity). Output 0 (even) or 1 (odd) indicates error.

• Limitation: Detects only single-bit errors. Cannot correct, only detect.

12.2 BCD Adder

• Design: Two 4-bit binary adders + correction logic.

• Correction Condition: If $$\displaystyle C_{out} = 1 $$ or $$\displaystyle S_3 S_2 = 1 $$ (sum > 9), add 6 (0110) to sum.

• Circuit: Use second 4-bit adder to add 6 when correction needed.

12.3 Decoding in Counters

• Purpose: Generate one-shot pulse for each count state (e.g., for timing, control).

• Circuit: Combinational decoder with counter outputs as inputs.

• Glitch Issue: Asynchronous counters have glitches during state transitions. Use synchronous counters or decode registered outputs (FF outputs) to avoid.

• Example: 3-bit synchronous counter, decode state 5: $$\displaystyle Y_5 = Q_2 Q_1' Q_0 $$.

12.4 Two-Dimensional Memory Decoding

• Scheme: Split address into row ($r$ bits) and column ($c$ bits).

• Decoders: Row decoder ($$\displaystyle 2^r $$ outputs), Column decoder ($$\displaystyle 2^c $$ outputs).

• Memory Cell Activation: Cell at $(i,j)$ selected when row line $$\displaystyle R_i=1 $$ and column line $$\displaystyle C_j=1 $$ (via AND gate).

• Advantage: Reduces decoder complexity from $$\displaystyle 2^{r+c} $$ to $$\displaystyle 2^r + 2^c $$ inputs.

12.5 Sequential Programmable Devices (Microcell)

• Structure: One flip-flop + one programmable logic block (AND-OR array).

• Inputs: Data inputs, feedback from FF output.

• Outputs: FF output (registered) or combinational output.

• Operation: Next state computed from inputs and present state, stored on clock edge.

Final Exam Tips:

1. Number Conversions: Always verify by converting back. For mixed-radix, compute decimal first.

2. K-Map: Draw carefully, label axes, include don't cares as 'X'.

3. Flip-Flops: Memorize characteristic equations and excitation tables.

4. Counters: For synchronous design, always start with state table and excitation equations.

5. PLA/PAL: Draw block diagram with AND/OR planes clearly.

6. Timing Diagrams: For counters/shift registers, show clock, FF outputs, and any control signals.