EX-403 RGPV B.Tech

Digital Electronics Logic Design (DELD)

Previous year papers and the official syllabus are free to read, no account needed.

Previous Year Papers

6 papers, latest Dec 2025

Free

Topics as the official RGPV syllabus lists them.

Unit 1 Number Systems and Codes 6

Digital number systems, base conversion, binary, decimal, octal, hexadecimal, number system with radix r, Gray codes
Alphanumeric codes – ASCII code and BCD codes, concept of parity, complement r's & (r‑1)'s, subtraction with complements, signed binary numbers, error detecting & correcting codes
Basic theorems and properties of Boolean algebra: AND, OR, NOT operators, Boolean algebra laws, De Morgan’s theorem, Boolean expression & logic diagram
Negative logic, alternate logic‑gate representation (bubbled gates), canonical and standard forms (minterms & maxterms), sum‑of‑minterms and product‑of‑maxterms conversion
Truth tables and Karnaugh maps for 2‑, 3‑, 4‑, 5‑ and 6‑variable functions, solving digital problems using maps, don’t‑care conditions, tabular minimisation
Sum‑of‑products and product‑of‑sums reduction, exclusive‑OR & exclusive‑NOR circuits, parity generator & checker design

Unit 1 notes

Unit 2 Combinational Circuits 8

Design procedure for combinational logic
Half‑adder, full‑adder, half‑subtractor, full‑subtractor and code‑converter designs
Analysis of design using universal building blocks
Implementation of any logic function using only NAND gates or only NOR gates
Binary serial adder, parallel adder, serial/parallel adder, look‑ahead carry generator, BCD adder
Binary multiplier and magnitude comparator designs
Decoder, demultiplexer, encoder, priority encoder implementations
Multiplexer design and implementation of combinational logic diagrams

Unit 2 notes

Unit 3 Sequential Logic Circuits 5

Latches: SR latch (NAND & NOR), D latch, edge‑triggered flip‑flops, JK flip‑flop, T flip‑flop, master‑slave flip‑flop
Analysis of clocked sequential circuits: state tables, state diagrams, state reduction, state equations, state assignments
Flip‑flop excitation tables and characteristic equations
Design procedure for sequential circuits using state reduction
Applications of flip‑flops in sequential logic design

Unit 3 notes

Unit 4 Registers and Counters 4

Asynchronous and synchronous counters, modulus counters, down counters, up/down counters, ripple‑counter propagation delay
Programmable counters, presettable counters, BCD counters, cascading counters, counter applications and decoding glitches
Ring counter, Johnson counter, rotate‑left and rotate‑right counters
Registers: buffer register, shift‑left, shift‑right, bidirectional shift registers, parallel‑in‑parallel‑out, serial‑in‑serial‑out, parallel‑in‑serial‑out, serial‑in‑parallel‑out registers

Unit 4 notes

Unit 5 Memory and Converters 4

Random Access Memory (RAM): timing waveform, memory decoding, internal construction, coincident decoding, address multiplexing
Read‑Only Memory (ROM) implementation, types of ROMs, combinational PLDs, Programmable Logic Array (PLA), Programmable Array Logic (PAL), sequential programmable devices
Analog‑to‑Digital conversion techniques: ramp, dual‑slope, integrating, successive‑approximation, parallel, serial, converter specifications
Digital‑to‑Analog conversion techniques: binary‑weighted and R/2R DACs

Unit 5 notes

Counted from 6 past EX-403 papers.

Average marks of the questions from each unit in one paper. You answer only some of them, so the total is more than the paper’s maximum.

Convert numbers between decimal, binary, octal and hexadecimal, including fractional parts.

Asked 5 times: 2026, 2025, 2022, 2020
Explain the principle of operation / working of a successive approximation ADC.

Asked 4 times: 2025, 2023, 2020, 2019
Simplify/minimize a 4-variable Boolean function in SOP form $\Sigma m$ (with don't-care conditions $d$ where given) using K-map and implement with logic gates.

Asked 4 times: 2026, 2024, 2020, 2019