EX-403 Digital Electronics and Logic Design (DELD) - Nov 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aDesign 3-bit data even parity generator and checker.
   How to answer

   • Define even parity for 3-bit data.
   • Truth table for generator (3 inputs, 1 parity output) and checker (4 inputs, error output).
   • Simplified Boolean expressions using K-map.
   • Logic diagram using XOR gates.
2. 7 Marks
   bSimplify following Boolean expressions: (i) $F(A,B,C,D) = \Pi M(0,1,2,3,4,5,6,7,9,11)$ Using K-map.
   How to answer

   • Plot 4-variable K-map for maxterms given.
   • Group 0s for POS simplification.
   • Derive simplified POS expression.
   • Draw simplified logic diagram if required.
3. 7 Marks
   aMinimize the following functions by Tabular method- $F(A,B,C,D) = \Sigma m(1,3,7,11,15) + \Sigma d (0,2,5)$
   How to answer

   • List minterms and don't cares in binary and group by weight.
   • Perform Quine-McCluskey tabular combination to get prime implicants.
   • Construct prime implicant chart and select essential primes.
   • Write minimal SOP expression.
4. 7 Marks
   bGive the general procedure with example for converting a multilevel AND-OR diagram into an all NAND diagram.
   How to answer

   • State rule for replacing AND-OR with NAND-NAND.
   • Steps: keep AND-OR structure, convert gates, add bubbles/inverters.
   • Handle multilevel inversions and single literals.
   • Illustrate with example diagram before and after conversion.
5. 7 Marks
   aDesign Full-Adder using 2-half adder and an OR gate.
   How to answer

   • Recall half-adder sum and carry equations.
   • Combine two half-adders for sum of three bits.
   • OR the two half-carries for final carry.
   • Show block diagram using 2 half-adders and OR gate.
6. 7 Marks
   bDesign 4 input priority encoder using combinational gates.
   How to answer

   • Define priority encoder truth table for 4 inputs.
   • Derive output equations for valid priority.
   • Implement using basic AND, OR, NOT gates.
   • Show logic diagram.
7. 7 Marks
   aFor the Function $F(A,B,C,D) = \Sigma m (0, 1, 3, 4, 7, 8, 9, 11, 14, 15)$, define multiplexers implement using

   1. i)$4 \times 1$ MUX
   2. ii)$2 \times 1$ MUX
   How to answer

   • Express F(A,B,C,D) in terms of select lines.
   • Design implementation table for 4x1 MUX stages.
   • Show cascading for 2x1 MUX implementation.
   • Draw MUX-based logic diagrams.
8. 7 Marks
   bDraw the clocked Master-Slave J-K flip-flop configuration and explain how it removes race-around condition in J-K flip-flops?
   How to answer

   • Draw master-slave JK with two SR latches and clock/inverted clock.
   • Explain master enabled on one level, slave on opposite.
   • Show how feedback is broken to avoid multiple toggling.
   • Explain removal of race-around condition.
9. 7 Marks
   aDifferentiate between Latch and Flip-Flop. Analyzing the synchronous sequential circuit, where input and output equation are- $J_A = x, J_B = x, K_A = B', K_B = A$, find- Logic diagram, state table, state equation, state diagram.
   How to answer

   • Differentiate latch (level-sensitive) vs flip-flop (edge-sensitive).
   • Draw logic diagram from J_A=x, J_B=x, K_A=B', K_B=A equations.
   • Form state table, state equations and state diagram.
   • Explain analysis steps.
10. 7 Marks
    bConvert the SR F-F to JK F-F.
    How to answer

    • Write excitation tables for SR and JK flip-flops.
    • Derive S,R in terms of J,K and present state.
    • Simplify using K-map to get conversion logic.
    • Draw conversion diagram with combinational logic.
11. 7 Marks
    aDesign a synchronous counter using JK flip-flop for the following input sequences : 0-1-2-4-5-6-0
    How to answer

    • Determine number of flip-flops for states 0,1,2,4,5,6.
    • Draw state diagram and excitation table using JK excitation.
    • Simplify J,K inputs with K-maps.
    • Draw final counter logic diagram.
12. 7 Marks
    bWith the help of diagram, explain the operation of universal shift register.
    How to answer

    • Show 4-bit universal shift register block with MUXs and D flip-flops.
    • Explain mode control S1,S0 for hold, shift-left/right, parallel load.
    • Describe operation for each mode.
    • Give neat diagram.
13. 7 Marks
    aExplain Moore type of synchronous sequential machine (FSM) using block diagram and suitable example.
    How to answer

    • Define Moore machine where output depends only on state.
    • Show block diagram with combinational, state register, output decoder.
    • Give suitable example with state diagram/table.
    • Contrast briefly with Mealy if needed.
14. 7 Marks
    bRealize the full adder circuit using the PAL.
    How to answer

    • Write full-adder sum and carry SOP expressions.
    • Show PAL AND-OR programmable structure.
    • Map sum and carry product terms to PAL.
    • Draw programmed PAL diagram.
15. 7 Marks
    aDraw the basic circuit of a ROM cell and explain its working.
    How to answer

    • Draw basic ROM cell with word/bit lines and transistor/diode.
    • Explain address decoding and bit storage.
    • Describe read operation.
    • Show array organization briefly.
16. 7 Marks
    bWith a neat diagram explain the operation of R-2R DAC.
    How to answer

    • Draw R-2R ladder with R and 2R resistors and switches.
    • Explain binary-weighted current division.
    • Derive analog output voltage expression.
    • Explain operation for digital input example.