UNIT 3: Digital Electronics Logic Design – Short Notes

Based on RGPV Past Papers (Jun 2025 – Jun 2022)

I. Number Systems and Code Conversions

Base Conversions

• Decimal to Binary (Integer Part): Repeated division by 2, remainders read bottom-up.

• Decimal to Binary (Fraction Part): Repeated multiplication by 2, integer parts read top-down.

• Binary to Decimal: Sum of $$\displaystyle bit \times 2^{position} $$.

• Between Non-Decimal Bases: Convert via decimal as intermediate.

• Octal ↔ Binary: 1 octal digit = 3 binary bits (group bits in 3s from right).

• Hex ↔ Binary: 1 hex digit = 4 binary bits (group bits in 4s from right).

[!TIP] For fractional conversion in non-decimal bases (e.g., base-6 to base-8), convert fractional part to decimal first, then to target base.

Binary ↔ Gray Code

• Binary to Gray: MSB same; each next Gray bit = XOR of current binary bit and previous binary bit.

$$G_i = B_i \oplus B_{i+1} \quad (\text{with } B_{n+1}=0)$$

• Gray to Binary: MSB same; each next binary bit = XOR of current Gray bit and previous binary bit.

$$B_i = G_i \oplus B_{i+1}$$

BCD, ASCII, Excess-3

• BCD (8421): 4-bit binary for decimal 0–9; invalid for 10–15.

• Excess-3: BCD + 3 (0011). Self-complementing for 9’s complement.

• ASCII: 7-bit code (0–127). Example: ‘B’ = $$\displaystyle 1000010_2 $$.

Parity Generation & Checking

• Even Parity: Extra bit = 1 if odd number of 1s in data; makes total 1s even.

• Odd Parity: Extra bit = 1 if even number of 1s; makes total 1s odd.

• Error Detection: Transmitter adds parity bit; receiver checks parity. Mismatch → error.

• Example: ASCII ‘B’ = $$\displaystyle 1000010_2 $$ (three 1s).

  • Even parity bit = 1 → transmitted byte: $$\displaystyle 11000010_2 $$.

  • Odd parity bit = 0 → transmitted byte: $$\displaystyle 01000010_2 $$.

II. Boolean Algebra and Function Minimization

Boolean Laws & Theorems

De Morgan’s for n Variables

• Two variables: $$\displaystyle (A+B)'=A'B' $$, $$\displaystyle (AB)'=A'+B' $$.

• Three variables: $$\displaystyle (A+B+C)'=A'B'C' $$, $$\displaystyle (ABC)'=A'+B'+C' $$.

• Complement of Function: Replace $+$ with $\cdot$, $\cdot$ with $+$, and complement each literal/variable.

Karnaugh Map (K-map)

• Plotting: Minterms (Σm) → 1s; Maxterms (ΠM) → 0s; Don’t cares (d) → X.

• Grouping Rules:

  • Groups of $$\displaystyle 2^n $$ (1,2,4,8,…).

  • Adjacent (including wrap-around).

  • Largest possible, fewest groups.

  • Don’t cares can be included if helpful.

• Minimal SOP: Each group gives a product term; literals absent in group.

• Minimal POS: Each group of 0s gives a sum term; literals absent in group.

Quine-McCluskey (Tabulation) Method

1. List minterms in binary, group by number of 1s.

2. Combine adjacent groups differing in 1 bit → mark combined terms.

3. Repeat until no more combinations → prime implicants.

4. Prime Implicant Chart: Minterms vs prime implicants.

5. Essential Prime Implicants: Cover minterms not covered by others.

6. Minimal Cover: Select essential + minimal additional to cover all minterms.

7. With Don’t Cares: Treat as optional in chart.

[!TIP] Multiple minimal expressions possible if non-essential prime implicants have choices.

III. Combinational Logic Design

A. Universal Gates

• NAND as Universal:

  • NOT: $$\displaystyle A' = A \uparrow A $$

  • AND: $$\displaystyle AB = (A \uparrow B)' $$

  • OR: $$\displaystyle A+B = (A' \uparrow B')' $$

  • NOR: $$\displaystyle A+B = (A \uparrow A) \uparrow (B \uparrow B) $$

  • XOR: $$\displaystyle A\oplus B = (A \uparrow (A \uparrow B)) \uparrow (B \uparrow (A \uparrow B)) $$

• NOR as Universal: Similar transformations.

B. Arithmetic Circuits

Half Adder

• $$\displaystyle Sum = A \oplus B $$, $$\displaystyle Carry = AB $$.

Full Adder

• Design: Two half adders + OR gate.

$$S = A \oplus B \oplus C_{in}$$

$$C_{out} = AB + C_{in}(A \oplus B)$$

• Truth table standard.

BCD Adder

• Adds two BCD digits; if sum > 9 or carry out, add 6 (0110) for correction.

• Correction logic: $$\displaystyle Y = S_3S_2 + S_3S_1 $$ (for sum > 9).

Half Subtractor

• $$\displaystyle Diff = A \oplus B $$, $$\displaystyle Borrow = A'B $$.

C. Data Processing Circuits

Decoder

• n-to-$$\displaystyle 2^n $$ decoder: n inputs, $$\displaystyle 2^n $$ outputs, one active-high output per input combination.

• Enable logic: Active-low enable common.

• 3-to-8 Decoder: Use 2-to-4 decoders + inverter.

• Binary to Gray Decoder: Gray output = $$\displaystyle G_2 = B_2 $$, $$\displaystyle G_1 = B_2 \oplus B_1 $$, $$\displaystyle G_0 = B_1 \oplus B_0 $$.

Encoder

• $$\displaystyle 2^n $$-to-n encoder: Opposite of decoder; may have priority.

• 4-to-2 Priority Encoder: Highest-order input prioritized if multiple 1s.

  • $$\displaystyle Y_1 = I_3 + I_2 $$, $$\displaystyle Y_0 = I_3 + I_1' $$.

  • Valid output: $$\displaystyle V = I_3 + I_2 + I_1 + I_0 $$.

Multiplexer (MUX)

• 2-to-1: $$\displaystyle Y = \bar{S}A_0 + SA_1 $$.

• 4-to-1: $$\displaystyle Y = \bar{S_1}\bar{S_0}I_0 + \bar{S_1}S_0I_1 + S_1\bar{S_0}I_2 + S_1S_0I_3 $$.

• Implementing F(w,x,y,z):

  • Use variables as select lines.

  • For 4-variable function, 8:1 MUX: connect minterms to data inputs; unused inputs to 0/1/don’t care.

  • For 3-variable function with 4:1 MUX: use two variables as select, third variable (or its complement) to data inputs.

Demultiplexer (DeMUX)

• 1 input, n outputs; input directed to one output based on select lines.

D. Comparators & Code Converters

Magnitude Comparator (2-bit)

• $$\displaystyle A>B = A_1B_1' + A_1'A_0B_1' + A_0B_1'B_0' $$.

• $$\displaystyle A=B = (A_1 \oplus B_1)' (A_0 \oplus B_0)' $$.

• $$\displaystyle A<B = A_1'B_1 + A_1A_0'B_1' + A_1'A_0'B_0 $$.

IV. Sequential Logic: Latches and Flip-Flops

A. Latches

• SR Latch (NOR): Cross-coupled NOR gates. $$\displaystyle S=R=1 $$ invalid.

• D Latch: $$\displaystyle Q = D $$ when enable=1; holds when enable=0.

  • Level-triggered (transparent when enable high).

  • Truth table:

    | EN | D | Q(next) | |----|---|---------| | 0 | X | Q(prev) | | 1 | 0 | 0 | | 1 | 1 | 1 |

B. Flip-Flops

• Edge-triggered: Positive (↑) or negative (↓) clock transition.

• Master-Slave JK FF:

  • Race-around condition: In level-triggered JK with $$\displaystyle J=K=1 $$, output toggles continuously during clock high.

  • Removal: Master (positive level) and slave (negative level) in two stages; output changes only at negative edge.

  • Characteristic equation: $$\displaystyle Q^* = J\bar{Q} + \bar{K}Q $$.

  • Truth table:

    | J | K | Q(next) | |---|---|---------| | 0 | 0 | Q | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | $\bar{Q}$ |

Excitation Tables

Flip-Flop Conversion

• SR to JK: Add feedback: $$\displaystyle S = J\bar{Q} $$, $$\displaystyle R = KQ $$.

• JK to D: $$\displaystyle J = D $$, $$\displaystyle K = \bar{D} $$.

V. State Machine Design

Definitions

• State Diagram: Circles (states) with labeled transitions (input/output). Moore: output depends on state only; Mealy: output depends on state and input.

• State Table: Columns: Present State (PS), Input (X), Next State (NS), Output (Z).

• State Equation: Boolean expression for NS flip-flop inputs in terms of PS and inputs.

• State Assignment: Binary, Gray (adjacent states differ by 1 bit), One-hot (one FF=1 per state).

Design Procedure

1. State diagram → State table.

2. Choose state assignment.

3. For each FF, derive excitation equations from state table using excitation table.

4. Draw logic diagram with FF inputs and output logic.

5. Verify.

VI. Counters

A. Asynchronous (Ripple) Counters

• 4-bit Up Counter: FF0 toggles on every clock; FF1 toggles on FF0’s 1→0; etc.

• Propagation delay: $$\displaystyle t_{pd} \approx n \cdot t_{pd(FF)} $$ (n = number of FFs).

• Disadvantage: Cumulative delay; intermediate states may be decoded incorrectly.

B. Synchronous Counters

• Design Procedure:

  1. State diagram (sequence).

  2. State table (PS, NS).

  3. Excitation equations using JK/D/T tables.

  4. Logic circuit.

• Example: 4-bit synchronous up counter (JK):

  • $$\displaystyle J_0=K_0=1 $$, $$\displaystyle J_1=K_1=Q_0 $$, $$\displaystyle J_2=K_2=Q_1Q_0 $$, $$\displaystyle J_3=K_3=Q_2Q_1Q_0 $$.

• Up-Down Counter: Control $M$; $$\displaystyle J=K=Q' $$ for down, $$\displaystyle J=K=Q $$ for up; use MUX to select.

C. Special Counters

Ring Counter

• n-bit: Single 1 circulates; $n$ states.

• Self-decoding: Only one FF high at a time → directly drives displays.

• Waveform: 1 shifts right/left each clock.

Johnson (Twisted Ring) Counter

• n-bit: Inverted output of last FF fed to first.

• States: $2n$; sequence: 000…0 → 111…1 → 000…0.

• Example 4-bit: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, then repeat.

BCD (Decade) Counter

• Counts 0–9; resets to 0 after 9.

• JK Implementation: Reset when $$\displaystyle Q_3Q_0=11 $$ (i.e., state 1010–1111 invalid). Use NAND to clear FFs.

D. Decoding in Counters

• One-hot decoding: Each state has unique FF=1; use FF outputs directly as decoded signals.

• Application: 7-segment display driving (each digit has dedicated decoder).

VII. Registers and Shift Operations

Register Basics

• Register: Group of FFs storing n-bit word; parallel load capability.

• Shift Register Types:

  • SISO: Serial In, Serial Out.

  • SIPO: Serial In, Parallel Out.

  • PISO: Parallel In, Serial Out.

  • PIPO: Parallel In, Parallel Out (no shifting).

Universal Shift Register

• Control Inputs: $$\displaystyle S_1S_0 $$ (00=hold, 01=shift right, 10=shift left, 11=parallel load).

• Operation: Multiplexers at each FF input select between:

  • Left neighbor (shift left)

  • Right neighbor (shift right)

  • Parallel data input

  • Current state (hold)

• Timing: All FFs clocked simultaneously (synchronous).

Applications

• Serial communication: Convert parallel to serial (SIPO/PISO).

• Time delay: Fixed number of clock cycles delay (SISO).

• Data manipulation: Bit reversal, rotation.

VIII. Memory and Programmable Logic

A. Static RAM (SRAM)

• 6-transistor cell: Cross-coupled inverters + two access transistors.

• Read Cycle:

  1. Address applied, $$\displaystyle CS=0 $$, $$\displaystyle WE=1 $$, $$\displaystyle OE=0 $$.

  2. Data appears on $DQ$ after $$\displaystyle t_{access} $$.

• Write Cycle:

  1. Address applied, $$\displaystyle CS=0 $$, $$\displaystyle WE=0 $$, data on $DQ$.

  2. Data written after $$\displaystyle t_{setup} $$.

• Timing: $$\displaystyle t_{access} < t_{cycle} $$; $OE$ controls output enable.

B. ROM

• Types:

  • Mask ROM: Programmed during fabrication.

  • PROM: One-time programmable (fuse links).

  • EPROM: UV erasable, electrically programmable.

  • EEPROM: Electrically erasable/programmable.

  • Flash: Block erase, high density.

• Organization: $$\displaystyle 2^n $$ words × m bits; address lines select word, data lines output.

• Cell: Typically a transistor with/without fuse.

C. Memory Decoding

• Two-dimensional: Use row and column decoders to reduce decoder size.

  • Example: 1K×8 RAM → 10 address lines → 10-to-1024 decoder large; instead: 5-bit row decoder × 5-bit column decoder.

• Chip Select (CS) Logic: Multiple chips; decode high-order address bits to enable specific chip.

D. Programmable Logic Devices (PLDs)

PLA (Programmable Logic Array)

• Both AND and OR arrays programmable.

• Implementation:

  1. Generate all product terms (AND array programmable).

  2. Program OR array to sum required product terms for each output.

• Example: $$\displaystyle F_1 = \Sigma m(0,1,3,5) $$, $$\displaystyle F_2 = \Sigma m(1,3,5,7) $$ → share product terms.

PAL (Programmable Array Logic)

• AND array programmable, OR array fixed.

• Faster than PLA due to fixed OR.

• Example: Full adder:

  • $$\displaystyle S = \bar{A}\bar{B}C + \bar{A}B\bar{C} + A\bar{B}\bar{C} + ABC $$

  • $$\displaystyle C_{out} = AB + BC + AC $$

  • Implement with 3 product terms per output.

Sequential PLDs

• Include flip-flops and feedback paths.

• Microcell: AND-OR logic + FF output feedback to AND array.

IX. Data Conversion Circuits

A. Digital-to-Analog Converter (DAC)

R-2R Ladder DAC

• Operation: Binary-weighted current division.

• Advantages: Uses only two resistor values (R and 2R); no precision resistors needed for weights.

• Output Voltage:

$$V_{out} = -\frac{R_f}{R} \cdot V_{ref} \cdot \left( \frac{b_0}{2} + \frac{b_1}{4} + \cdots + \frac{b_{n-1}}{2^n} \right)$$

(for n-bit, MSB first).

Weighted Resistor DAC (brief)

• Each bit controls a resistor of value $$\displaystyle R/2^i $$; op-amp sums currents.

• Disadvantage: Wide resistor range for high bits.

B. Analog-to-Digital Converter (ADC)

Successive Approximation ADC

• Components: SAR register, comparator, DAC, control logic.

• Steps:

  1. Set SAR MSB=1, others=0 → DAC output = $$\displaystyle V_{ref}/2 $$.

  2. Compare with $$\displaystyle V_{in} $$: if $$\displaystyle V_{in} \ge V_{DAC} $$, keep MSB=1; else clear.

  3. Repeat for next bit (halving step each time).

• Timing: n clock cycles for n-bit conversion.

• Advantages: Fast (medium), moderate cost.

• Disadvantages: Conversion time depends on bits; not as fast as flash.

Flash ADC (brief)

• Parallel comparators ($$\displaystyle 2^n-1 $$ for n-bit).

• Fastest but expensive and power-hungry.

X. Additional Topics (From Past Papers)

Parity Generator and Checker Design (n-bit)

• Even Parity Generator: $$\displaystyle P = b_0 \oplus b_1 \oplus \cdots \oplus b_{n-1} $$.

• Checker: Received bits + parity bit → XOR all; result 0 → no error.

• Circuit: XOR tree.

Asynchronous vs Synchronous Counters

Timing Parameters in Flip-Flops

• Setup time ($$\displaystyle t_{su} $$): Data must be stable before clock edge.

• Hold time ($$\displaystyle t_h $$): Data must be stable after clock edge.

• Violation → metastability.

Error Detection Beyond Parity

• Not covered in RGPV past papers for this unit.

Key Formulas & Equations

• Gray conversion: $$\displaystyle G = B \oplus (B \gg 1) $$

• K-map grouping: $$\displaystyle \boxed{\text{Group size } = 2^n} $$

• Quine-McCluskey complexity: $$\displaystyle \boxed{O(3^n \cdot n)} $$ worst-case

• Full Adder: $$\displaystyle \boxed{S = A \oplus B \oplus C_{in},\quad C_{out} = AB + C_{in}(A \oplus B)} $$

• JK FF characteristic: $$\displaystyle \boxed{Q^* = J\bar{Q} + \bar{K}Q} $$

• R-2R DAC: $$\displaystyle \boxed{V_{out} = -\frac{R_f}{R} V_{ref} \sum_{i=0}^{n-1} \frac{b_i}{2^{n-i}}} $$

[!TIP] For design questions, always draw state diagram/table first, then assign states, derive excitation equations, and finally logic circuit. Use one-hot for fewer FFs in small state machines.