UNIT 1: Digital Electronics Logic Design - Exam-Focused Notes

Based on rigorous analysis of RGPV past papers (2022-2025). These notes are structured for maximum exam impact.

1.0 NUMBER SYSTEMS, CODES & CONVERSIONS (Very High Frequency)

1.1 Base Conversion Techniques

• Core Principle: Positional number system. Value = Σ (digit × base^position).

• Integer Conversion (Any Base → Decimal): Multiply each digit by its positional weight and sum.

  • Example: $$\displaystyle (1011.101)_2 = 1×2^3 + 0×2^2 + 1×2^1 + 1×2^0 + 1×2^{-1} + 0×2^{-2} + 1×2^{-3} = 11.625_{10} $$

• Fractional Conversion (Decimal → Any Base): Repeated multiplication by new base. Integer part of each product is the digit.

  • Example: $$\displaystyle (0.625)_{10} → (0.101)_2 $$: $$\displaystyle 0.625×2=1.25 $$ (1), $$\displaystyle 0.25×2=0.5 $$ (0), $$\displaystyle 0.5×2=1.0 $$ (1).

• Conversion Between Non-Decimal Bases (e.g., Hex to Octal): Best Practice: Convert via Binary.

  1. Convert each hex digit to 4-bit binary.

  2. Group binary bits into 3-bit groups (for octal) from the binary point.

  3. Convert each 3-bit group to octal digit.

  • Exam Tip: This two-step method is foolproof and faster for exams.

1.2 Binary Coded Decimal (BCD) & Excess-3 Code

• BCD (8421 Code): Each decimal digit (0-9) represented by its 4-bit binary equivalent.

  • Invalid Codes: 1010 to 1111 are not valid BCD.

  • Conversion: Direct digit-to-4-bit mapping. $$\displaystyle (259)_{10} → (0010 0101 1001)_{BCD} $$.

• Excess-3 Code: BCD code + 3 (0011). Self-complementing property (9's complement of a decimal digit = 1's complement of its Excess-3 code).

  • Conversion: Add 3 (0011) to each BCD digit. $$\displaystyle (2)_{BCD}=0010 → 0010+0011=0101 $$ (Excess-3 for 2).

1.3 Gray Code

• Property: Only one bit changes between consecutive codes. Used in K-maps, shaft encoders, error correction.

• Binary → Gray:

  1. MSB of Gray = MSB of Binary.

  2. Each subsequent Gray bit = XOR of current binary bit and previous binary bit.

  • $$\displaystyle G_i = B_i \oplus B_{i+1} $$ (where $$\displaystyle B_{i+1} $$ is the bit to the left).

  • Example: Binary 1011 → Gray 1110.

• Gray → Binary:

  1. MSB of Binary = MSB of Gray.

  2. Each subsequent Binary bit = XOR of current Gray bit and previously calculated Binary bit.

  • $$\displaystyle B_i = G_i \oplus B_{i-1} $$.

1.4 Error Detection Codes - Parity

• Concept: Add a single parity bit to a data word to make total number of 1's even (Even Parity) or odd (Odd Parity).

• Generator Circuit: XOR tree of all data bits. Output is parity bit.

  • $$\displaystyle P_{even} = D_1 \oplus D_2 \oplus ... \oplus D_n $$

  • $$\displaystyle P_{odd} = \overline{D_1 \oplus D_2 \oplus ... \oplus D_n} $$

• Checker Circuit: XOR tree of all data bits and the received parity bit. Output 1 indicates error.

  • $$\displaystyle Check = P_{received} \oplus D_1 \oplus D_2 \oplus ... \oplus D_n $$

• Example (ASCII 'B'):

  • ASCII 'B' = $$\displaystyle 1000010_2 $$ (7 bits).

  • Even Parity: Count 1's = 2 (even). Parity bit P=0. Transmitted: 0 1000010.

  • Odd Parity: Count 1's = 2 (even). Need odd total → P=1. Transmitted: 1 1000010.

  • Limitation: Detects single-bit errors only. Cannot detect even-numbered bit errors.

2.0 BOOLEAN ALGEBRA & LOGIC SIMPLIFICATION (Very High Frequency)

2.1 Fundamental Concepts

• Basic Laws: Identity, Null, Idempotent, Inverse, Commutative, Associative, Distributive.

• De Morgan's Theorems (CRITICAL):

  • $$\displaystyle \overline{A+B} = \overline{A} \cdot \overline{B} $$

  • $$\displaystyle \overline{A \cdot B} = \overline{A} + \overline{B} $$

  • General Form (n variables): $$\displaystyle \overline{f(A_1, A_2, ..., A_n)} = f(\overline{A_1}, \overline{A_2}, ..., \overline{A_n}) $$ with operators swapped (AND↔OR).

  • Proof Method: Use truth tables for 2/3 variables. Show LHS and RHS columns identical.

• Complement of a Function: Apply De Morgan's: 1) Invert all inputs, 2) Swap operators (AND/OR), 3) Invert output.

2.2 Simplification Methods

• Karnaugh Map (K-Map): Graphical minimization. Golden Rule: Adjacent cells differ by only one bit.

  • Grouping Rules: Groups of $$\displaystyle 2^n $$ cells (1,2,4,8...). Each group eliminates one variable. Groups can overlap. Wrap-around allowed.

  • SOP Minimization: Group 1's → write product terms → sum them.

  • POS Minimization: Group 0's → write sum terms → product of sums.

  • "Don't Care" Conditions ($\Sigma d$ / $\Pi d$): Treat as 1 for SOP (to enlarge groups) or 0 for POS. Can be included or excluded to maximize grouping.

• Quine-McCluskey (Tabulation) Method:

  1. List Minterms: Group by number of 1's.

  2. Combine: Compare adjacent groups. Differ by one bit → combine, replace differing bit with -. Mark combined terms.

  3. Prime Implicants: Unmarked terms from all iterations.

  4. Prime Implicant Chart: Rows = prime implicants, Columns = minterms. X marks coverage.

  5. Essential Prime Implicants: Columns with single X. Must be included in final cover.

  6. Selection: Use Petrick's method or chart reduction to select minimal set of remaining prime implicants to cover leftover minterms.

2.3 Gate-Level Implementation

• Universal Gates:

  • NAND Implementation:

    • NOT: A' = (A·A)' or single-input NAND.

    • AND: A·B = ((A·B)')'

    • OR: A+B = (A'·B')' (De Morgan)

    • NOR: (A+B)' = NAND of inverted inputs.

    • XOR: A⊕B = (A·B')' + (A'·B)' → NAND-NAND implementation.

  • NOR Implementation: Similar, using De Morgan's dual forms.

• Multilevel Conversion (AND-OR → All NAND):

  1. Ensure all bubbles (inversions) are at gate outputs.

  2. Replace each AND gate with NAND gate.

  3. Replace each OR gate with NAND gate (adds inversion at output, may need extra inversion at previous stage).

  • Rule of Thumb: If an OR gate has single-input bubbles → replace with NAND. If it has no bubbles → replace with NAND and add an inverter (or NAND as inverter) on its output.

3.0 COMBINATIONAL LOGIC DESIGN (High Frequency)

3.1 Arithmetic Circuits

• Half Adder (HA):

  • Inputs: A, B.

  • Outputs: Sum = $A \oplus B$, Carry = $A·B$.

  • Logic: 1 XOR gate, 1 AND gate.

• Full Adder (FA):

  • Inputs: A, B, $$\displaystyle C_{in} $$.

  • Outputs: Sum = $$\displaystyle A \oplus B \oplus C_{in} $$, $$\displaystyle C_{out} = AB + C_{in}(A \oplus B) $$.

  • Design using HA: $$\displaystyle Sum = HA1(A,B) \oplus C_{in} $$; $$\displaystyle C_{out} = HA1_{carry} + (HA1_{sum}·C_{in}) $$.

• Half Subtractor (HS):

  • Inputs: A, B.

  • Outputs: Diff = $A \oplus B$, Borrow = $\overline{A}·B$.

• Full Subtractor (FS):

  • Inputs: A, B, $$\displaystyle B_{in} $$.

  • Outputs: Diff = $$\displaystyle A \oplus B \oplus B_{in} $$, $$\displaystyle B_{out} = \overline{A}B + \overline{(A \oplus B)}B_{in} $$.

• n-bit Binary Adder/Subtractor (2's Complement):

  • Use n FAs.

  • Subtraction: $$\displaystyle A - B = A + (2's~complement~of~B) $$.

  • Control: $$\displaystyle C_0 = 1 $$ for subtraction (invert B bits via XOR with 1), $$\displaystyle C_0 = 0 $$ for addition. Final carry out is ignored for subtraction result.

3.2 Data Processing Circuits

• Multiplexer (MUX): $$\displaystyle 2^n:1 $$ selects one of $$\displaystyle 2^n $$ data inputs to output based on n select lines.

  • Implementing any Boolean function: Use $$\displaystyle 2^n:1 $$ MUX where n = number of variables. Connect inputs based on truth table (0/1 or variable/complement).

  • Example (3-var F): Use 8:1 MUX. Connect $$\displaystyle D_0...D_7 $$ to 0/1 based on F values for m0...m7. S2,S1,S0 as select.

• Demultiplexer (DEMUX): $$\displaystyle 1:2^n $$ routes single input to one of $$\displaystyle 2^n $$ outputs based on n select lines.

• Decoder: $$\displaystyle n:2^n $$ activates exactly one output (minterm) for each input combination. Enable input required.

  • Binary to Gray Decoder: Truth table maps binary input to Gray output. Implement with OR gates from K-map of each Gray bit.

• Encoder: $$\displaystyle 2^n:n $$ converts $$\displaystyle 2^n $$ inputs (one-hot) to n-bit binary code. Priority Encoder: If multiple inputs active, output code of highest-priority input.

• Magnitude Comparator (2-bit):

  • Outputs: $$\displaystyle A>B $$, $$\displaystyle A=B $$, $$\displaystyle A<B $$.

  • Logic: $$\displaystyle A=B $$ → $$\displaystyle A_1 \odot B_1 \cdot A_0 \odot B_0 $$. $$\displaystyle A>B $$ → $$\displaystyle A_1\overline{B_1} + (A_1 \odot B_1)A_0\overline{B_0} $$.

3.3 Programmable Logic Devices (PLDs) - Combinational

• PLA (Programmable Logic Array):

  • Structure: Programmable AND array → Programmable OR array.

  • Programming Table: Columns for input variables (and complements), product terms (P0, P1...), output functions (F1, F2...). Mark 1 for connections.

• PAL (Programmable Array Logic):

  • Structure: Programmable AND array → Fixed OR array (each OR gate has fixed inputs from specific AND terms).

  • Advantage: Faster than PLA due to fixed OR.

  • Implementation: Derive minimized SOP. Assign product terms to available OR gate inputs.

4.0 SEQUENTIAL LOGIC FUNDAMENTALS: FLIP-FLOPS & LATCHES (Very High Frequency)

4.1 Basic Memory Elements

• Latch: Level-triggered. Transparent when clock is active (HIGH for positive, LOW for negative). Changes output continuously with input during active clock level.

• Flip-Flop: Edge-triggered. Changes state only at the instant of clock edge (rising/falling). Master-Slave configuration uses two latches to achieve edge behavior.

• SR Latch (Basic):

  • Inputs: S (Set), R (Reset). Active HIGH.

  • Invalid State: S=R=1.

  • Characteristic Equation: $$\displaystyle Q_{next} = S + \overline{R}Q $$ (with constraint $$\displaystyle S·R=0 $$).

• D Latch:

  • Inputs: D (Data), E (Enable).

  • Operation: $$\displaystyle Q_{next} = D $$ when E=1 (transparent). Holds when E=0.

  • Equation: $$\displaystyle Q_{next} = E·D + \overline{E}·Q $$.

4.2 Edge-Triggered Flip-Flops

• Clock Triggering:

  • Positive Edge: Responds to LOW→HIGH transition.

  • Negative Edge: Responds to HIGH→LOW transition.

  • Master-Slave: Master latch (transparent when CLK=1) feeds slave latch (transparent when CLK=0). Output changes at falling edge for positive-level master.

• JK Flip-Flop:

  • Truth Table:

    | J | K | Q(t+1) | Action | |---|---|--------|--------| | 0 | 0 | Q(t) | No change | | 0 | 1 | 0 | Reset | | 1 | 0 | 1 | Set | | 1 | 1 | Q'(t) | Toggle |

  • Characteristic Equation: $$\displaystyle Q_{next} = J\overline{Q} + \overline{K}Q $$.

  • Excitation Table: (Q(t), Q(t+1)) → (J, K) inputs needed.

• D Flip-Flop:

  • Truth Table: $$\displaystyle D=0 → Q(t+1)=0 $$; $$\displaystyle D=1 → Q(t+1)=1 $$. No invalid state.

  • Characteristic Equation: $$\displaystyle Q_{next} = D $$.

  • Excitation Table: $$\displaystyle D = Q(t+1) $$.

• T Flip-Flop:

  • Truth Table: $$\displaystyle T=0 → Q(t+1)=Q(t) $$; $$\displaystyle T=1 → Q(t+1)=Q'(t) $$.

  • Characteristic Equation: $$\displaystyle Q_{next} = T \oplus Q $$.

  • Excitation Table: $$\displaystyle T = Q(t) \oplus Q(t+1) $$.

4.3 Flip-Flop Conversion

• SR FF to JK FF:

  • Problem: SR FF has invalid state S=R=1. JK FF needs J=K=1 for toggle.

  • Solution: Add two AND gates.

  • Equations: $$\displaystyle S = J \overline{Q} $$, $$\displaystyle R = K Q $$.

  • Operation: When J=K=1 → S=R=0 (no change) or S=R=1 (invalid) depending on Q. But with feedback, if Q=1 → S=0, R=1 (reset next state=0). If Q=0 → S=1, R=0 (set next state=1). Achieves toggle without invalid state.

5.0 SEQUENTIAL CIRCUIT ANALYSIS & DESIGN (High Frequency)

5.1 Fundamental Definitions

• State Diagram (FSM):

  • Moore Machine: Outputs depend only on present state. Outputs on state circles.

  • Mealy Machine: Outputs depend on present state and inputs. Outputs on transition arrows.

• State Table: Columns: Present State (PS), Inputs (X), Next State (NS), Outputs (Z).

• State Equation: Boolean equation for next state in terms of present state and inputs. Derived from excitation tables of chosen FF.

• State Assignment: Mapping of state names (A, B, C...) to binary codes (00, 01, 10...). One-hot assignment: n states → n FFs, only one FF=1 at a time. Simplifies design but uses more hardware.

5.2 Analysis Procedure (Given Logic Diagram)

1. Identify flip-flop type (JK, D, T) and count (n).

2. Write output equation(s) (Z = f(inputs, present state)).

3. Write state equations (D, J/K, T inputs) from the combinational logic driving FF inputs.

4. Construct state table:

   • List all combinations of PS (2^n rows) and inputs.

   • Compute NS using state equations.

   • Compute output Z using output equation.

5. Draw state diagram from state table.

5.3 Design Procedure (From State Diagram)

1. State Assignment: Assign binary codes to each state.

2. State Table: Expand diagram into table with PS, Inputs, NS, Outputs.

3. Choose Flip-Flop Type: (JK/D/T). Usually JK or D preferred.

4. Derive Excitation/Input Equations:

   • For D FF: $$\displaystyle D = NS $$ (directly from NS column).

   • For JK FF: Use JK excitation table to find (J,K) for each (PS, NS) combination. Create K-maps for J and K separately.

   • For T FF: $$\displaystyle T = PS \oplus NS $$.

5. Simplify Equations: Use K-maps or Quine-McCluskey.

6. Draw Logic Diagram: Connect combinational logic (from simplified equations) to FF inputs and outputs.

6.0 COUNTERS (Very High Frequency)

6.1 Classification & Terminology

• Asynchronous (Ripple) Counter: FF clock inputs driven by previous FF's Q' (or Q). Slow (ripple delay), simple.

• Synchronous Counter: All FF clocks tied to common clock signal. Fast, designed using combinational logic for FF inputs.

• Up/Down Counter: Counts up (00→01→10...) or down (11→10→01...). Direction controlled by input (UP/DOWN).

• Modulus (MOD-N): Counts N distinct states before repeating. n-bit binary counter is MOD-$$\displaystyle 2^n $$.

6.2 Design of Synchronous Counters (Using JK FF)

• General Steps:

  1. Draw state diagram for desired sequence.

  2. Create state table (PS, NS). For n FFs, list all 2^n possible PS (even unused states).

  3. Use JK excitation table to find required (J,K) inputs for each FF to go from PS to NS.

  4. Draw K-maps for each FF's J and K inputs (variables = present state bits).

  5. Simplify to get J-K equations.

  6. Draw circuit: Connect K-map outputs to respective J,K inputs. Connect all CLKs together.

• Custom Sequence Example (0-1-2-4-5-6-0):

  • States: 000, 001, 010, 100, 101, 110. Unused: 011, 111 → self-loop (J=K=0) to avoid hang-up.

• 4-bit Synchronous Up-Down Counter:

  • Control: UP=1 → count up; UP=0 → count down.

  • Logic: For each FF $$\displaystyle Q_i $$, its toggle condition depends on all lower bits.

    • Up: Toggle when all LSBs are 1. $$\displaystyle T_i = Q_0·Q_1·...·Q_{i-1}·UP $$

    • Down: Toggle when all LSBs are 0. $$\displaystyle T_i = \overline{Q_0}·\overline{Q_1}·...·\overline{Q_{i-1}}·\overline{UP} $$

  • Use T FFs with $$\displaystyle T_i $$ as above. OR the two conditions for up/down.

6.3 Special-Purpose Counters

• Ring Counter: n-bit shift register with Q' of last FF fed to D of first FF. Initialized with one '1'.

  • Sequence: 100...0 → 010...0 → 001...0 → ... → 100...0 (n states).

  • Modulus = n. Self-decoding (one-hot).

• Johnson (Twisted Ring) Counter: n-bit shift register with Q' of last FF fed to D of first FF.

  • Sequence: 000...0 → 100...0 → 110...0 → 111...0 → ... → 111...1 → 011...1 → 001...1 → 000...0.

  • Modulus = 2n. 50% duty cycle outputs possible. Used as frequency divider.

• BCD Counter (Decade Counter): Counts 0000 to 1001 (0-9) then resets to 0000. Synchronous design ensures reset to 0000 when state = 1010.

6.4 Decoding in Counters

• One-Hot Decoding: Each state has a dedicated output line (like ring counter). Glitch-free by design.

• Two-Hot (or more) Decoding: Standard binary counter. Decoder output may have glitches (short pulses) during state transitions because multiple bits change.

• Glitch-Free Output Generation:

  • Use static (level) outputs from flip-flops directly, not combinational decoder outputs.

  • Or use synchronous reset to force specific state.

  • For decoder outputs, ensure output is enabled only after clock edge (use FF output as enable).

7.0 SHIFT REGISTERS (High Frequency)

7.1 Types & Operations

• SISO (Serial In Serial Out): 4 D-FFs in chain. Serial input to first FF, output from last. 4 clock pulses to shift 4 bits in/out.

• SIPO (Serial In Parallel Out): Serial input to first FF. All FF outputs available in parallel after shift.

• PISO (Parallel In Serial Out): Parallel data loaded via D inputs (with load control). Serial output from last FF. Shift operation same as SISO.

• PIPO (Parallel In Parallel Out): All D inputs and Q outputs parallel. Load and read happen simultaneously with clock.

7.2 Bidirectional & Universal Shift Registers

• Bidirectional: Can shift Left (MSB→LSB) or Right (LSB→MSB). Uses multiplexers at each FF input to select either previous FF's output (shift) or parallel data input (load).

• Universal Shift Register (4-bit):

  • Control Inputs: S1 S0 (00=Hold, 01=Shift Right, 10=Shift Left, 11=Parallel Load).

  • Structure: Each FF's D input comes from a 4:1 MUX.

    • MUX Input 0: Q (Hold)

    • MUX Input 1: Q_{i-1} (Shift Right, for i>0)

    • MUX Input 2: Q_{i+1} (Shift Left, for i<3)

    • MUX Input 3: P_i (Parallel data input)

  • All FFs clocked simultaneously.

7.3 Applications

• Serial-to-Parallel Conversion: SIPO register.

• Parallel-to-Serial Conversion: PISO register.

• Data Storage/Transfer: PIPO register.

• Time Delay: SISO register provides fixed clock-cycle delay.

• Sequence Generation: Ring/Johnson counters.

8.0 MEMORY & PROGRAMMABLE LOGIC (High Frequency)

8.1 Read-Only Memory (ROM)

• Internal Organization: Memory Array ( diodes/transistors at intersections) + Address Decoder.

  • Decoder: n-input → $$\displaystyle 2^n $$ word lines (rows).

  • Data Lines (m): One per bit of word. Each word line connects to m bits (columns) via fuse (PROM) or transistor (mask ROM).

• Types:

  • Mask ROM: Programmed during IC fabrication. Permanent, lowest cost for high volume.

  • PROM (Programmable ROM): Fuses blown by user once.

  • EPROM (Erasable PROM): UV light erases entire array. Reprogrammable.

  • EEPROM (Electrically Erasable PROM): Byte-wise erase/write. Slower, more cycles.

• ROM as Combinational Logic Implementer:

  • Truth table stored in ROM. Address = inputs, Data = outputs.

  • Any combinational function can be implemented by storing its truth table.

  • Size: $$\displaystyle 2^n × m $$ ROM for n-input, m-output function.

8.2 Random Access Memory (RAM)

• SRAM (Static RAM):

  • Cell: 6-transistor (6T) latch. Bistable → holds data as long as power on.

  • Read Cycle: Address applied → word line selected → transistors conduct → differential pair senses voltage → amplifier → data out. Non-destructive.

  • Write Cycle: Address applied → word line high → data on bit lines forces latch into new state.

  • Timing: t_{ACC} (address to data valid), t_{RC} (read cycle), t_{WC} (write cycle).

• DRAM (Dynamic RAM):

  • Cell: 1 transistor + 1 capacitor. Charge on capacitor = 1/0. Needs periodic refresh (every few ms) as charge leaks.

  • Advantage: Higher density, lower cost per bit. Disadvantage: Refresh circuitry, slower.

8.3 Memory Organization & Decoding

• Two-Dimensional (2D) Decoding:

  • Problem: Large ROM (e.g., 16K×8) needs 14-to-16384 decoder. Impractical.

  • Solution: Split address into row (R) and column (C).

  • Structure:

    1. Row Decoder: $$\displaystyle n_R $$-input → $$\displaystyle 2^{n_R} $$ row lines.

    2. Column Decoder: $$\displaystyle n_C $$-input → $$\displaystyle 2^{n_C} $$ column lines.

    3. Memory Array: $$\displaystyle 2^{n_R} × 2^{n_C} $$ cells. Each cell selected by unique (row, column) pair.

  • Example: 16K×8 = $$\displaystyle 2^{14}×8 $$. Use 7-bit row address (128 rows) and 7-bit column address (128 columns). Two 7-to-128 decoders.

8.4 Sequential Programmable Devices

• PLA (Sequential): Adds flip-flops on outputs. Feedback from FF outputs to AND array inputs enables state machine implementation.

• PAL (Sequential): Fixed OR array with output logic macrocells (OLMCs). Each OLMC can be configured as combinational output or registered (with FF) output, sometimes with feedback.

9.0 DATA CONVERSION CIRCUITS (Medium Frequency)

9.1 Digital-to-Analog Converter (DAC) - R-2R Ladder

• Circuit: Ladder of resistors R and 2R. Digital inputs control switches to Vref (for 1) or GND (for 0).

• Operation: Each bit position has Thevenin equivalent resistance of 2R looking into its switch. This makes each bit position contribute a current proportional to its weight ($$\displaystyle 2^i $$).

• Output Voltage (for n-bit, Vref = full scale):

$$V_{out} = -\frac{V_{ref}}{2^n} \left( D_{n-1}·2^{n-1} + D_{n-2}·2^{n-2} + ... + D_0·2^0 \right)$$

*   Negative for current-to-voltage op-amp configuration.

*   **Key Advantage:** Only two resistor values (R, 2R). Excellent accuracy, monotonic.

9.2 Analog-to-Digital Converter (ADC) - Successive Approximation

• Block Diagram: Successive Approximation Register (SAR) + DAC + Comparator + Control Logic.

• Operation Cycle (n bits):

  1. Reset: SAR output = 0...0.

  2. For i from MSB (n-1) to LSB (0):

     • Set SAR bit i to 1.

     • DAC converts SAR output to analog $$\displaystyle V_{DAC} $$.

     • Comparator: If $$\displaystyle V_{in} ≥ V_{DAC} $$, keep bit i = 1. Else, clear bit i to 0.

  3. After n cycles, SAR holds digital equivalent of $$\displaystyle V_{in} $$.

• Conversion Time: n clock cycles (fixed, independent of input magnitude).

• Advantages: Fast (moderate speed), good accuracy, no integration (unlike dual-slope).

• Disadvantages: May have missing codes due to DAC non-linearity. Not as accurate as integrating types.

[!TIP] EXAM STRATEGY - UNIT 1

1. Conversions: Always show clear steps. For fractional parts, multiply repeatedly. For non-decimal bases, use binary as intermediate.

2. K-Maps: Draw grid correctly, label variables (AB across, CD down or vice versa). Group largest possible powers of 2. Write minimal SOP/POS.

3. Quine-McCluskey: Show iteration table clearly. Mark combined terms. Draw prime implicant chart. Identify essentials first.

4. Flip-Flops: Memorize characteristic equations and excitation tables. Conversion problems (SR→JK) are very common.

5. Counter Design: Always draw state diagram/table first. For custom sequences, self-loop unused states. Show K-maps for each FF input.

6. PLA/PAL: Be able to draw programming table from a given function. Know the structural difference (AND/OR programmable).

7. Timing Diagrams: For RAM cycles, label t_{ACC}, t_{RC}, t_{WC} clearly. For counters, show all FF waveforms with delays.

8. Short Notes: For topics like "Decoding in Counters", "Priority Encoder", write definition + key circuit/logic + application. 4-mark questions expect 3-4 crisp points.