UNIT 1: DIGITAL SYSTEM DESIGN - EXAM-FOCUSED SHORT NOTES

1. NUMBER SYSTEMS & CONVERSIONS

1.1 Base Representations

• Decimal (Base-10): Digits 0-9. Positional weight = $$\displaystyle 10^i $$.

• Binary (Base-2): Digits 0,1. Positional weight = $$\displaystyle 2^i $$. Fundamental for digital systems.

• Octal (Base-8): Digits 0-7. Positional weight = $$\displaystyle 8^i $$. Shortcut: 3 binary bits = 1 octal digit.

• Hexadecimal (Base-16): Digits 0-9, A(10), B(11), C(12), D(13), E(14), F(15). Positional weight = $$\displaystyle 16^i $$. Shortcut: 4 binary bits = 1 hex digit.

1.2 Conversion Techniques

General Formula for Base-B to Decimal:

$$ (d_n d_{n-1} ... d_0 . d_{-1} ... d_{-m})_B = \sum_{i=0}^{n} d_i \times B^i + \sum_{j=1}^{m} d_{-j} \times B^{-j} $$

Decimal to Other Base (Integer Part): Repeated division by target base, remainders in reverse order. Decimal to Other Base (Fractional Part): Repeated multiplication by target base, integer parts in forward order.

Key Shortcut: Convert via Binary as intermediate base for Octal↔Hex.

• Octal → Hex: Convert each octal digit to 3-bit binary, then regroup into 4-bit hex.

• Hex → Octal: Convert each hex digit to 4-bit binary, then regroup into 3-bit octal.

[!TIP] Exam Alert: Always show steps for fractional conversions. For mixed conversions (e.g., 314.52₈), convert integer and fractional parts separately.

1.3 Special Codes

• Binary Coded Decimal (BCD): Each decimal digit (0-9) represented by 4-bit binary. Invalid codes: 1010-1111.

  • Conversion: Direct digit-to-4-bit mapping (e.g., 9 → 1001).

• Excess-3 Code: BCD + 3 (0011). Self-complementing property (9's complement = 1's complement).

  • Conversion: Decimal → BCD → Add 0011 to each 4-bit group.

• Gray Code: Only 1 bit changes between successive numbers. Weighted, non-positional.

  • Binary → Gray: $$\displaystyle G_i = B_i \oplus B_{i+1} $$ (MSB same, others XOR with next higher bit).

  • Gray → Binary: $$\displaystyle B_n = G_n $$; $$\displaystyle B_{i-1} = B_i \oplus G_{i-1} $$ (MSB down to LSB).

  • Conversion Table: 0000→0000, 0001→0001, 0010→0011, 0011→0010...

• ASCII: 7-bit code for 128 characters (A-Z, a-z, 0-9, symbols). Extended ASCII is 8-bit.

2. BOOLEAN ALGEBRA & LOGIC GATES

2.1 Fundamental Theorems

De Morgan's Theorems:

1. $$\displaystyle \overline{A + B + C + ...} = \overline{A} \cdot \overline{B} \cdot \overline{C} \cdot ... $$

2. $$\displaystyle \overline{A \cdot B \cdot C \cdot ...} = \overline{A} + \overline{B} + \overline{C} + ... $$

Proof (for 2 variables): Use truth tables or Boolean laws. Application: NAND/NOR implementation, simplifying complemented expressions.

2.2 Logic Gates

Gate	Symbol	Truth Table (2-input)	Boolean Expression
AND	DiagramSEARCH: AND gate symbol" alt="AND" />	1 only if A=1 AND B=1	$$\displaystyle Y = A \cdot B $$
OR	DiagramSEARCH: OR gate symbol" alt="OR" />	1 if A=1 OR B=1	$$\displaystyle Y = A + B $$
NOT	DiagramSEARCH: NOT gate symbol" alt="NOT" />	Inverts input	$$\displaystyle Y = \overline{A} $$
NAND	DiagramSEARCH: NAND gate symbol" alt="NAND" />	0 only if A=1 AND B=1	$$\displaystyle Y = \overline{A \cdot B} $$
NOR	DiagramSEARCH: NOR gate symbol" alt="NOR" />	0 if A=1 OR B=1	$$\displaystyle Y = \overline{A + B} $$
XOR	DiagramSEARCH: XOR gate symbol" alt="XOR" />	1 if A ≠ B	$$\displaystyle Y = A \oplus B = A\overline{B} + \overline{A}B $$
XNOR	DiagramSEARCH: XNOR gate symbol" alt="XNOR" />	1 if A = B	$$\displaystyle Y = A \odot B = \overline{A \oplus B} $$

2.3 Universal Gates

• Concept: NAND or NOR alone can implement any Boolean function.

• Implementation using NAND:

  • NOT: $$\displaystyle A' = A \text{ NAND } A $$

  • AND: $$\displaystyle A \cdot B = (A \text{ NAND } B)' = (A \text{ NAND } B) \text{ NAND } (A \text{ NAND } B) $$

  • OR: $$\displaystyle A + B = (A' \cdot B')' = (A \text{ NAND } A) \text{ NAND } (B \text{ NAND } B) $$

• Implementation using NOR:

  • NOT: $$\displaystyle A' = A \text{ NOR } A $$

  • OR: $$\displaystyle A + B = (A \text{ NOR } B)' = (A \text{ NOR } B) \text{ NOR } (A \text{ NOR } B) $$

  • AND: $$\displaystyle A \cdot B = (A' + B')' = (A \text{ NOR } A) \text{ NOR } (B \text{ NOR } B) $$

[!TIP] Common Pitfall: Forgetting double inversion when implementing AND/OR with universal gates. Always remember: NAND/NOR is inverting.

2.4 Logic Families Overview

3. COMBINATIONAL LOGIC DESIGN & MINIMIZATION

3.1 Canonical Forms

• Minterm ($$\displaystyle m_i $$): Product term containing all variables (in true or complemented form). e.g., $ABC'D$. Index = binary value of variables (A=MSB).

• Maxterm ($$\displaystyle M_i $$): Sum term containing all variables. e.g., $A+B+C'+D$. Index = binary value of variables (0 for complemented, 1 for true).

• SOP (Sum of Products): $$\displaystyle F = \sum m(\text{minterms where } F=1) $$. Canonical SOP = sum of all minterms for F=1.

• POS (Product of Sums): $$\displaystyle F = \prod M(\text{maxterms where } F=0) $$. Canonical POS = product of all maxterms for F=0.

• Relationship: $$\displaystyle \sum m(i) = \prod M(\text{all other indices}) $$.

3.2 Karnaugh Map (K-Map) Minimization

Rules for Grouping:

1. Groups must be powers of 2 (1,2,4,8,...).

2. Groups must be rectangular and contiguous (wrap-around allowed).

3. Each 1 must be covered at least once.

4. Use largest possible groups, then fewest number of groups.

5. Don't Cares (X): Can be included to make larger groups but not required.

Key Terms:

• Implicant: Any group of 1s/Xs.

• Prime Implicant (PI): Implicant that cannot be combined with another to eliminate a variable.

• Essential Prime Implicant (EPI): PI that covers a 1 not covered by any other PI.

• Minimal SOP: Sum of all EPIs + minimum PIs to cover remaining 1s.

Minimization Steps:

1. Plot K-map (2,3,4 vars). For 4 vars: AB across top (00,01,11,10), CD down side (Gray code).

2. Group 1s/Xs following rules.

3. Write simplified product term for each group (variable present if same in all cells of group).

4. SOP = OR of all product terms.

POS Minimization: Group 0s (treat Xs as 1s for 0-grouping). Write sum term for each group (variable present if different in all cells). POS = AND of all sum terms.

[!TIP] Exam Tip: For 4-variable K-map, remember the diagonal adjacency (m0 adjacent to m2, m1 adjacent to m3). Always check for wrap-around (leftmost column adjacent to rightmost, top row to bottom).

3.3 Quine-McCluskey (Tabular) Method

Step-by-Step Procedure:

1. List Minterms: Group minterms by number of 1s in binary.

2. Combine Adjacent: Compare groups $i$ and $i+1$. Combine if they differ in exactly 1 bit. Mark combined terms with '-'. Uncombined terms are Prime Implicants.

3. Repeat: Combine new terms (with '-') from previous step. Continue until no more combinations.

4. Prime Implicant Chart: Rows = all PIs. Columns = original minterms. Mark 'X' where PI covers minterm.

5. Select Essential PIs: Column with only one 'X' → that PI is Essential.

6. Cover Remaining Minterms: Use Petrick's Method or trial-and-error to select minimal set of remaining PIs.

With Don't Cares: Include don't cares in initial list but do not include them in the final cover requirement (they can be covered or not).

3.4 Standard Combinational Circuits

Half Adder (HA):

• Inputs: A, B

• Outputs: Sum = $A \oplus B$, Carry = $A \cdot B$

• Logic: XOR for Sum, AND for Carry.

Full Adder (FA):

• Inputs: A, B, $$\displaystyle C_{in} $$

• Outputs: Sum = $$\displaystyle A \oplus B \oplus C_{in} $$, $$\displaystyle C_{out} = AB + BC_{in} + AC_{in} $$

• Design using 2 HAs: $$\displaystyle S = HA_1(A,B) \oplus C_{in} $$; $$\displaystyle C_{out} = C_1 + (S \cdot C_{in}) $$.

• IC 7483: 4-bit full adder chip.

Half Subtractor (HS):

• Inputs: A, B

• Outputs: Diff = $A \oplus B$, Borrow = $\overline{A} \cdot B$

Full Subtractor (FS):

• Inputs: A, B, $$\displaystyle B_{in} $$

• Outputs: Diff = $$\displaystyle A \oplus B \oplus B_{in} $$, $$\displaystyle B_{out} = \overline{A}B + \overline{A}B_{in} + BB_{in} $$

BCD Adder:

• Adds two BCD digits. Output must be ≤ 9.

• Correction Logic: If sum > 9 or $$\displaystyle C_{out}=1 $$, add 6 (0110) to correct.

• Condition: $$\displaystyle C_{out} + S_3 S_2 + S_3 S_1 = 1 $$ → activate correction.

• Circuit: 4-bit FA + correction logic (OR gate feeding second FA's $$\displaystyle C_{in} $$ and adding 6).

Carry Look-Ahead Adder (CLA):

• Principle: Generate carry signals in parallel to reduce delay.

• Equations:

  • $$\displaystyle C_i = G_i + P_i C_{i-1} $$

  • $$\displaystyle G_i = A_i B_i $$ (Generate)

  • $$\displaystyle P_i = A_i \oplus B_i $$ (Propagate)

• Block Diagram:

  DiagramCANVAS: 4-bit CLA block showing Generate/Propagate logic for each bit and final carry equations

• Advantage: Faster than ripple carry for large n.

Binary Multiplier:

• Array Multiplier: Uses AND gates for partial products and adders to sum them. For 4x4: 16 AND gates, 3 rows of FA/HA.

• Partial Products: $$\displaystyle P_i = A_i \cdot B $$ (shifted appropriately).

Magnitude Comparator (2-bit example):

• Inputs: A₁A₀, B₁B₀

• Outputs: A>B, A=B, A<B

• Equations:

  • A>B = $$\displaystyle A_1\overline{B_1} + A_1A_0\overline{B_0} + \overline{A_1}A_0B_1\overline{B_0} $$

  • A=B = $$\displaystyle (A_1 \odot B_1) \cdot (A_0 \odot B_0) $$

  • A<B = $$\displaystyle \overline{A_1}B_1 + \overline{A_1}\overline{A_0}B_0 + A_1\overline{A_0}B_1\overline{B_0} $$

Parity Generator/Checker:

• Even Parity: Output = 1 if even number of 1s in input. XOR of all bits.

• Odd Parity: Output = 1 if odd number of 1s. Invert even parity output.

• Checker: Transmitted data + parity bit → check XOR result (0 for even, 1 for odd).

3.5 MSI Components & Implementation

Multiplexer (MUX): $$\displaystyle 2^n:1 $$ selects one of $$\displaystyle 2^n $$ data inputs using n select lines.

• 2:1 MUX: $$\displaystyle Y = \overline{S}D_0 + S D_1 $$

• Implementing Any Function: Use select lines as variables, data inputs as minterms (0/1/X).

• Designing Larger MUX: e.g., 16:1 from 2:1 → hierarchical: 8 2:1 MUXes → 4 2:1 MUXes → 2 2:1 MUXes → 1 2:1 MUX.

Demultiplexer (DEMUX): $$\displaystyle 1:2^n $$ routes one input to one of $$\displaystyle 2^n $$ outputs based on select lines.

• 1:4 DEMUX: $$\displaystyle Y_i = \overline{S_1}\overline{S_0}D $$ for i=0, etc.

Decoder: $$\displaystyle n:2^n $$ activates exactly one output (low or high) based on n-bit input. Often has enable inputs.

• 2-to-4 Decoder: $$\displaystyle Y_i = \overline{A}B' $$ etc. (for active high).

• Implementing Functions: Use decoder to generate minterms, OR required minterms.

• Minimum Decoder: For function with k minterms, use smallest decoder that covers all minterms (e.g., 2-to-4 for 3 minterms).

Encoder: $$\displaystyle 2^n:n $$ converts $$\displaystyle 2^n $$ inputs to n-bit binary code. Priority Encoder: If multiple inputs=1, highest priority (largest index) is encoded.

• 4-bit Priority Encoder (inputs I₃-I₀, outputs Y₁Y₀, V):

  • $$\displaystyle Y_1 = I_3 + I_2 $$

  • $$\displaystyle Y_0 = I_3 + \overline{I_2}I_1 $$

  • $$\displaystyle V = I_3 + I_2 + I_1 + I_0 $$ (Valid output)

Code Converter (Excess-3 to Gray example):

1. Write truth table (Excess-3 input → Gray output).

2. Simplify each Gray output bit using K-map.

3. Implement with logic gates.

4. SEQUENTIAL LOGIC CIRCUITS: FLIP-FLOPS & REGISTERS

4.1 Latch vs. Flip-Flop

• Latch: Level-triggered. Transparent when clock=1 (or 0). Fast but prone to race.

• Flip-Flop: Edge-triggered (positive/negative). Changes state only at clock edge. Standard for synchronous design.

4.2 Fundamental Flip-Flops

Race-Around Condition in JK FF (Level-triggered): J=K=1, output toggles continuously while clock=1. Eliminated by Master-Slave or edge-triggering.

4.3 Master-Slave Flip-Flop

• Master-Slave JK: Two latches (master + slave) in series, clock inverted to slave.

• Operation: Master follows inputs while clock=1. Slave updates from master when clock→0. Two-level clocking prevents race-around.

• Waveform: Output changes at negative clock edge (if slave negative-edge triggered).

4.4 Flip-Flop Conversions

Procedure:

1. Write excitation table for target FF (required inputs for $$\displaystyle Q_t \rightarrow Q_{t+1} $$).

2. Write state table for desired conversion (present state $Q$, next state $$\displaystyle Q^+ $$).

3. Combine tables → get input equations (J,K for JK; D for D; T for T) in terms of $Q$.

4. Simplify using K-maps → draw logic diagram.

Example: T to JK

• Excitation: T=0 → $$\displaystyle Q^+=Q $$; T=1 → $$\displaystyle Q^+=\overline{Q} $$

• From state table: $$\displaystyle J = T $$, $$\displaystyle K = T $$ → So T-FF is same as JK-FF with J=K=T.

4.5 Shift Registers

• SISO (Serial In Serial Out): 4 D-FFs in chain. Serial input to first FF, output from last.

• SIPO (Serial In Parallel Out): Outputs from all FFs available in parallel.

• PISO (Parallel In Serial Out): Parallel load via multiplexers on D inputs.

• PIPO (Parallel In Parallel Out): Direct parallel load and parallel output.

Universal Shift Register:

• Control Signals: SHIFT (left/right), LOAD (parallel), CLK.

• Design: Each FF input via 4:1 MUX: inputs = parallel data bit, left neighbor, right neighbor, hold (Q).

• Applications: Serial-to-parallel conversion, time delay, ring counter.

4.6 Special Shift Registers

• Ring Counter: n-bit shift register with output of last FF fed to input of first. Sequence: Single '1' circulates. Modulus = n.

  • 4-bit: Initial 1000 → 0100 → 0010 → 0001 → 1000...

• Johnson Counter (Twisted Ring): Complement of last FF output fed to first.

  • 4-bit Sequence: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000... Modulus = 2n.

• PRBS Generator: Shift register with XOR/XNOR feedback taps. Generates pseudo-random sequence. Length = $$\displaystyle 2^n - 1 $$ for n-stage with proper taps (e.g., 4-stage: taps at 4 and 3).

5. SEQUENTIAL LOGIC CIRCUITS: COUNTERS

5.1 Counter Classification

Up/Down Counter: Mode control (M) selects increment/decrement. Synchronous: M affects combinational logic inputs. Asynchronous: M controls direction of clocking (e.g., using AND gates on clock inputs).

MOD-N Counter: Counts from 0 to N-1 then repeats. Requires $$\displaystyle n = \lceil \log_2 N \rceil $$ FFs. Reset logic to force state N → 0.

5.2 Design of Synchronous Counters

General Procedure:

1. State Diagram: Draw sequence of states (0 → 1 → 2...).

2. State Table: Columns: Present State ($$\displaystyle Q_A, Q_B... $$), Next State ($$\displaystyle Q^+ $$).

3. Excitation Table: Add columns for FF inputs (D, J/K, T) using excitation tables.

4. K-Maps: For each FF input variable, plot K-map using present state as variables. Simplify to get input equations.

5. Logic Diagram: Draw FFs with combinational logic from equations.

MOD-6 Counter (0-5) using D FFs:

• States: 000, 001, 010, 011, 100, 101 → 000...

• Unused states (110, 111) → self-correcting design ensures they go to valid state.

• D equations from K-map:

  • $$\displaystyle D_A = Q_A'Q_B'Q_C' + Q_A Q_B' Q_C' $$ (simplify further)

  • $$\displaystyle D_B = Q_A' Q_B' + Q_A' Q_C' + Q_B Q_C' $$

  • $$\displaystyle D_C = Q_A' + Q_B' + Q_C' $$ (or similar)

5.3 Design of Asynchronous Counters

• Use JK FFs with J=K=1 for toggle.

• Clock: FF0 gets external clock. Clock of FF1 = $$\displaystyle \overline{Q_0} $$ (for up counter), FF2 = $$\displaystyle \overline{Q_1} $$, etc.

• 4-bit Up: $$\displaystyle Q_0 $$ toggles every clock; $$\displaystyle Q_1 $$ toggles when $$\displaystyle Q_0=1 $$; $$\displaystyle Q_2 $$ toggles when $$\displaystyle Q_0=Q_1=1 $$; $$\displaystyle Q_3 $$ toggles when $$\displaystyle Q_0=Q_1=Q_2=1 $$.

• 4-bit Up/Down: Use 2:1 MUX on each FF's clock input. Select line M: M=0 → up (use $\overline{Q}$), M=1 → down (use Q).

5.4 Applications

• Frequency Division: Asynchronous counter divides by $$\displaystyle 2^n $$ (each FF is ÷2).

• Pulse Train Generator: Design counter that decodes a specific state to generate output pulse of desired frequency/duty cycle.

  • Example: 120 Hz → 20 Hz. Need divide by 6. Use MOD-6 counter, decode state 5 (101) to generate pulse.

• Decoding (One-Hot): AND gate with active-low outputs for each state (e.g., $$\displaystyle Y_0 = \overline{Q_2} \overline{Q_1} \overline{Q_0} $$ for state 0).

6. FINITE STATE MACHINES (FSM) & SYNTHESIS

6.1 Moore vs. Mealy Machine

6.2 FSM Design Procedure

1. From Specification to State Diagram: Define states, inputs, outputs, transitions.

2. State Assignment: Assign binary codes to states.

   • Binary: 00,01,10,11...

   • Gray: Adjacent states differ by 1 bit (reduces glitches).

   • One-Hot: Only one FF=1 per state (simple, uses more FFs).

3. State Reduction (if needed):

   • Implication Table: Pair states with identical output behavior. Check if they can be merged.

   • Partition Method: Group states with same output. Refine partitions until stable.

4. State Table: Columns: Present State, Inputs, Next State, Outputs.

6.3 FSM Implementation

1. Next-State Equations: From state table, treat next state bits as output functions of present state & inputs. Use K-maps.

2. Output Equations: Similarly, treat outputs as functions.

3. Choose FF Type: D FFs simplest ($$\displaystyle D = Q^+ $$). JK FFs require excitation table mapping to J,K.

4. Draw Circuit: FFs + combinational logic for D/JK inputs and outputs.

ASM (Algorithmic State Machine) Chart:

• State Box: Represents a state (outputs inside/outside).

• Decision Box: Tests input condition (diamond). Paths based on 1/0.

• Conditional Output Box: Outputs that depend on both state and path taken.

• Conversion to State Table: Each path through decision boxes becomes a row in state table.

6.4 Sequence Detector Design (Example: "0011" Overlapping, Mealy)

1. States: S0 (no match), S1 (got '0'), S2 (got '00'), S3 (got '001').

2. Transitions:

   • S0 --0→ S1, --1→ S0

   • S1 --0→ S2, --1→ S0

   • S2 --0→ S2, --1→ S3

   • S3 --0→ S1 (overlap: last '0' of "0011" is first '0' of new sequence), --1→ S0 (output=1 on this transition)

3. State Assignment: S0=00, S1=01, S2=10, S3=11.

4. State Table & K-maps → D flip-flop equations:

   • $$\displaystyle D_A = \overline{A}B\overline{X} + A\overline{B}\overline{X} $$ (example)

   • $$\displaystyle D_B = \overline{A}\overline{B}X + \overline{A}B X $$

   • $$\displaystyle Z = A B X $$ (output depends on present state A,B and input X)

5. Circuit: 2 D FFs + combinational logic for D inputs and Z.

[!TIP] Overlapping vs Non-overlapping: Overlapping allows suffix of detected sequence to be prefix of next (e.g., "0011" → last "11" can start new? No, but last '0' can). Non-overlapping resets to initial state after detection.

7. LOGIC FAMILIES & PROGRAMMABLE LOGIC

7.1 TTL Logic Family

Basic TTL NAND Gate Circuit:

• Multi-emitter input transistor: Acts like AND gate (all inputs high → base current flows).

• Phase splitter: Single transistor gives inverted/non-inverted signals.

• Totem-pole output: Active pull-up (transistor) + active pull-down (transistor). Reduces power, speeds up falling edge.

• Operation: Inputs high → current flows through multi-emitter → phase splitter turns on pull-down → output low. Any input low → no current → pull-up on → output high.

Tri-State TTL Gate:

• Concept: Output can be High, Low, or High-Impedance (Z).

• Enable Control: Active-low or active-high enable pin. When disabled, both output transistors off → high-Z.

• Application: Bus systems. Multiple devices share a common wire; only one enabled at a time.

• Circuit: Adds enable transistor(s) to totem-pole output.

7.2 ECL (Emitter-Coupled Logic)

Basic ECL Inverter:

• Differential amplifier with constant current source.

• Reference voltage (Vref) set by voltage divider.

• Operation: Input > Vref → transistor Q1 on → output at collector of Q2 (high). Input < Vref → Q2 on → output low.

• Advantages: Very high speed (no saturation, small voltage swings ~0.8V).

• Disadvantages: High power consumption (constant current), poor noise margin.

7.3 CMOS Logic Family

Basic CMOS Inverter:

• Complementary pair: PMOS (pull-up) and NMOS (pull-down).

• Operation: Input high → NMOS on, PMOS off → output low (to ground). Input low → PMOS on, NMOS off → output high (to VDD).

• Static Power: Near zero (only leakage, no direct path VDD-GND in steady state).

• Advantages: Extremely low power, high noise margin, high input impedance.

• Disadvantages: Slow speed (high input capacitance, resistive loads). Static sensitive.

7.4 Programmable Logic Devices

FPGA (Field-Programmable Gate Array):

• Basic Architecture:

  • CLB (Configurable Logic Block): Contains LUTs (Look-Up Tables, small RAMs that implement any logic function), flip-flops, multiplexers.

  • IOB (Input/Output Block): Handles pin interfacing, often with tri-state buffers.

  • Interconnect Matrix: Programmable routing switches (SRAM-based) connecting CLBs and IOBs.

• Configuration Memory: SRAM-based (volatile, reprogrammable). Loaded at power-up from external memory.

• Advantages over CPLD/PLA: Very high capacity (thousands to millions of gates), in-system reprogrammable, suitable for large, complex designs.

• CPLD: Smaller, non-volatile (EEPROM/Flash), faster pin-to-pin delay.

[!TIP] Exam Focus: Be able to contrast TTL/ECL/CMOS in a table. For PLD, know FPGA architecture blocks (CLB, IOB, interconnect) and SRAM configuration.