EC-303 Digital System Design - Nov 2022 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 8 Marks
   aConvert the following binary numbers into decimal, octal and hexadecimal.

   1. i)111100001101
   2. ii)111.0111
   How to answer

   • Convert binary to decimal by positional weights
   • Convert to octal by 3-bit grouping
   • Convert to hexadecimal by 4-bit grouping
   • Handle fractional part 111.0111 by negative powers of 2
2. 6 Marks
   bState and prove De-Morgan's theorem.
   How to answer

   • State De-Morgan's two theorems with Boolean expressions
   • Prove using truth table for 2 variables
   • Prove algebraically using Boolean axioms
   • Show application to NAND/NOR logic
3. 7 Marks
   aSimplify the following using Quine-McCluskey method? $f(w,x,y,z) = \sum m(0,1,3,9,10,12,13,14) + \sum d(2,5,6,11)$
   How to answer

   • List minterms and don't cares in binary and group by number of 1s
   • Perform Quine-McCluskey tabular combination to get prime implicants
   • Construct prime implicant chart and select essential prime implicants
   • Write minimized SOP expression
4. 7 Marks
   bDesign one full adder using two half adders?
   How to answer

   • Define half adder and full adder truth tables
   • Show sum using two XOR stages and carry using OR of half-adders carries
   • Draw block diagram / logic diagram using two half adders plus OR gate
5. 6 Marks
   aDesign and explain a 4-bit priority encoder.
   How to answer

   • Define priority encoder and priority concept
   • Give truth table for 4-bit priority encoder with valid output
   • Derive Boolean expressions and logic implementation
6. 8 Marks
   bDesign and explain a 16:1 mux using 2:1 mux.
   How to answer

   • Explain 2:1 mux as building block and selection logic
   • Show tree structure: 8 + 4 + 2 + 1 = 15 nos. 2:1 mux for 16:1
   • Explain select lines S3-S0 routing across stages
7. 6 Marks
   aWrite a short notes on JK flip-flop.
   How to answer

   • Give symbol, truth table / characteristic table and excitation
   • Explain J-K operation: hold, set, reset, toggle
   • Mention race-around and master-slave / edge-triggered solution
8. 8 Marks
   bWhat are the basic elements used in ASM chart explain in detail?
   How to answer

   • Define ASM chart purpose for FSM design
   • Explain state box, decision box, conditional output box with symbols
   • Explain ASM block, linking and timing
9. 9 Marks
   aDesign a modulo-6 counter which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1... The counter counts the clock pulses if it's enable input is equal to 1, using D flip-flop?
   How to answer

   • Determine 3 D flip-flops needed for 6 states and state diagram
   • Draw excitation / transition table and derive D inputs with K-maps
   • Draw logic circuit with enable control and explain counting sequence
10. 5 Marks
    bExplain difference between the synchronous and asynchronous counters.
    How to answer

    • Define synchronous vs asynchronous clocking
    • Compare on clock connection, speed, propagation delay, complexity
    • Give examples and applications
11. 6 Marks
    aDesign and explain the working of 4-bit ring counter.
    How to answer

    • Explain ring counter principle with circulating single 1
    • Show 4 D flip-flops in shift register with feedback
    • Give timing / state sequence and applications
12. 8 Marks
    bDesign asynchronous 4-bit up/down counter using JK flip-flop.
    How to answer

    • Explain up/down control logic for JK toggle mode
    • Show cascading with clock from Q/Qbar and UP/DOWN control
    • Draw 4-bit asynchronous up/down counter circuit
13. 7 Marks
    aDraw and explain Tri-state TTL NAND gate.
    How to answer

    • Give TTL NAND tri-state circuit with enable/control transistor
    • Explain high, low and high-impedance states operation
    • Draw circuit diagram and truth table
14. 7 Marks
    bExplain in detail FPGA with suitable block diagram.
    How to answer

    • Define FPGA and its architecture: CLB, interconnect, IOB
    • Draw suitable block diagram of FPGA
    • Mention programming technology and applications
15. 14 Marks
    Write short notes on following any two questions.

    1. i)Implement all logic gates with universal gates.
    2. ii)Design two bit magnitude comparator.
    3. iii)Finite state machine capabilities and limitations.
    4. iv)State diagram and state stable, state reduction.
    How to answer

    • For chosen two topics give definition, diagram/truth table and working
    • Explain design steps / expressions
    • Mention applications and limitations