EC-303 Digital System Design - Dec 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aFor the following Boolean function, list all prime implicants, essential prime implicants and POS form using K-map. $F(A, B, C, D) = \pi M (0, 1, 3, 4, 7, 9, 11, 14, 15)$
   How to answer

   • Draw 4-variable K-map for maxterms $\pi M(0,1,3,4,7,9,11,14,15)$
   • Identify all prime implicants by grouping 0s
   • Identify essential prime implicants covering minterms uniquely
   • Write minimal POS expression
2. 7 Marks
   bDesign a full adder using only required number of half adders.
   How to answer

   • State truth table of full adder: Sum = A xor B xor Cin
   • Show two half-adders for partial sums
   • Use OR gate for final carry: Cout = carry1 + carry2
   • Draw block diagram with 2 half adders + OR gate
3. 7 Marks
   aDesign an Excess-3 to GRAY code convertor and obtain a minimum SOP form. Realise the function using 2-level gate implementation.
   How to answer

   • Write truth table Excess-3 input vs GRAY output
   • Plot K-maps for each GRAY output bit
   • Obtain minimum SOP expressions
   • Realise with 2-level AND-OR gate implementation
4. 7 Marks
   bDesign the logic circuit diagram of a 2-bit binary multiplier and represent the output in POS form.
   How to answer

   • Write truth table for 2-bit x 2-bit multiplication
   • Derive expressions for 4 output bits
   • Express outputs in POS form
   • Draw logic circuit diagram using gates
5. 7 Marks
   aRealize $(A+A'B)$ using only minimum number of 2-to-4 line decoder to generate the function at a particular output pin of decoder.
   How to answer

   • Simplify $(A+A'B) = A+B$
   • Show decoder outputs generate minterms
   • Use minimum number of 2-to-4 decoders with enable
   • Show required output pin connection
6. 7 Marks
   bImplement the following Boolean functions using $8 \times 1$ multiplexer (MUX) and external logic gates. Connect inputs 'B' and 'D' to select lines ($S_1$ and $S_0$) of MUX. $F(A, B, C, D) = \Sigma m (0, 3, 5, 7, 9, 10, 12, 14)$
   How to answer

   • Use B and D as select lines $S_1, S_0$ of $8\times1$ MUX
   • Create implementation table for $F(A,B,C,D)=\Sigma m(0,3,5,7,9,10,12,14)$
   • Derive MUX data inputs in terms of A, C
   • Draw MUX with external gates
7. 7 Marks
   aDesign a 3 bit UP/DOWN synchronous counter with mode bit M, such that when, M = 0, then counter counts in DOWN direction and when M = 1, then counter counts in UP direction. Use D flip flop for design of the counter.
   How to answer

   • Write state table for 3-bit UP (M=1) / DOWN (M=0) counting
   • Derive D flip-flop excitation: D = next state
   • Minimize D inputs with K-maps in terms of present state and M
   • Draw counter circuit with 3 D flip-flops
8. 7 Marks
   bA square waveform of 120 Hz is to be used to generate a square waveform of frequency 20 Hz using a counter. Design a logic circuit for the same using D flip-flops and other necessary logic gates. Show all the necessary steps for achieving the goal.
   How to answer

   • Required division ratio = 120 Hz / 20 Hz = 6
   • Design mod-6 counter using D flip-flops
   • Use counter output as divided square wave
   • Show state diagram, excitation and logic diagram steps
9. 7 Marks
   aConvert a T flip-flop into J-K flip-flop. Show all the necessary calculations with final logic diagram.
   How to answer

   • Write excitation tables of T and J-K flip-flops
   • Derive T = JQ' + KQ or equivalent via K-map
   • Show combinational logic for T input
   • Draw final conversion logic diagram
10. 7 Marks
    bThe state diagram of a control unit is shown in Fig. 1. It has four states and two inputs, 'x' and 'y'. Draw the equivalent ASM chart and design the controller using D flip flops.

    How to answer

    • Interpret state diagram Fig. 1 with states 00,01,11,10 and inputs x,y
    • Construct equivalent ASM chart with state and conditional boxes
    • Derive D flip-flop next-state equations
    • Draw controller circuit using D flip-flops
11. 14 Marks
    Design a sequence detector to detect the sequence 0011 using Mealy machine. Use D flip-flops only along with other logic gates.
    How to answer

    • Draw Mealy state diagram for sequence 0011 with overlapping
    • Assign states and derive state table
    • Obtain D flip-flop excitation and output equations
    • Draw circuit with D flip-flops and gates
12. 7 Marks
    aExplain the following:

    1. i)Three state TTL gate
    2. ii)Fan-in and Fan-out
    3. iii)Nose margin
    How to answer

    • Define three-state TTL operation and high-impedance state
    • Define fan-in/fan-out with loading limits
    • Define noise margin with VOH, VOL, VIH, VIL levels
    • Give examples/diagrams for each
13. 7 Marks
    bDesign a synchronous counter to generate the following sequence (as shown in Fig. 2) using T flip flop. $0-2-7-3-4-5$ cyclic

    How to answer

    • Write transition table for sequence 0-2-7-3-4-5
    • Derive T flip-flop excitation from present to next state
    • Minimize T inputs using K-maps
    • Draw synchronous counter circuit
14. 14 Marks
    Assuming that the initial state of the shift register shown in Fig. 3 is 100 (i.e., $Q_0 = 1, Q_1 = 0$ and $Q_2 = 0$), find the next six successive states. Also find, after how many shifts does the register return to the starting state?

    How to answer

    • Identify shift register wiring: D0 = Q0 XOR Q1, D1 = Q0, D2 = Q1 with clock
    • Iterate from initial $Q_0=1, Q_1=0, Q_2=0$ for six clocks
    • Tabulate successive states Q0 Q1 Q2
    • Determine period when state 100 repeats