EC-303 Digital System Design/Digital Electronics - Dec 2025 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aConvert the followings:

   1. i)$(753.4)_{8}$ to decimal
   2. ii)$(101101.101)_{2}$ to hexadecimal
   3. iii)$(9A.6)_{16}$ to binary
   4. iv)$(245)_{10}$ to hexadecimal
   5. v)$(1101101)_{2}$ to octal
   6. vi)$(59)_{10}$ to Excess-3
   7. vii)$(101011)_{2}$ to Gray code
   How to answer

   • Recall base conversion methods for integer and fractional parts
   • Apply octal/binary/hex/decimal interconversion for (i)-(v)
   • Apply BCD Excess-3 addition of 3 for (vi) and binary to Gray XOR rule for (vii)
   • Show steps and final converted values
2. 7 Marks
   bMinimize the function using K-map with don't care conditions: $F=\sum m(1, 3, 7, 11, 15)+d(0, 2, 5)$
   How to answer

   • Plot 4-variable K-map with minterms 1,3,7,11,15 and don't cares 0,2,5
   • Form largest power-of-2 groups using don't cares
   • Write prime implicants and minimized SOP expression
   • Optionally show logic diagram
3. 7 Marks
   aImplement the following function using only NOR gates: $$F=(A+B)(C+D)$$
   How to answer

   • Express $F=(A+B)(C+D)$ in NOR-only form using De-Morgan
   • Show double inversion / bubble manipulation steps
   • Draw logic diagram using only NOR gates
   • Verify equivalence with truth table
4. 7 Marks
   bExplain the Full Subtractor circuit and derive expressions for Difference and Borrow.
   How to answer

   • Define full subtractor inputs A,B,Bin and outputs Difference, Borrow
   • Give truth table for 8 combinations
   • Derive Difference = A xor B xor Bin and Borrow expressions via K-map
   • Show logic circuit using XOR, AND, OR/NOT
5. 7 Marks
   aExplain the working of Carry Look Ahead Adder with logic equations.
   How to answer

   • Define generate Gi and propagate Pi signals
   • Derive carry equations C1, C2, C3, C4 independent of ripple
   • Explain parallel carry generation for speed improvement
   • Show block/logic diagram of 4-bit CLA adder
6. 7 Marks
   bDesign a 3-to-8 line decoder and explain its operation.
   How to answer

   • Give truth table for 3 inputs to 8 active outputs
   • Implement using 3 NOT gates and 8 3-input AND gates
   • Explain enable and one-hot output operation
   • Show logic diagram
7. 7 Marks
   aExplain Master-Slave JK flip-flop with neat timing diagram. How does it eliminate the race-around condition?
   How to answer

   • Describe master and slave SR/JK latches with inverted clocks
   • Show timing diagram for J=K=1 toggling and other modes
   • Explain race-around condition in level-triggered JK
   • Show how master-slave operation on opposite clock phases eliminates race
8. 7 Marks
   bDesign a synchronous FSM using JK flip-flops for a mod-4 up counter. Draw state diagram and excitation table.
   How to answer

   • Draw 4-state diagram 00->01->10->11->00 for mod-4 up counter
   • Make present-next state table and JK excitation table
   • Derive J,K equations for two flip-flops
   • Show logic diagram
9. 7 Marks
   aDesign a Pseudo Random Binary Sequence (PRBS) generator and explain its working.
   How to answer

   • Explain LFSR principle with shift register and XOR feedback
   • Select polynomial taps for maximal length sequence
   • Show block diagram of PRBS generator
   • Explain pseudo-random sequence generation working
10. 7 Marks
    bExplain asynchronous (ripple) counters with neat block diagram and timing waveforms. Discuss their advantages and limitations.
    How to answer

    • Show cascaded T/JK flip-flops with clock rippling block diagram
    • Draw timing waveforms showing successive division by 2
    • List advantages: simplicity, low hardware
    • Discuss limitations: propagation delay, speed, glitches
11. 7 Marks
    aExplain the working of a universal shift register with neat diagram.
    How to answer

    • Describe 4-bit register with 4x1 MUX per stage for mode select
    • Explain S1S0 modes: hold, shift right, shift left, parallel load
    • Show neat diagram with flip-flops and multiplexers
    • Explain synchronous operation
12. 7 Marks
    bDesign a mod-6 synchronous counter using JK flip-flops by following these steps (i) State diagram (ii) State table (iii) Excitation table (iv) Logic diagram
    How to answer

    • Draw 6-state diagram 000 to 101 with return to 000
    • Form state table and JK excitation table
    • Minimize J,K equations using K-map
    • Draw final logic diagram
13. 7 Marks
    aExplain Tri-state TTL logic with truth table and timing diagram. Why is tri-state logic required?
    How to answer

    • Describe tri-state outputs: logic 0, logic 1, high-impedance
    • Give truth table with enable and timing/enable operation
    • Explain bus sharing and need for tri-state
    • Show TTL tri-state circuit
14. 7 Marks
    bImplement the Boolean function $F(A,B,C,D)=\sum m(0,2,5,7,8,10,13,15)$ using a programmable logic device.
    How to answer

    • Express $F(A,B,C,D)=\sum m(0,2,5,7,8,10,13,15)$ in SOP form
    • Explain PLA/PAL structure with AND-OR planes
    • Show fuse/programming map for given minterms
    • Draw implementation diagram
15. 14 Marks
    Write a short note on any two :

    1. a)De-Morgan's Theorem
    2. b)Magnitude Comparator
    3. c)Ring Counter
    4. d)Emitter Coupled Logic (ECL)
    How to answer

    • Select any two topics from four options
    • Give definition/principle with relevant equations/diagram
    • Explain working with example or truth table
    • Mention applications/advantages