DIGITAL SYSTEM DESIGN (EC-303) - Important Questions
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Unit 17 Marks High Priority
Convert numbers (including fractional parts) between decimal, binary, octal and hexadecimal systems, and convert the given binary number to Gray code and Excess-3 code.
Predicted for DEC-2026
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Unit 17 Marks High Priority
Minimize the Boolean function using K-map with don't care conditions: Y = Sum m(0,1,6,7) + Sum d(8,9,10,11,12) and obtain minimal SOP expression.
Predicted for DEC-2026
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Unit 17 Marks High Priority
State and prove De-Morgan's theorem with truth table and logic gate representation.
Predicted for DEC-2026
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Unit 27 Marks High Priority
Design a full adder using two half adders. Derive truth table, expressions for Sum and Carry and draw logic diagram.
Predicted for DEC-2026
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Unit 27 Marks High Priority
Explain the working and design of BCD adder with neat diagram and correction logic.
Predicted for DEC-2026
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Unit 27 Marks High Priority
Design and explain a 4-bit priority encoder with truth table and logic circuit.
Predicted for DEC-2026
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Unit 27 Marks High Priority
Explain an 8:1 multiplexer in detail with block diagram, truth table and logic circuit.
Predicted for DEC-2026
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Unit 37 Marks High Priority
Explain the working of master-slave JK flip-flop with circuit diagram and timing diagram and explain how it eliminates race-around condition.
Predicted for DEC-2026
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Unit 37 Marks High Priority
Design a Pseudo Random Binary Sequence (PRBS) generator and explain its working with state diagram.
Predicted for DEC-2026
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Unit 37 Marks High Priority
Explain the design procedure for a synchronous finite state machine with suitable example.
Predicted for DEC-2026
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Unit 47 Marks High Priority
Explain the working of a universal shift register with neat diagram and example of modes of operation.
Predicted for DEC-2026
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Unit 47 Marks High Priority
Design a MOD-6 synchronous counter using J-K flip-flops with state diagram, state table, excitation table and logic diagram.
Predicted for DEC-2026
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Unit 47 Marks High Priority
Explain the differences between synchronous and asynchronous counters with respect to operation, speed, design and applications.
Predicted for DEC-2026
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Unit 57 Marks High Priority
Draw the circuit diagram of Tri-state TTL NAND gate and explain its working, including truth table and need for tri-state logic.
Predicted for DEC-2026
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Unit 514 Marks High Priority
Write short notes on any two of the following: (i) FPGA architecture with suitable block diagram (ii) CMOS family and its interfacing with TTL (iii) Programmable logic devices - PAL and PLA.
Predicted for DEC-2026
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