DIGITAL SYSTEM DESIGN (EC-303) - Important Questions

Convert numbers (including fractional parts) between decimal, binary, octal and hexadecimal systems, and convert to/from Gray code and Excess-3 code.

Minimize / simplify the Boolean function using K-map with don't care conditions

Simplify $f(w,x,y,z)=\Sigma m(0,1,3,9,10,12,13,14)+\Sigma d(2,5,6,11)$ using the Quine-McCluskey method.

Simplify the given Boolean function using Boolean algebra.

Minimize / simplify the Boolean function using K-map to obtain minimal SOP expression (no don't cares)

Write short notes on De-Morgan's theorem (among given topics).

What is a universal gate? Implement NOR gate using NAND gate.

Implement $F=(A+B)(C+D)$ using only NOR gates.

State and prove De-Morgan's theorem.

Minimize $f=\Sigma(1,2,3,7,8,9,10,11,14,15)$ using the Quine-McCluskey method.

Minimize $f=\Sigma(1,2,3,5,6,9,10,13,15)$ using the Quine-McCluskey method.

Convert decimal number $(572)_{10}$ to Gray code.

Explain the working and design of BCD adder with diagram.

Design a full adder using two half adders.

Explain the full subtractor in detail with truth table, expressions for Difference and Borrow, and logic circuit design.

Design and explain a 4-bit priority encoder.

Explain the working and design of 4-bit Carry Look Ahead Adder with logic equations.

Design a 3-to-8 line decoder and explain its operation.

Explain an 8:1 multiplexer in detail.

Design and explain a 16:1 multiplexer using 2:1 multiplexers.

Write short notes on Binary Multiplier and Binary Divider (as part of choice among Parity checker, FPGA).

Write short notes on any two: Carry look ahead adder, Shift register, Pseudo Random Binary Sequence generator.

Design a full subtractor circuit.

Design an Excess-3 to GRAY code convertor and obtain a minimum SOP form. Realise the function using 2-level gate implementation.

Explain the working of master-slave (JK) flip-flop and how it eliminates race-around condition

Design a Pseudo Random Binary Sequence (PRBS) generator and explain its working.

Define and explain the working of JK flip-flop with diagram, truth table, and race-around condition

Explain the design procedure for a synchronous finite state machine.

Design a synchronous FSM mod-4 up counter using JK flip-flops, including state diagram and excitation table.

Write short notes on any two: implementation of logic gates with universal gates, design of two-bit magnitude comparator, FSM capabilities and limitations, state diagram, state stability and state reduction.

Explain in detail the basic elements used in an ASM chart.

Design a pulse train generator.

Design a Mealy sequence detector for sequence 0011 using D flip-flops and logic gates.

Convert a T flip-flop into J-K flip-flop with calculations and logic diagram

Draw the equivalent ASM chart from a given control unit state diagram and design the controller using D flip-flops.

Explain the working of a universal shift register with neat diagram and example.

Design a MOD-6 synchronous counter using J-K flip-flops

Explain the differences between synchronous and asynchronous counters

Design a MOD-6 / divide-by-6 counter counting 0,1,2,3,4,5 using D flip-flops

Explain asynchronous (ripple) counters with block diagram and timing waveforms, including advantages and limitations.

Design asynchronous 4-bit up/down counter using JK flip-flop.

Design and explain the working of a 4-bit ring counter.

Design a MOD-7 counter using JK flip-flop

Given initial state 100, determine the next six successive states of the shift register and number of shifts to return to starting state.

Design a 3-bit UP/DOWN synchronous counter with mode control using D flip-flops.

Design a synchronous counter for the sequence $0-2-7-3-4-5$ cyclic using T flip-flop

Explain the difference between synchronous and asynchronous counters.

Draw the circuit diagram of Tri-state TTL (NAND) gate and explain its working, including truth table and need for tri-state logic

Explain ECL logic family / draw circuit of basic ECL inverter and explain its operation

Draw the circuit diagram of TTL NAND gate and explain its working

Implement the Boolean function $F(A,B,C,D)=\sum m(0,2,5,7,8,10,13,15)$ using a programmable logic device.

Explain in detail FPGA with suitable block diagram.

Explain Tri-state TTL and CMOS logic families

Explain TTL logic family

Explain three-state TTL gate, fan-in and fan-out, and noise margin

Write a short note on any two :