UNIT 3: VLSI Design - Comprehensive Study Notes

IC Fabrication and Manufacturing Process

1. Wafer Preparation

• Silicon Wafer: Starting material, single-crystal, <100> orientation.

• Steps:

  1. Czochralski (CZ) growth: Molten silicon doped with impurity (p-type: Boron; n-type: Phosphorus/Arsenic). Crystal pulled and rotated.

  2. Slicing & Lapping: Ingot sliced into wafers (~725µm thick), surfaces ground flat.

  3. Polishing: Chemical-Mechanical Polishing (CMP) for mirror finish.

  4. Cleaning: RCA clean (SC1: NH₄OH/H₂O₂/H₂O; SC2: HCl/H₂O₂/H₂O) to remove organics, metals, particles.

• Cleanliness & Process Control:

  • Class 1-10 Cleanroom: Air filtered, personnel in bunny suits.

  • Particle control: Critical dimension (CD) ~0.1µm; particle >1/3 CD causes defect.

  • Process control: In-situ monitoring (ellipsometry for oxide thickness), statistical process control (SPC).

2. Photolithography

• Purpose: Transfer circuit pattern from mask to wafer.

• Steps:

  1. Photoresist coating: Spin coat (positive/negative resist).

  2. Soft bake: Evaporate solvent.

  3. Exposure: UV light through mask (align to previous layers).

  4. Development: Dissolve exposed (positive) or unexposed (negative) resist.

  5. Hard bake: Harden resist, improve adhesion.

• Importance: Defines minimum feature size; resolution limit: $$\displaystyle R = k_1 \cdot \frac{\lambda}{NA} $$ (Rayleigh criterion).

3. Oxidation

• Thermal growth of SiO₂ in wet (H₂O) or dry (O₂) ambient.

• Deal-Grove model:

  • Linear-parabolic growth: $$\displaystyle x^2 + A x = B(t + \tau) $$

  • Where $x$ = oxide thickness, $A$ = linear rate constant, $B$ = parabolic rate constant.

• Uses: Gate oxide (thin, high-quality), field oxide (thick, isolation), sacrificial layer.

4. Doping & Ion Implantation

• Diffusion: High-temp drive-in of dopant from deposited source (e.g., POCl₃ for n⁺). Gaussian profile.

• Ion Implantation: Accelerated ions (dose, energy) → precise, low-temp. Requires annealing to repair damage.

• Activation: Annealing (RTA) to place dopants on lattice sites.

5. Metallization & Interconnects

• Deposition: Sputtering (Al, Cu), CVD (W, TiN).

• Patterning: Litho + etch (reactive ion etch, RIE).

• Interconnects in CMOS:

  • Local: Poly-Si, metal1.

  • Intermediate: Metal2, metal3.

  • Global: Thick metal, power rails.

  • Challenges: RC delay, electromigration, crosstalk. Use low-k dielectrics, Cu (dual-damascene).

6. CMOS Process Flows

• n-well CMOS (for p-substrate):

  1. p-substrate start.

  2. n-well implant (mask, drive-in).

  3. Field oxide (LOCOS) growth.

  4. Gate oxide growth.

  5. Poly deposition, doping, patterning.

  6. Source/Drain implants (n⁺ for NMOS, p⁺ for PMOS in n-well).

  7. Annealing.

  8. Interlayer dielectric (ILD) deposition, contact etch.

  9. Metallization, passivation.

• Twin-tub CMOS:

  1. p⁺ buried layer (n-tub) and n⁺ buried layer (p-tub) implants.

  2. Epitaxial growth (lightly doped p- or n-).

  3. n-tub and p-tub implants (separate masks).

  4. Continue as n-well process.

  • Advantages: Better latch-up immunity, symmetric characteristics, lower substrate resistance.

  • Disadvantages: More masks, higher cost, complex epitaxy.

7. Technology Comparison

• NMOS vs CMOS area: CMOS ~2× NMOS due to separate n/p regions.

• Effects: CMOS → low static power, high noise margin; Bipolar → high speed, high gain; Hybrid → BiCMOS for analog/RF.

Device Models and Characteristics

A. MOSFET Models

1. DC Model (Long-Channel)

• Triode (Linear) ($$\displaystyle V_{DS} < V_{GS} - V_{th} $$):

$$I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2} \right] (1 + \lambda V_{DS})$$

• Saturation ($$\displaystyle V_{DS} \geq V_{GS} - V_{th} $$):

$$I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})^2 (1 + \lambda V_{DS})$$

• Subthreshold ($$\displaystyle V_{GS} < V_{th} $$):

$$I_D \approx I_{D0} e^{\frac{V_{GS} - V_{th}}{n V_T}} (1 - e^{-\frac{V_{DS}}{V_T}})$$

where $$\displaystyle n = 1 + \frac{C_{dep}}{C_{ox}} $$, $$\displaystyle V_T = kT/q $$.

2. Body Effect

• Threshold voltage shift due to source-bulk bias:

$$V_{th} = V_{th0} + \gamma \left( \sqrt{|\phi_F + V_{SB}|} - \sqrt{|\phi_F|} \right)$$

where $$\displaystyle \gamma = \frac{\sqrt{2q \epsilon_{si} N_{sub}}}{C_{ox}} $$, $$\displaystyle \phi_F = \frac{kT}{q} \ln \frac{N_{sub}}{n_i} $$.

3. Short-Channel Effects

• DIBL (Drain-Induced Barrier Lowering): $$\displaystyle V_{th} $$ decreases with $$\displaystyle V_{DS} $$.

• Velocity Saturation: $$\displaystyle v_{sat} $$ limits $$\displaystyle I_D $$; $$\displaystyle I_D \propto (V_{GS} - V_{th}) $$ not squared.

• Channel Length Modulation (CLM): $\lambda$ increases as $L$ ↓.

• Applications: High-speed logic, RF. Limitations: Increased leakage, reduced $$\displaystyle V_{th} $$ control.

4. MOSFET SPICE Models

• Level 1 (Large Signal): Square-law, no short-channel effects.

• Level 2: Adds mobility degradation, CLM, substrate bias, DIBL.

• Small-Signal Model (High-frequency):

  • Parameters: $$\displaystyle g_m = \frac{\partial I_D}{\partial V_{GS}} $$, $$\displaystyle g_{ds} = \frac{\partial I_D}{\partial V_{DS}} $$, $$\displaystyle C_{gs}, C_{gd}, C_{gb} $$.

  • Cutoff frequency: $$\displaystyle f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})} $$.

5. Noise Modeling

• Thermal (channel) noise: $$\displaystyle i_d^2 = 4kT \gamma g_m $$ ($$\displaystyle \gamma = 2/3 $$ long-channel).

• Flicker (1/f) noise: $$\displaystyle i_d^2 = \frac{K}{C_{ox} W L f} g_m^2 $$.

• SPICE: .NOISE analysis; NFL (flicker noise coefficient).

B. BJT Models

1. Ebers-Moll Model

• Emitter current: $$\displaystyle I_E = I_{ES} \left( e^{\frac{V_{BE}}{V_T}} - 1 \right) - \alpha_R I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right) $$

• Collector current: $$\displaystyle I_C = \alpha_F I_{ES} \left( e^{\frac{V_{BE}}{V_T}} - 1 \right) - I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right) $$

• $$\displaystyle \alpha_F, \alpha_R $$: Forward/reverse transport factors; $$\displaystyle I_{ES}, I_{CS} $$: Saturation currents.

2. Temperature Dependence

• $$\displaystyle I_{ES} \propto T^3 e^{-E_g/(kT)} $$ → doubles per ~10°C.

• $$\displaystyle V_{BE} $$ decreases ~2mV/°C.

• Mitigation: Biasing with negative feedback, temperature compensation circuits.

3. High-Frequency Behavior

• Hybrid-π model:

  • $$\displaystyle g_m = I_C / V_T $$

  • $$\displaystyle r_\pi = \beta / g_m $$

  • $$\displaystyle C_\pi = C_{be} + C_{bc} $$ (Miller effect)

  • $$\displaystyle C_\mu = C_{bc} $$ (base-collector depletion capacitance)

• f_T: $$\displaystyle f_T = \frac{g_m}{2\pi (C_\pi + C_\mu)} $$; limited by $$\displaystyle C_\mu $$ and $$\displaystyle r_b $$.

C. Diode Models

• Shockley Equation:

$$I = I_S \left( e^{\frac{V}{n V_T}} - 1 \right)$$

• $$\displaystyle I_S $$ (reverse saturation): $$\displaystyle \propto A \cdot D_n / L_n $$; depends on area, doping, lifetime.

• Ideality factor $n$: 1 (diffusion), 2 (recombination in depletion).

D. Passive Component Models in ICs

• Resistors:

  • Diffusion resistor: $$\displaystyle R = \frac{L}{W} \cdot R_{sq} $$; $$\displaystyle R_{sq} = 1/(q \mu N_{sub} t_{dep}) $$.

  • Poly resistor: $R \propto L/W$, TCR ~ -100 ppm/°C.

  • Pinch-off: High $$\displaystyle V_{DS} $$ → resistance increases.

• Capacitors:

  • MOS capacitor: $$\displaystyle C = \frac{\epsilon_{ox}}{t_{ox}} $$ (accumulation), depletion (voltage-dependent), inversion.

  • MIM capacitor: Metal-Insulator-Metal; low voltage coefficient.

• Inductors: Spiral inductors (Al/Cu) on top metal; model includes series $R$, parallel $$\displaystyle C_{sub} $$.

• Utilization of Semiconductor Models: Diode model for p-n junction capacitance; BJT for base resistance in interconnect modeling.

Design Rules and Simulation

A. Design Rules

• Lambda (λ) based: All dimensions in multiples of λ (half minimum feature size).

  • Width: $W \geq 2\lambda$

  • Spacing: $S \geq 2\lambda$

  • Overlap: $O \geq \lambda$

• Purpose: Ensure mask alignment tolerance, process variations don’t cause shorts/opens.

• Process parameters: $$\displaystyle \lambda = \frac{1}{2} \cdot \text{minimum printable feature} $$.

B. Circuit Simulation (SPICE)

• Need: Verify functionality, performance (timing, power), robustness before tape-out.

• Significance: Reduces fabrication cycles, optimizes design, predicts yield.

• SPICE Analyses:

  • DC: Operating point, transfer curves.

  • AC: Small-signal frequency response (gain, phase).

  • Transient: Time-domain response (delay, rise/fall).

  • Noise: Noise margin, sensitivity.

• Flowchart:

  1. Input: Netlist (devices, connections, models).

  2. Parse: Check syntax, build nodal matrix.

  3. Solve: Iterative (Newton-Raphson) for nonlinear devices.

  4. Output: Voltages, currents, plots.

• Device Modeling in SPICE: MOSFET (Level 1-3, BSIM), BJT (Gummel-Poon), diode (Shockley).

Latch-up and Reliability

A. Latch-up Mechanism

• Physical origin: Parasitic p-n-p-n thyristor (p⁺ source → n-well → p-substrate → n⁺ source of adjacent NMOS).

• Triggering conditions:

  1. Substrate resistance $$\displaystyle R_{sub} $$: High $$\displaystyle R_{sub} $$ → voltage drop → forward bias of parasitic base-emitter.

  2. Injection current: $$\displaystyle I_{inj} $$ from NMOS drain (avalanche) or PMOS source.

  3. Power supply transients: $$\displaystyle dV_{DD}/dt $$ induces displacement current.

• Result: Low-impedance path $$\displaystyle V_{DD} $$ → $GND$ → thermal runaway.

B. Prevention Techniques

• Internal:

  • Guard rings: p⁺ in n-well (around PMOS), n⁺ in p-sub (around NMOS) → collect minority carriers, reduce $$\displaystyle R_{sub} $$.

  • Well contacts: Frequent n⁺ contacts in n-well, p⁺ in p-sub → lower well resistance.

  • Epitaxial substrate: Thin epi-layer on p⁺ substrate → shorts parasitic thyristor.

  • Twin-tub: Isolated tubs reduce lateral resistance.

• External: Current limiting resistors, $$\displaystyle V_{DD} $$ slew rate control.

C. Impact on Fabrication

• Effects: Permanent damage, yield loss, reliability risk.

• Resolution: Latch-up testing (ILIM), layout rule enforcement (spacing/contacts), process modifications (SOI).

Digital System Components

A. Register Storage Circuits

• Types:

  • Static (SR): Feedback (cross-coupled inverters); holds data as long as power on.

  • Dynamic (DR): Capacitor storage; needs periodic refresh.

  • Quasi-static (QSR): Combines static master with dynamic slave; high density, non-destructive read.

  • Astatic: No stable states; used in high-speed pipelines.

• Timing Parameters:

  • Setup time $$\displaystyle t_{su} $$: Data must be stable before clock edge.

  • Hold time $$\displaystyle t_h $$: Data must be stable after clock edge.

  • Propagation delay $$\displaystyle t_{pd} $$: Clock-to-output delay.

  • Derivation: $$\displaystyle t_{pd} = t_{pd,clk→Q} + t_{logic} $$; $$\displaystyle t_{su}, t_h $$ from flip-flop internal delays.

• Comparison QSR vs SR:

  • QSR: Smaller area (no cross-couple), but requires non-overlapping clocks.

  • SR: Larger, but simpler clocking.

• Case Study: Nonmetal register cells (e.g., pass-transistor based) → reduced capacitive load, lower power.

B. Microcoded Controllers

• Architecture:

  • Control Store (ROM/RAM): Microinstructions.

  • Microsequencer: Generates next microaddress (based on condition codes).

  • Microinstruction fields: Control signals for datapath.

• Operation: Each machine instruction → sequence of microinstructions. Horizontal (wide, parallel) vs vertical (compact, sequential).

• Role: Simplifies complex instruction set, easy to modify.

C. Systolic Arrays

• Design Principles:

  • Regular 2D array of identical PEs (Processing Elements).

  • Local communication (nearest neighbor).

  • Synchronous data flow: Data pipelined rhythmically (like heart beat).

• Implementation Challenges:

  • Clock distribution skew.

  • I/O bandwidth matching.

  • Fault tolerance.

• Advantages: High throughput, regular layout, scalable parallelism (matrix multiply, FFT).

D. Algotronix Architecture

• Structure: Bit-serial, word-parallel processor with distributed control.

  • ALUs in grid, each with local memory.

  • Global bus for configuration.

• Functionality: Reconfigurable for different algorithms (e.g., sorting, convolution).

• Significance: Early FPGA-like concept; high performance for regular algorithms, but limited for irregular tasks.

Performance, Packaging, and Testing

A. Scaling in VLSI

• Definition: Shrinking dimensions (length, width, oxide, voltage) by factor $$\displaystyle S > 1 $$.

• Types:

  • Constant-field (Dennard): $$\displaystyle V_{DD} \propto L $$, $$\displaystyle I_{DS} \propto W/L $$ → power density constant.

  • Constant-voltage: $$\displaystyle V_{DD} $$ fixed → field increases → short-channel effects.

• Effects:

  • Speed: $f \propto 1/L$ (delay $$\displaystyle \propto L^2 $$ in constant-field).

  • Power: $$\displaystyle P \propto f C V^2 $$; $C \propto W$ → $P \propto S$ (constant-field) or $$\displaystyle P \propto S^2 $$ (constant-voltage).

  • Performance: Increased density, but leakage (subthreshold, BTBT) dominates at deep submicron.

B. Packaging & Testing

• Packaging Steps:

  1. Wafer dicing: Saw cut.

  2. Die attach: Chip on leadframe/substrate.

  3. Wire bonding: Al/Au wires from pad to lead.

  4. Encapsulation: Plastic/ceramic mold.

  5. Marking, testing.

• Testing:

  • Parametric: $$\displaystyle I_{DD} $$, functionality.

  • Burn-in: Elevated temp/voltage → accelerate failure (infant mortality).

  • Automated Test Equipment (ATE): High-speed digital/analog tests.

• Importance: Ensures reliability, screens defects, meets specs.

Design Methodologies and Technologies

A. Random Logic vs Structured Logic

B. Hybrid Technology (BiCMOS)

• Concept: Combine bipolar (high $$\displaystyle g_m $$, speed) and CMOS (low power, density).

• Implementation: Bipolar transistors in n-well/p-substrate; CMOS over shallow trench isolation.

• Benefits: High drive, low power, analog/RF integration.

• Applications: Analog front-ends, high-speed I/O, mixed-signal SoCs.

C. Bipolar Technology

• Characteristics: High $$\displaystyle f_T $$ (>50 GHz), high gain, high power.

• Role in VLSI: Used for analog/RF blocks, drivers; limited by power and density.

• Process: Isolation (oxide/nitride), multiple implants, polyemitter.

D. Interconnects in CMOS

• Role: Connect transistors, distribute clock/power.

• Impact:

  • Delay: $$\displaystyle t_{pd} \propto RC $$; becomes dominant over gate delay (<90nm).

  • Power: Dynamic $$\displaystyle P_{sw} \propto C \cdot f \cdot V^2 $$; $C \propto$ length, coupling.

  • Signal Integrity: Crosstalk, reflection, EM.

• Solutions: Low-k dielectrics, Cu, repeaters, shielding.

[!TIP] Exam Focus:

• Derive MOSFET I-V (triode, saturation) and Ebers-Moll equations—appears every year.

• Compare n-well vs twin-tub with diagrams.

• Latch-up mechanism & prevention (guard rings, well contacts) is high-yield.

• SPICE analyses (DC, AC, transient) and design rules (λ-based) are direct questions.

• Scaling effects on power/speed: know constant-field vs constant-voltage.

• Algotronix & Systolic Arrays: concise description with architecture.

• Timing parameters ($$\displaystyle t_{su}, t_h, t_{pd} $$) for registers—derive from flip-flop delays.

• Photolithography steps and oxidation models (Deal-Grove) are frequently asked.