EC-701 VLSI Design - Dec 2025 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aDiscuss each step involved from wafer preparation to final testing, highlighting the importance of cleanliness and process control.
   How to answer

   • Outline wafer preparation: crystal growth, slicing, polishing, cleaning
   • List fabrication steps: oxidation, lithography, etching, diffusion, ion implantation, metallization
   • Explain final testing: wafer probe, dicing, packaging, final test
   • Emphasize role of cleanliness and process control in yield and reliability
2. 7 Marks
   bDraw and explain the cross-sectional views of a MOS transistor at various stages of fabrication.
   How to answer

   • Define MOS transistor structure and fabrication sequence
   • Sketch cross-sectional views at oxidation, gate formation, source/drain, metallization stages
   • Explain each stage process and structural change
   • Highlight importance of sequence for device characteristics
3. 7 Marks
   aExplain $\lambda$-based design rules and their importance in ensuring reliable fabrication.
   How to answer

   • Define lambda-based design rules and lambda scaling concept
   • List key rules: width, spacing, extension, overlap in lambda units
   • Explain need for manufacturability and process independence
   • Discuss importance in reliable fabrication, yield and avoiding design rule violations
4. 7 Marks
   bExplain the DC model of a MOSFET. Derive the equations for different regions of operation and sketch the ID-VDS characteristics.
   How to answer

   • Define MOSFET DC model and terminal voltages
   • Derive $I_D$ equations for cutoff, linear/triode and saturation regions
   • Define threshold voltage and channel-length modulation effect
   • Sketch $I_D$-$V_{DS}$ characteristics for different $V_{GS}$
5. 7 Marks
   aExplain the Ebers-Moll model of a BJT. Derive the equations for emitter and collector currents.
   How to answer

   • Describe Ebers-Moll model concept with two back-to-back diodes and controlled sources
   • Present equivalent circuit for NPN/PNP BJT
   • Derive emitter current and collector current equations with alpha parameters
   • Discuss modes: active, saturation, cutoff
6. 7 Marks
   bWhat do you understand by passive component models? Discuss the modeling of resistors, capacitors and inductors in integrated circuits.
   How to answer

   • Define passive component models in IC context
   • Discuss integrated resistor modeling: sheet resistance, parasitics
   • Discuss capacitor modeling: MOS, poly-poly, MIM and parasitics
   • Discuss inductor modeling: spiral inductor, series resistance, substrate loss
7. 7 Marks
   aWhat is circuit simulation? Explain the need and significance of circuit simulation in VLSI design.
   How to answer

   • Define circuit simulation and its types
   • Explain need: verification before fabrication, cost and time saving
   • Discuss significance in VLSI: DC, AC, transient analysis, performance optimization
   • Give examples of tools like SPICE
8. 7 Marks
   bDerive the expression for large signal diode current based on the Shockley diode equation. Explain the significance of reverse saturation current and ideality factor.
   How to answer

   • State Shockley diode equation $I = I_S(e^{V/nV_T}-1)$
   • Derive large-signal current expression and assumptions
   • Define reverse saturation current $I_S$ and its physical significance
   • Explain ideality factor n and deviations from ideal behavior
9. 7 Marks
   aExplain the Level 2 MOSFET model and how it improves upon the Level 1 model.
   How to answer

   • Outline Level 1 MOSFET model limitations
   • Explain Level 2 model additions: mobility degradation, velocity saturation, small-geometry effects
   • Compare accuracy and parameters of Level 1 vs Level 2
   • Discuss improvement in short-channel modeling
10. 7 Marks
    bExplain the design and working of register storage circuits used in digital systems. Derive timing parameters such as setup time, hold time and propagation delay.
    How to answer

    • Describe register storage circuits: latches, flip-flops, register files
    • Explain design and working with clocking
    • Define setup time, hold time and propagation delay
    • Derive timing constraints for reliable operation
11. 7 Marks
    aWhat is a micro-coded controller? Explain its architecture and operation in detail.
    How to answer

    • Define micro-coded controller and microinstruction concept
    • Describe architecture: control memory, sequencer, microinstruction register
    • Explain operation: fetch, decode, execute micro-operations
    • Compare with hardwired control advantages
12. 7 Marks
    bWhat is Algotronix architecture? Describe its structure, functionality and significance in high-performance VLSI systems.
    How to answer

    • Define Algotronix architecture and its context
    • Describe structure: configurable logic blocks and interconnect
    • Explain functionality and programming model
    • Discuss significance in high-performance VLSI systems
13. 7 Marks
    aWhat is the twin-tub CMOS process? Explain its fabrication steps and advantages over n-well and p-well processes.
    How to answer

    • Define twin-tub CMOS process
    • Outline fabrication steps: twin well formation, gate, source/drain, contacts
    • Compare with n-well and p-well processes
    • List advantages: balanced performance, latch-up control, independent threshold optimization
14. 7 Marks
    bDescribe the conditions and mechanisms that trigger latch-up in CMOS circuits. Explain the role of substrate resistance, injection current and power supply transients in initiating latch-up events.
    How to answer

    • Explain parasitic pnpn thyristor structure in CMOS
    • Describe triggering: substrate resistance voltage drop, injection current, supply transients
    • Explain regenerative feedback mechanism of latch-up
    • Discuss prevention by layout and process measures
15. 14 Marks
    Write short notes on any two:

    1. a)Packaging and testing
    2. b)MOS Models
    3. c)Systolic Arrays
    4. d)Internal Latch up Prevention Techniques
    How to answer

    • Select any two topics from packaging, MOS models, systolic arrays, latch-up prevention
    • Define each selected topic with key concepts
    • Explain working/principles with neat sketch where applicable
    • Mention significance in VLSI design flow