EC-701 VLSI Design - Jun 2025 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aDefine scaling in VLSI design. Explain its effects on power, speed and performance.
   How to answer

   • Define scaling as proportional reduction of device dimensions and voltages
   • Explain constant-field vs constant-voltage scaling rules
   • Discuss effects on power dissipation, speed/delay and density/performance
   • Mention scaling limits like short-channel effects and interconnect issues
2. 7 Marks
   bDescribe the photolithography process and its importance in IC manufacturing.
   How to answer

   • Define photolithography and its role in pattern transfer
   • List steps: cleaning, oxidation, photoresist coating, exposure, development, etching, stripping
   • Explain masks, UV light and resolution
   • Discuss importance for miniaturization, yield and IC manufacturing
3. 7 Marks
   aDiscuss the importance of IC testing in VLSI manufacturing. Explain the burn-in test and its role in reliability assessment.
   How to answer

   • Explain need for IC testing to ensure functionality, yield and reliability
   • Describe levels: wafer, packaged, system level testing
   • Explain burn-in test: elevated voltage/temperature stress to weed infant mortality
   • Discuss role in reliability assessment and bathtub curve
4. 7 Marks
   bExplain DC models for semiconductor devices. Derive the DC current-voltage (I-V) characteristics for a MOSFET in different regions of operation.
   How to answer

   • Explain DC models: ideal, Level 1/2/3, BSIM overview for diodes, BJT, MOSFET
   • Write gradual channel approximation assumptions
   • Derive $I_D$ in cutoff, linear/triode and saturation regions
   • Show $I_D-V_{DS}$ curves and threshold, channel-length modulation effect
5. 7 Marks
   aExplain the body effect in MOSFETs and its impact on threshold voltage.
   How to answer

   • Define body effect with source-to-body bias $V_{SB}$
   • Explain depletion charge and threshold voltage increase formula
   • Give $V_{TH} = V_{T0} + \gamma(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F})$
   • Discuss impact on speed, power and design in CMOS/n-well
6. 7 Marks
   bWhat do you understand by passive component models? Discuss the modeling of resistors, capacitors, and inductors in integrated circuits.
   How to answer

   • Define passive component models in IC context
   • Discuss integrated resistor types and parasitics
   • Discuss MOS/MIM capacitors and parasitic capacitance
   • Discuss spiral inductors, Q-factor and area limitations
7. 7 Marks
   aDiscuss the different types of analyses performed in SPICE (e.g. DC, AC, transient, noise analysis).
   How to answer

   • List SPICE analysis types: DC operating point, DC sweep, AC, transient, noise, etc.
   • Explain purpose and inputs/outputs of each analysis
   • Mention frequency vs time domain setup
   • Give example applications for VLSI verification
8. 7 Marks
   bDiscuss the impact of base resistance and capacitance on BJT high-frequency behavior.
   How to answer

   • Identify base resistance $r_b$ and junction/depletion capacitances
   • Explain effect on $f_T$, $f_{max}$ and gain-bandwidth
   • Discuss Miller effect and high-frequency roll-off
   • Mention modeling for RF BJT design
9. 7 Marks
   aHow is noise modeled in SPICE simulations for MOSFETs? Explain.
   How to answer

   • List MOSFET noise sources: thermal, flicker, shot
   • Explain SPICE noise models and parameters
   • Describe .NOISE analysis setup
   • Discuss scaling effect on noise in VLSI
10. 7 Marks
    bDefine random logic and structured logic. Explain the advantages and disadvantages of structured logic over random logic.
    How to answer

    • Define random logic vs structured logic (PLA, gate array, standard cell)
    • Compare design effort, area, speed and flexibility
    • List advantages of structured logic: regularity, testability, time-to-market
    • List disadvantages: overhead, performance penalty vs full-custom random
11. 7 Marks
    aWhat are quasi-static register cells and how do they differ from static and dynamic registers?
    How to answer

    • Define quasi-static register cells with weak feedback keeper
    • Contrast with static (cross-coupled latch) and dynamic (capacitive storage)
    • Discuss power, area, leakage and clocking differences
    • Mention applications in datapath and low-power design
12. 7 Marks
    bWhat is a Systolic array. What are the challenges in implementing systolic array architectures.
    How to answer

    • Define systolic array as rhythmic pipelined PE array
    • Explain data flow: broadcast, pipelined, systolic
    • Discuss challenges: mapping, synchronization, I/O bandwidth, scalability
    • Mention area, fault tolerance and design complexity
13. 7 Marks
    aExplain the step-by-step fabrication of an n-well CMOS transistor.
    How to answer

    • Start from p-substrate, n-well formation and active area definition
    • Describe gate oxidation, polysilicon, source/drain implants for NMOS/PMOS
    • Explain contacts, metallization and passivation steps
    • Include cross-sectional sequence and twin-tub concept
14. 7 Marks
    bWhat are layout design rules and why are they essential in CMOS design?
    How to answer

    • Define layout design rules: lambda vs micron rules
    • Explain width, spacing, overlap, extension rules
    • Discuss need to ensure manufacturability, yield and reliability
    • Mention DRC and avoidance of short/open, latchup
15. 14 Marks
    Write a short note on any two

    1. a)Hybrid Technology
    2. b)Diode Models
    3. c)Algotronix
    4. d)Latchup Triggering
    How to answer

    • Select any two topics from list
    • Define each term with key principle and structure
    • Explain relevance to VLSI modeling/design
    • Give example/application and limitations