EC-701 VLSI Design - Nov 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aWhat are the different technologies use in VLSI Design? Explain in brief.
   How to answer

   • List VLSI technologies - NMOS, CMOS, BiCMOS, GaAs, SOI
   • Brief features of each technology
   • Comparison on speed, power, density
   • Applications and selection criteria
2. 7 Marks
   b"Microelectronics Field plays a vital role in VLSI designing" Prove this statement with the help of a practical example.
   How to answer

   • Define microelectronics field scope
   • Link to VLSI scaling, integration, fabrication
   • Practical example e.g. CMOS IC / microprocessor
   • Justify vital role conclusion
3. 7 Marks
   aDiscuss the packaging and testing steps of IC production process in detail.
   How to answer

   • Define IC packaging types
   • Steps: wafer dicing, die attach, wire bonding, encapsulation
   • Testing steps: wafer probe, final test, burn-in
   • Purpose of packaging and testing
4. 7 Marks
   bDiscuss about the design rules and process parameters of VLSI circuits.
   How to answer

   • Define design rules - lambda, micron rules
   • Process parameters - threshold, oxide thickness, diffusion
   • Need for DRC and scaling
   • Impact on yield and performance
5. 7 Marks
   aClassify various MOSFET Models and explain any one of them.
   How to answer

   • Classify MOSFET models - Level 1,2,3, BSIM, EKV
   • Basis of classification - geometry, physics
   • Explain any one model in detail
   • I-V characteristics and parameters
6. 7 Marks
   bDerive a relation for the Sub threshold operations. How we can implement this operation on short channel devices?
   How to answer

   • Define subthreshold region $V_{GS}<V_{TH}$
   • Derive $I_{sub}$ exponential relation with subthreshold slope
   • Short-channel effects on subthreshold
   • Implementation techniques for short-channel devices
7. 7 Marks
   aDerive a necessary expressions for short channel devices and elaborate their results with the help of a suitable example.
   How to answer

   • Define short-channel effects - velocity saturation, DIBL, punchthrough
   • Derive necessary expressions
   • Explain results with diagrams
   • Illustrate with suitable example
8. 7 Marks
   bDerive a relation for Temperature Dependence of the BJT.
   How to answer

   • State BJT current temperature dependence
   • Derive $I_C$ vs $T$ relation using $I_S(T)$
   • Explain bandgap, mobility effects
   • Conclude temperature coefficient
9. 7 Marks
   aWrite any five differences between Random Logic and Structured Logic.
   How to answer

   • Define Random Logic and Structured Logic
   • Compare on 5 aspects: design, area, speed, flexibility, application
   • Present in tabular form
   • Examples of each
10. 7 Marks
    bWhat do you mean by Astatic register cell? Explain the multiplication process and general linear system solver mechanism.
    How to answer

    • Define Astatic register cell
    • Explain multiplication process using register cells
    • Explain general linear system solver mechanism
    • Applications in VLSI
11. 7 Marks
    aDiscuss the principle of Quasi Static register cells. Discuss any practical case study of VLSI devices with mentioned register cells.
    How to answer

    • Define Quasi Static register cells
    • Explain principle of operation and charge storage
    • Practical case study of VLSI device using them
    • Advantages and limitations
12. 7 Marks
    bExplain the principle of Microprocessor Design Methods. Give any one practical application.
    How to answer

    • List microprocessor design methods - custom, semi-custom, FPGA
    • Explain principle of design flow
    • Steps: specification, RTL, synthesis, layout
    • One practical application
13. 7 Marks
    aElaborate the principle of Basic n-well CMOS Process. Discuss the Twin tub process and its disadvantages in fabrication technique.
    How to answer

    • Describe basic n-well CMOS process steps
    • Explain twin-tub process flow
    • Compare n-well vs twin-tub
    • Disadvantages in fabrication technique
14. 7 Marks
    bAnalyze the effects of Latch up's triggering in chip fabrication techniques and how we can resolve the problems due to latch up?
    How to answer

    • Define latch-up and parasitic thyristor
    • Analyze triggering effects on chip fabrication
    • Problems: high current, device failure
    • Prevention: guard rings, SOI, layout rules
15. 14 Marks
    Write short notes:

    1. a)Latch up
    2. b)Hybrid Technology
    3. c)Bipolar Technology
    4. d)Interconnects
    How to answer

    • Define latch-up with parasitic BJT action
    • Explain hybrid and bipolar technologies
    • Explain interconnects - types, delays, materials
    • Give applications and limitations