UNIT 2: VLSI Design - Comprehensive Study Notes

I. Fabrication Process & CMOS Technology

Wafer Preparation and Manufacturing Flow

• Silicon Wafer Production:

  • Czochralski (CZ) Method: Most common. A seed crystal is dipped into molten silicon and rotated/pulled to form a cylindrical ingot. Doping can be done during growth.

  • Float-Zone (FZ) Method: Higher purity, lower defect density. A polycrystalline rod is passed through a heating coil, melting a narrow zone that moves along the rod.

  • Slicing & Polishing: Ingot is sliced into wafers (typically 150mm, 200mm, 300mm diameter). Wafers are lapped, polished (mirror finish), and cleaned.

• Cleanroom Standards:

  • Classified by particle count per cubic foot (e.g., Class 1 = ≤1 particle/ft³).

  • Contamination Control: Gowning, air showers, laminar flow benches, chemical handling.

Photolithography

• Process Steps:

  1. Photoresist Coating: Spin coating of liquid photoresist (positive/negative) to uniform thin film.

  2. Soft Bake: Evaporate solvent.

  3. Exposure: UV light through photomask (reticle). Pattern transfer.

  4. Development: Chemical wash removes exposed (positive) or unexposed (negative) resist.

  5. Hard Bake: Harden resist pattern.

  6. Etching: Transfer pattern into underlying layer (wet or dry etch).

• Role: Primary pattern transfer step. Resolution limits feature scaling (Rayleigh criterion: \( R = k_1 \frac{\lambda}{NA} \)).

Oxidation, Diffusion, and Ion Implantation

• Thermal Oxidation:

  • Dry Oxidation (O₂): Slow, high-quality SiO₂. \( x^2 + A x = B(t + \tau) \) (Deal-Grove model).

  • Wet Oxidation (H₂O/H₂O₂): Faster, lower quality. Used for field oxide.

• Dopant Introduction:

  • Diffusion: High-temperature drive-in of dopant from deposited source. Gaussian/erfc profiles. Less precise.

  • Ion Implantation: Accelerated ions implanted at precise energy/dose. More controllable, requires annealing to repair damage. Preferred in modern processes.

Metallization and Interconnect Formation

• Metal Deposition:

  • Sputtering: Argon ions knock atoms from target. Good step coverage.

  • Evaporation: Thermal/e-beam evaporation. Poor step coverage.

• Interconnect Layers:

  • Multiple metal layers (M1, M2, ...) separated by dielectric (SiO₂, low-k).

  • Contacts: openings to active area.

  • Vias: openings between metal layers.

  • Aluminum traditionally used; now Cu (lower resistivity, but requires barrier/diffusion layers like SiN, TaN).

CMOS Process Variants

Design Rules

• λ-based Rules: Minimum dimensions expressed as multiples of λ (half the minimum gate length). Ensures scalability.

  • Minimum Width (W): e.g., \( W_{min} = 2\lambda \)

  • Minimum Spacing (S): e.g., \( S_{min} = 2\lambda \)

  • Enclosure (E): e.g., \( E_{contact} = \lambda \)

  • Extension (X): e.g., \( X_{active-over-gate} = \lambda \)

• Importance: Ensure manufacturability (no opens/shorts), reliability (prevent diffusion overlap), and yield.

Scaling Theory

• Constant-Field Scaling (Dennard):

  • Dimensions ↓ by factor \( S \), voltage ↓ by \( S \), doping ↑ by \( S \).

  • Effects:

    • Delay \( \tau \propto \frac{L^2}{\mu V} \) → ↓ by \( S \)

    • Power density \( P/A \propto V^2 f \) → constant

    • Electric field constant.

• Constant-Voltage Scaling:

  • Dimensions ↓, voltage constant.

  • Effects:

    • Delay ↓

    • Power density ↓ (good for battery)

    • Electric field ↑ → reliability issues (hot carriers, oxide breakdown).

Hybrid and Bipolar Technologies

• BiCMOS: Integration of BJT (high speed, high drive) and CMOS (low static power, high density).

  • Process: Add bipolar steps (deep n-well, p-base, n+ emitter) to CMOS.

  • Applications: High-performance logic (e.g., ECL drivers), analog/RF.

• Trade-offs: Increased cost, complexity, area vs. superior \( f_T \), gain, noise margin.

II. Device Physics and Modeling

A. MOSFET Models

DC Large-Signal Models

• Level 1 (Square-Law) Model:

  • Assumptions: Long-channel, gradual channel, no short-channel effects, mobility constant.

  • Threshold Voltage: \( V_{TH} = V_{FB} + 2\phi_F + \frac{\sqrt{2q\varepsilon_{si} N_A 2\phi_F}}{C_{ox}} \)

  • Current Equations:

    • Triode (Linear) Region (\( V_{GS} > V_{TH}, V_{DS} < V_{GS} - V_{TH} \)):

      \[ I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_{TH})V_{DS} - \frac{V_{DS}^2}{2} \right] \]

    • Saturation Region (\( V_{GS} > V_{TH}, V_{DS} \geq V_{GS} - V_{TH} \)):

      \[ I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{TH})^2 (1 + \lambda V_{DS}) \]

      where \( \lambda \) = channel-length modulation parameter.

  • Limitations: Inaccurate for short-channel devices; ignores mobility degradation, velocity saturation.

• Level 2 Model:

  • Improvements:

    • Mobility Degradation: \( \mu = \frac{\mu_0}{1 + \theta (V_{GS} - V_{TH})} \)

    • Threshold Voltage Roll-off: \( V_{TH} = V_{TH0} - \gamma \left( \sqrt{1 + \frac{C_{ox} V_{SB}}{q \varepsilon_{si} N_A}} - \sqrt{1 + \frac{C_{ox} \phi_F}{q \varepsilon_{si} N_A}} \right) \)

    • Includes substrate bias (body) effect explicitly.

    • Better for moderate channel lengths.

Short-Channel Effects

• Drain-Induced Barrier Lowering (DIBL):

  • High \( V_{DS} \) lowers potential barrier at source end → \( V_{TH} \) decreases with \( V_{DS} \).

  • Effect: Increased leakage, loss of saturation.

• Channel Length Modulation (CLM):

  • Pinch-off point moves toward source with \( V_{DS} \) → effective \( L \) decreases → \( I_D \) increases in saturation.

• Velocity Saturation:

  • High lateral field → carrier velocity saturates at \( v_{sat} \).

  • Current (for \( V_{DS} > V_{sat} L \)): \( I_D \approx W C_{ox} v_{sat} (V_{GS} - V_{TH}) \) (linear in \( V_{GS} \), independent of \( L \)).

• Impact: Degrades analog performance, increases leakage, requires modified models (e.g., Level 3, BSIM).

Subthreshold Operation

• Weak Inversion: \( V_{GS} < V_{TH} \), current dominated by diffusion.

  \[ I_D \approx I_0 e^{\frac{V_{GS} - V_{TH}}{n V_T}} \left(1 - e^{-\frac{V_{DS}}{V_T}}\right) \]

  where \( I_0 = \mu C_{ox} \frac{W}{L} V_T^2 \), \( n = 1 + \frac{C_{dep}}{C_{ox}} \) (subthreshold slope factor), \( V_T = kT/q \).

• Subthreshold Slope (SS): \( SS = \ln(10) \cdot n V_T \approx 60 \text{ mV/dec} \) at 300K for \( n=1 \).

  • Lower SS → sharper turn-off → lower leakage.

• Applications: Ultra-low-power circuits, sensor interfaces.

Body Effect

• Threshold Voltage Dependence:

  \[ V_{TH} = V_{TH0} + \gamma \left( \sqrt{|\phi_F + V_{SB}|} - \sqrt{|\phi_F|} \right) \]

  where \( \gamma = \frac{\sqrt{2q \varepsilon_{si} N_A}}{C_{ox}} \) (body effect coefficient).

• Impact: In CMOS, PMOS body tied to VDD, NMOS to GND → no body effect in digital gates. In analog (e.g., current mirrors), \( V_{SB} \) varies → \( V_{TH} \) mismatch.

Small-Signal High-Frequency Models

• Hybrid-π Model:

  • Transconductance: \( g_m = \frac{\partial I_D}{\partial V_{GS}} \approx \frac{2 I_D}{V_{GS} - V_{TH}} \) (saturation) or \( \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{TH}) \).

  • Output Conductance: \( g_{ds} = \frac{\partial I_D}{\partial V_{DS}} \approx \lambda I_D \).

  • Capacitances:

    • \( C_{gs} \): Gate-source overlap + channel charge.

    • \( C_{gd} \) (Miller): Gate-drain overlap + channel charge (sensitive to \( V_{DS} \)).

    • \( C_{db} \): Drain-bulk junction.

• Cutoff Frequency:

  \[ f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})} \]

• Maximum Oscillation Frequency:

  \[ f_{max} = \frac{f_T}{2 \sqrt{R_g (g_{ds} + g_{mb} + 2\pi f_T C_{gd})}} \]

  where \( R_g \) = gate resistance, \( g_{mb} \) = body transconductance.

B. BJT Models

• Ebers-Moll Model:

  • Emitter Current (forward active):

    \[ I_E = I_{ES} \left( e^{\frac{V_{BE}}{V_T}} - 1 \right) - \alpha_R I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right) \]

  • Collector Current:

    \[ I_C = \alpha_F I_E - I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right) \]

  where \( I_{ES}, I_{CS} \) = saturation currents, \( \alpha_F, \alpha_R \) = forward/reverse common-base gains.

• Temperature Dependence:

  • \( V_{BE} \downarrow \approx -2 \text{ mV/°C} \) (due to \( V_T \uparrow \) and \( I_S \uparrow \)).

  • \( \beta \) may vary with temperature.

• High-Frequency Effects:

  • Base Resistance (\( r_b \)): Limits \( f_T \).

  • Junction Capacitances:

    • \( C_{je} \): Emitter-base depletion.

    • \( C_{jc} \): Collector-base depletion (voltage-dependent).

    • \( f_T = \frac{\beta_0}{2\pi (C_{je} + C_{jc})} \) (approx).

C. Diode Models

• Shockley Diode Equation:

  \[ I = I_S \left( e^{\frac{V}{n V_T}} - 1 \right) \]

  • \( I_S \): Reverse saturation current (depends on area, doping, temperature: \( I_S \propto T^3 e^{-E_g/kT} \)).

  • \( n \): Ideality factor (1 for diffusion, 2 for recombination).

• Significance: Models forward conduction and reverse leakage. Basis for all pn junction devices.

D. Passive Component Models in ICs

III. Circuit Simulation with SPICE

• Purpose & Significance:

  • Design Verification: Check functionality, performance before tape-out.

  • Performance Prediction: Timing, power, noise margins.

  • Yield Analysis: Monte Carlo simulations for process variations.

  • Model Validation: Compare with silicon data.

• Types of Analyses:

  • DC Analysis: Operating point, transfer curves (e.g., \( V_{in} \) vs \( V_{out} \)).

  • AC Analysis: Small-signal frequency response (gain, phase, \( f_T \)).

  • Transient Analysis: Time-domain (switching, delays, power).

  • Noise Analysis: Thermal (channel), shot (junction), flicker (1/f).

• Device Model Parameter Extraction:

  • Process-specific parameters (\( \mu_0, V_{TH0}, \lambda, \gamma \)) extracted from test structures.

  • Temperature effects via \( T_{NOM} \), \( X_T \) parameters.

• Noise Modeling in SPICE:

  • MOSFET: Thermal noise \( \overline{i_d^2} = 4kT \gamma g_m \) ( \( \gamma \approx 2/3 \) for long-channel), flicker noise \( \overline{i_d^2} \propto 1/f \).

  • BJT: Shot noise \( \overline{i_c^2} = 2q I_C \), base resistance thermal noise \( 4kT/r_b \).

IV. Reliability, Packaging, and Testing

A. Latch-up in CMOS Circuits

• Physical Mechanism:

  • Parasitic Thyristor: p⁺-n⁺-p-n (PNPN) structure formed by n-well/p-substrate and n⁺/p⁺ diffusion.

  • Regenerative Feedback: If \( I_{n} \beta_N + I_{p} \beta_P \geq 1 \), latch-up triggers → low-impedance path VDD-to-GND → thermal destruction.

• Triggering Conditions:

  • Substrate Resistance (\( R_{sub} \)): High \( R_{sub} \) → voltage drop → forward bias parasitic base-emitter.

  • Injection Current: \( I_{n} \) from NMOS (n⁺ source) or \( I_{p} \) from PMOS (p⁺ source).

  • Power Supply Transients: \( dI/dt \) induces \( L \frac{dI}{dt} \) voltage spikes.

  • Temperature/Process: High temp ↑ leakage; process variations affect \( \beta \).

• Prevention Techniques:

  • Internal:

    • Guard Rings: p⁺ around NMOS (collect \( I_n \)), n⁺ around PMOS (collect \( I_p \)).

    • Substrate Contacts: Low \( R_{sub} \) (many p⁺ taps in n-well, n⁺ taps in p-sub).

    • Epitaxial Substrate: Thin high-resistivity epi on low-resistivity sub → reduces \( R_{sub} \).

    • Silicon-On-Insulator (SOI): Eliminates latch-up path.

  • External: Current limiting resistors, slow \( dV/dt \) power supplies.

• Testing: Latch-up susceptibility test (apply current/voltage stress, monitor supply current).

B. IC Packaging Technologies

• Package Types:

  • DIP (Dual In-line): Through-hole, low frequency.

  • QFP (Quad Flat Pack): Surface mount, fine pitch.

  • BGA (Ball Grid Array): High I/O, good thermal/electrical performance.

  • Flip-Chip: Direct bump attach → shortest interconnect.

• Considerations:

  • Thermal Management: Thermal resistance \( \theta_{JA} \), heat sinks.

  • Electrical: Inductance/capacitance of leads, signal integrity.

  • Mechanical: Stress, reliability.

C. Testing Methodologies

• Burn-in Testing:

  • Purpose: Accelerated life test to eliminate infant mortality (early failures).

  • Conditions: Elevated temperature (125°C) and voltage (1.5-2x nominal) for 48-168 hrs.

• Functional & Parametric Testing:

  • Functional: Verify logic operation (scan test, BIST).

  • Parametric: Measure \( I_{DDQ} \), timing, voltage thresholds.

  • DFT (Design for Testability): Boundary Scan (JTAG), scan chains.

D. Cleanroom Practices and Process Control

• Cleanliness Classes: ISO 14644-1 (Class 1-9). VLSI uses Class 1-5.

• Particle Control: Gowning, air showers, sticky mats, chemical filtration.

• Statistical Process Control (SPC):

  • Monitor key parameters (oxide thickness, sheet resistance) using control charts.

  • Process Monitoring: Use test structures (MOS capacitors, van der Pauw resistors) on wafer edge.

V. Digital System Design Concepts

A. Logic Design Paradigms

• Random Logic:

  • Custom, irregular layout.

  • Pros: Optimized area/speed for specific function.

  • Cons: Design time long, hard to test/verify, not scalable.

• Structured Logic:

  • Regular, repeatable structures (e.g., PLA, gate arrays, standard cells).

  • Pros: Automated design/tools, high testability, predictable timing, scalable.

  • Cons: May be less area-efficient than full custom.

• Microprocessor Design:

  • Structured Approach: Use standard cell libraries, automated place/route.

  • Efficiency: Reuse of functional blocks (ALU, register file), modular design.

B. Register Storage Circuits

• Register Cell Types:

  • Static (6T SRAM): Cross-coupled inverters + access transistors. Non-volatile while powered. Used for registers/caches.

  • Dynamic: Charge on capacitor (1T DRAM). Needs refresh. Smaller area.

  • Quasi-Static:

    • Hybrid: Static master, dynamic slave (or vice versa).

    • Non-Metallization: Avoids metal layer in cell → reduces capacitance, improves speed.

    • Example: Dual-rail dynamic logic with static feedback.

• Timing Parameters:

  • Setup Time (\( t_{su} \)): Data must be stable before clock edge.

  • Hold Time (\( t_h \)): Data must be stable after clock edge.

  • Clock-to-Q Delay (\( t_{cQ} \)): Time from clock edge to output valid.

  • Derivation: Based on transistor switching times, internal node capacitances, clock skew.

C. Microcoded Controllers

• Architecture:

  • Control Store: ROM/RAM holding microinstructions.

  • Microinstruction Format:

    • Horizontal: One bit per control signal → wide, fast.

    • Vertical: Encoded fields → narrow, slower, more compact.

  • Address Generation Logic: Next microaddress from current microinstruction, opcode, status flags.

• Operation:

  1. Fetch microinstruction from control store using micro-PC.

  2. Decode to generate control signals.

  3. Execute one step of instruction.

  4. Update micro-PC (sequential, branch, call, return).

• Advantages: Flexible, easier to modify/debug than hardwired control.

D. Specialized Architectures

• Systolic Arrays:

  • Design Principles:

    • Regular 2D grid of identical processing elements (PEs).

    • Local connectivity: Each PE connects to neighbors (N, S, E, W).

    • Synchronous data flow: Data "pulses" through array in wavefront manner.

  • Implementation Challenges:

    • Synchronization: Clock distribution across array.

    • Routing: Minimize long wires, balance loads.

    • I/O Bandwidth: Must feed data at high rate.

  • Applications: Matrix multiplication, convolution, FFT.

• Algotronix Architecture:

  • Structure: Array of identical processing units (PUs) with local memory and nearest-neighbor interconnect.

  • Functionality: Data-parallel, iterative algorithms. Each PU executes same instruction on different data (SIMD-like).

  • Significance: Early commercial systolic array chip (e.g., IMS T800 transputer). Demonstrated high throughput for signal processing, graphics, scientific computing with efficient communication.

[!TIP] Exam Focus Areas (From Past Papers):

1. Fabrication: n-well vs. twin-tub steps, photolithography, design rules.

2. Device Models: Derive Level 1 MOSFET equations, explain Level 2 improvements, short-channel effects.

3. Latch-up: Mechanism, triggering, prevention (guard rings, epitaxial substrate).

4. Digital Design: Quasi-static registers, microcoded controllers, systolic arrays/Algotronix.

5. SPICE: Purpose, analysis types, noise modeling.

6. Passive Components: Models for resistors/capacitors/inductors in ICs.

7. Scaling: Effects on power/speed, constant-field vs. constant-voltage.

8. BJT/Diodes: Ebers-Moll, Shockley equation, temperature effects.