VLSI Design (EC-701) - Unit 1 Short Notes

UNIT 1: VLSI DESIGN - COMPREHENSIVE SHORT NOTES

I. VLSI FABRICATION TECHNOLOGY & PROCESSES

A. Complete IC Manufacturing Flow

The IC fabrication process is a sequence of highly controlled steps performed in a cleanroom (Class 1-1000) to prevent particulate contamination.

Standard Flow:

1. Wafer Preparation: Starting with a high-purity, single-crystal silicon ingot, wafers are sliced, polished, and cleaned.

2. Oxidation: Thermal growth of a silicon dioxide (SiO₂) layer. Acts as a mask for doping, insulator between layers, and passivation.

3. Photolithography: The pattern transfer step.

   • Apply photoresist (light-sensitive polymer).

   • Align photomask (reticle) and expose to UV light.

   • Develop to remove exposed (positive resist) or unexposed (negative resist) areas.

4. Etching: Remove material not protected by photoresist.

   • Wet Etching: Chemical bath, isotropic.

   • Dry Etching (RIE): Plasma-based, anisotropic, preferred for fine features.

5. Ion Implantation: Dopant atoms (B, P, As) are accelerated into silicon at specific energies/doses. Followed by annealing to repair crystal damage and activate dopants.

6. Metallization: Deposition of conductive layers (Al, Cu, W) to form interconnects. Often uses silicides (e.g., TiSi₂, CoSi₂) to reduce contact resistance.

7. Passivation: Final protective layer (SiO₂, Si₃N₄) to shield the circuit from moisture and mechanical damage.

!TIP: Cleanliness is paramount. A single 0.5µm particle can ruin dozens of chips. Process control (temperature, time, concentration) is critical for yield and device matching.

B. Key Process Steps (Definitions & Importance)

• Oxidation: SiO₂ = Si + O₂. Importance: Excellent insulator, high-quality Si-SiO₂ interface, masks for ion implantation.

• Photolithography: The "printing" process defining feature size. Limiting factor for minimum feature size (resolution λ).

• Metallization: Forms wires connecting devices. Trade-off: Al (easy to deposit, poor electromigration) vs. Cu (better performance, hard to etch, needs barrier/liner).

C. CMOS Transistor Fabrication

1. n-well CMOS Process (for pMOS in n-well):

1. Start with p-type substrate.

2. Grow field oxide (LOCOS) for isolation.

3. Implant n-well (high-dose, high-energy).

4. Gate oxide growth.

5. Poly-silicon deposition, patterning to form gate.

6. Lightly Doped Drain (LDD) implant (n⁻ for nMOS, p⁻ for pMOS).

7. Sidewall spacer formation (Si₃N₄).

8. Source/Drain implants (n⁺ for nMOS, p⁺ for pMOS in n-well).

9. Silicide formation on exposed Si/poly.

10. Interlayer dielectric (ILD) deposition, contact etch, metallization.

2. Twin-Tub CMOS Process:

• Steps: Start with high-resistivity p-type epitaxial layer on p⁺ substrate. Create separate n-tub (for pMOS) and p-tub (for nMOS) by ion implantation in predefined regions. Follow similar steps as n-well for each transistor type.

• Advantages over n-well/p-well:

  • Better isolation between nMOS and pMOS.

  • Reduced latch-up susceptibility (tubs connected to respective supplies via low-resistance contacts).

  • Higher performance (no well resistance penalty for one transistor type).

  • Flexibility in optimizing each transistor independently.

D. Latch-Up in CMOS

• Physical Origin: Formation of a parasitic pnpn thyristor (p⁺ source/n-well/p-substrate/n⁺ source of adjacent nMOS).

  
  p⁺ (nMOS source)
  
      |
  
  n-well
  
      |
  
  p-substrate
  
      |
  
  n⁺ (pMOS source)
  
  

• Triggering Mechanisms:

  1. High substrate/cell resistance: Voltage drop forward-biases parasitic npn base-emitter junction.

  2. Injection current: Excess minority carriers (e.g., from ionizing radiation, forward-biased junction).

  3. Power supply transients: Negative spikes on VDD or positive on VSS.

• Internal Prevention Techniques:

  • Guard Rings: p⁺ ring around nMOS, n⁺ ring around pMOS, tied to VSS/VDD respectively. Provide low-resistance paths for minority carriers.

  • Epitaxial Wafers: Thin, high-resistivity epi-layer on p⁺ substrate drastically reduces lateral substrate resistance.

  • Substrate Contacts: Frequent, low-resistance contacts to VSS (for p-substrate) and well taps to VDD.

  • Twin-Tub Process: (See above).

E. Technology Comparison & Hybrid Approaches

• BiCMOS: Integrates bipolar transistors (high current drive, speed) with CMOS (low power, density). Used in SRAM drivers, high-speed logic, analog front-ends.

II. DEVICE MODELING & CHARACTERISTICS

A. MOSFET DC & Small-Signal Models

1. Level 1 (Square-Law) DC Model:

• Assumptions: Long-channel, uniform doping, gradual channel approximation, no short-channel effects.

• Key Parameters: $$\displaystyle W, L, \mu_n, C_{ox}, V_{th} $$.

• Threshold Voltage: $$\displaystyle V_{th} = V_{FB} + 2\phi_F + \frac{\sqrt{2\epsilon_s q N_a 2\phi_F}}{C_{ox}} $$

• Current Equations:

  • Cutoff: $$\displaystyle V_{GS} < V_{th} $$, $$\displaystyle I_D = 0 $$

  • Triode (Linear): $$\displaystyle V_{GS} > V_{th}, V_{DS} < V_{GS}-V_{th} $$

$$I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS}-V_{th})V_{DS} - \frac{V_{DS}^2}{2} \right]$$

*   **Saturation:** $$\displaystyle V_{GS} > V_{th}, V_{DS} \geq V_{GS}-V_{th} $$

$$I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS}-V_{th})^2 (1 + \lambda V_{DS})$$

    where $\lambda$ is the **channel-length modulation** parameter.

• Transconductance: $$\displaystyle g_m = \frac{\partial I_D}{\partial V_{GS}} = \frac{2I_D}{V_{GS}-V_{th}} $$ (in saturation, ignoring $\lambda$).

2. Level 2 MOSFET Model:

• Improvements over Level 1:

  • Mobility Degradation: $$\displaystyle \mu_{eff} = \frac{\mu_0}{1 + \theta (V_{GS}-V_{th})} $$ (θ: mobility degradation coefficient).

  • Threshold Voltage Roll-off: $$\displaystyle V_{th} $$ decreases with decreasing $L$ (short-channel effect).

  • Drain-Induced Barrier Lowering (DIBL): $$\displaystyle V_{th} $$ decreases with increasing $$\displaystyle V_{DS} $$.

  • Subthreshold Conduction: $$\displaystyle I_D \propto e^{(V_{GS}-V_{th})/nV_T} $$ (n: subthreshold slope factor).

3. Short-Channel Devices:

• Effects:

  • Velocity Saturation: Carrier velocity saturates at $$\displaystyle v_{sat} $$, limiting $$\displaystyle I_D \propto (V_{GS}-V_{th}) $$ not $$\displaystyle (V_{GS}-V_{th})^2 $$.

  • DIBL: Drain field lowers channel potential, reducing $$\displaystyle V_{th} $$ and increasing $$\displaystyle I_D $$ at $$\displaystyle V_{DS}=0 $$.

  • Channel Length Modulation (CLM): More pronounced, $$\displaystyle I_D $$ increases strongly with $$\displaystyle V_{DS} $$.

  • Hot Carrier Effects (HCE): High electric fields near drain cause carrier injection into oxide, degrading device.

• Advantages: Higher speed (less parasitic capacitance), better scalability.

• Limitations: Lower $$\displaystyle V_{th} $$ control, higher leakage, HCE.

4. Body Effect:

• $$\displaystyle V_{th} $$ increases with source-to-substrate reverse bias ($$\displaystyle V_{SB} > 0 $$ for nMOS).

$$V_{th} = V_{th0} + \gamma \left( \sqrt{|2\phi_F + V_{SB}|} - \sqrt{|2\phi_F|} \right)$$

where $$\displaystyle \gamma = \frac{\sqrt{2\epsilon_s q N_a}}{C_{ox}} $$ is the **body effect coefficient**.

5. Subthreshold Operation:

• Region: $$\displaystyle V_{GS} < V_{th} $$, weak inversion.

• Current Relation:

$$I_D = I_0 e^{(V_{GS}-V_{th})/nV_T} (1 - e^{-V_{DS}/V_T})$$

where $$\displaystyle I_0 $$ is a technology parameter, $$\displaystyle n = 1 + \frac{C_{dep}}{C_{ox}} $$ (subthreshold slope factor, ideal n=1), $$\displaystyle V_T = kT/q $$.

• Implementation in Short-Channel: DIBL reduces effective $$\displaystyle V_{th} $$, increasing subthreshold leakage. Requires careful $$\displaystyle V_{th} $$ engineering (halo implants).

B. BJT Models & Characteristics

Ebers-Moll Model (Large-Signal):

• Assumptions: Active mode, uniform doping, low-level injection.

• Equations:

$$I_E = I_{ES} \left( e^{V_{BE}/V_T} - 1 \right) - \alpha_R I_{CS} \left( e^{V_{BC}/V_T} - 1 \right)$$

$$I_C = \alpha_F I_{ES} \left( e^{V_{BE}/V_T} - 1 \right) - I_{CS} \left( e^{V_{BC}/V_T} - 1 \right)$$

where $$\displaystyle I_{ES}, I_{CS} $$ are saturation currents, $$\displaystyle \alpha_F, \alpha_R $$ are forward/reverse common-base current gains.

• Temperature Dependence: $$\displaystyle I_S \propto T^3 e^{-E_g/kT} $$. $$\displaystyle V_{BE} $$ decreases ~2mV/°C. Mitigation: Biasing with negative feedback (emitter resistor), bandgap reference circuits.

High-Frequency Behavior:

• Base Resistance ($$\displaystyle r_b $$): Causes voltage drop, reduces $$\displaystyle V_{BE} $$ at high $$\displaystyle I_C $$, limiting $$\displaystyle f_T $$.

• Junction Capacitances:

  • $$\displaystyle C_{be} $$ (diffusion capacitance): $$\displaystyle C_{be} = \tau_F g_m $$ (charge storage).

  • $$\displaystyle C_{bc} $$ (Miller capacitance): Amplified by Miller effect, critical for high-frequency gain.

  • Transition Frequency: $$\displaystyle f_T = \frac{g_m}{2\pi (C_{be} + C_{bc})} \approx \frac{1}{2\pi \tau_F} $$.

C. Diode Models

Shockley Diode Equation (Large-Signal):

$$I_D = I_S \left( e^{V_D/(nV_T)} - 1 \right)$$

• $$\displaystyle I_S $$ (Reverse Saturation Current): $$\displaystyle I_S \propto Area \cdot T^3 e^{-E_g/kT} $$. Determines leakage.

• $n$ (Ideality Factor): 1 (diffusion current), 2 (recombination in depletion region). Indicates quality of junction.

• Applications: Modeling pn junctions in BJTs, diodes, parasitic diodes in ICs.

D. Passive Component Models in ICs

III. DESIGN RULES & LAYOUT

A. Design Rules

• λ-based Rules: All dimensions expressed as multiples of λ (half the minimum feature size). Ensures scalability and mask correctness.

• Types:

  • Width Rules: Minimum wire/poly/diffusion width.

  • Spacing Rules: Minimum gap between same/different layers (to prevent shorts, crosstalk).

  • Overlap Rules: Minimum overlap of one layer on another (e.g., poly over active to ensure gate contact).

  • Extension Rules: Minimum extension of diffusion beyond poly (for source/drain).

• Importance: Ensure manufacturability, yield, and device functionality. Violations cause opens, shorts, or weak devices.

B. Interconnects

• Role: Provide electrical connection between devices. Dominates RC delay in deep sub-micron.

• RC Delay Considerations:

  • Resistance ($R$): Increases as width decreases ($R \propto 1/W$). Cu reduces R vs. Al.

  • Capacitance ($C$): Fringe capacitance becomes dominant as spacing decreases and thickness increases.

  • Delay: $\tau \propto R \cdot C$. Solution: Use thicker/wider lower-level metals for global wires, repeaters/buffers for long lines.

  • Skin Effect: At high frequencies, current crowds to surface, increasing effective R.

IV. CIRCUIT SIMULATION (SPICE)

A. Need & Significance

• Need: Verify circuit functionality and performance before costly fabrication.

• Significance:

  • Predict DC, AC, transient behavior.

  • Extract performance metrics (gain, bandwidth, power, noise).

  • Debug design errors.

  • Generate models for higher-level system simulation.

  • Perform worst-case analysis (process corners, temperature).

B. SPICE Analysis Types

1. DC Analysis: Solves for node voltages for a given bias. Used for operating point, transfer curves ($$\displaystyle V_{out} $$ vs $$\displaystyle V_{in} $$), DC transfer.

2. AC Analysis: Small-signal linearized analysis around a DC operating point. Gives frequency response (gain, phase, $$\displaystyle f_T $$, $$\displaystyle f_{max} $$).

3. Transient Analysis: Solves nonlinear differential equations in time. Time-domain response to pulses, clocks, arbitrary inputs.

4. Noise Analysis: Computes output-referred noise from device thermal/flicker noise sources.

C. Device Model Implementation in SPICE

• MOSFET Noise: Modeled as:

  • Thermal (Channel) Noise: $$\displaystyle i_n^2 = \frac{8}{3} kT \gamma g_m $$ (γ=1 for long-channel, >1 for short-channel).

  • Flicker (1/f) Noise: $$\displaystyle i_n^2 = \frac{K}{C_{ox} W L} \cdot \frac{1}{f} $$ (K: process constant).

• Diode/Bipolar Models: Use Ebers-Moll or Gummel-Poon models. Include junction capacitances ($$\displaystyle C_{je}, C_{jc} $$) and base resistance ($$\displaystyle r_b $$) for high-frequency.

D. Simulation Flowchart

[Circuit Netlist] → [Parse & Load Models] → [DC Operating Point] → [AC/Transient/Noise Analysis] → [Plot/Print Results]

!TIP: Always check convergence. Use UIC (use initial conditions) for transient, adjust RELTOL, ABSTOL, add Gmin/Rshunt if needed.

V. DIGITAL SYSTEM DESIGN ARCHITECTURES

A. Logic Design Styles

B. Register Storage Circuits

Function: Store 1-bit (or n-bit) state synchronously to a clock. 1. Static Register (Latch/Flip-Flop):

• Principle: Uses cross-coupled inverters (bistable) to hold state as long as power is on.

• Master-Slave Flip-Flop: Two latches (master, slave) clocked 180° out of phase. Solves race-around condition.

• Timing Parameters:

  • Setup Time ($$\displaystyle t_{su} $$): Minimum time data must be stable before clock edge.

  • Hold Time ($$\displaystyle t_h $$): Minimum time data must be stable after clock edge.

  • Propagation Delay ($$\displaystyle t_{pd} $$): Time from clock edge to output change.

  • Clock-to-Q Delay ($$\displaystyle t_{CQ} $$): Specific $$\displaystyle t_{pd} $$ for FF.

$$t_{cycle} > t_{CQ} + t_{su} + t_{logic} + t_{skew}$$

2. Dynamic Register:

• Stores charge on a capacitor (gate of an inverter). Requires periodic refresh (two-phase non-overlapping clocks). Faster, smaller but leakage-sensitive.

• Types: 2-phase, 1-phase (precharge/evaluate).

3. Quasi-Static Register:

• Hybrid. Uses dynamic node but with static feedback (e.g., a weak keeper transistor) to prevent complete discharge. Faster than static, more robust than dynamic.

C. Microcoded Controllers

• Architecture: Control memory (ROM/RAM) stores microinstructions. Microprogram Counter (µPC) sequences microinstructions. Microinstruction fields generate control signals directly or via decoders.

• Operation:

  1. Fetch microinstruction from control store (address from µPC).

  2. Decode fields to generate datapath control signals (ALU op, register enables, bus selects).

  3. Execute one micro-operation.

  4. Update µPC (next address logic: sequential, branch, jump based on condition codes).

• Advantage: Flexible, easy to modify/expand (change microcode). Disadvantage: Slower than hardwired (extra memory access).

D. Systolic Arrays

• Concept: Regular 2D array of identical processing elements (PEs). Data flows synchronously through the array in a wavefront pattern (like heart pumping blood - hence "systolic").

• Design: Each PE performs a simple, fixed operation (e.g., multiply-accumulate). Local interconnects only (nearest neighbor).

• Advantages: Massive parallelism, regular interconnect (short wires), high throughput, pipelined.

• Implementation Challenges:

  • I/O Bandwidth: Must feed data at peak rate.

  • Synchronization: Global clock distribution over large array.

  • Mapping Algorithm: Must fit regular systolic flow (e.g., matrix multiplication, convolution).

  • Utilization: Not all PEs active for all problems/input sizes.

E. Specialized Architectures: Algotronix

• Structure: A systolic array designed specifically for solving dense linear systems (Ax=b) and matrix operations.

• Functionality:

  • Array of identical PEs arranged in a triangular mesh.

  • Each PE contains a multiplier-accumulator (MAC) and local memory.

  • Matrix A is loaded into PEs. Vector x is pumped in from top/left. Result vector y emerges from bottom/right.

  • Implements Gaussian elimination and back-substitution in a pipelined, systolic manner.

• Significance: Demonstrated extremely high performance for linear algebra (100+ GFLOPS in 1980s) due to perfect data locality and concurrency. A landmark in algorithm-specific VLSI architecture.

VI. PACKAGING & TESTING

A. Importance

• Packaging: Protects die from environment, provides thermal path, electrical interface (I/O pins), mechanical support.

• Testing: Ensures only functional, reliable parts are shipped. Major cost factor (test time = $). Identifies faults from fabrication, design, or handling.

B. Packaging Steps & Technologies

1. Die Separation: Sawing/breaking wafer into individual dies.

2. Die Attach: Mounting die on package paddle (epoxy, eutectic solder).

3. Wire Bonding: Connecting die pads to package leads with Au/Al wires (ultrasonic/thermocompression).

4. Encapsulation: Sealing in plastic (epoxy mold compound) or ceramic.

5. Marking, Trimming, Testing.

• Technologies: DIP, PLCC, QFP, BGA, CSP, 3D IC (TSV). Trend: Smaller footprint, more I/Os, better electrical performance (BGA/CSP).

C. Testing Steps in IC Production

1. Wafer Probing (CP - Circuit Probing): Test dies on-wafer before dicing. Identifies gross failures.

2. Burn-in: (See below).

3. Final Test (FT): Test packaged parts under temperature/voltage extremes.

4. System-Level Test: Test in final application environment.

D. Burn-in Test

• Role: Accelerated life test to screen out infant mortality failures (weak devices that fail early).

• Method: Operate parts at elevated temperature (125°C) and high voltage for extended time (48-168 hrs).

• Mechanism: Accelerates failure mechanisms like electromigration, dielectric breakdown, mobile ion contamination.

• Outcome: Weak parts fail during burn-in; survivors have high reliability in field.

VII. SCALING & PERFORMANCE

A. Scaling in VLSI Design (Dennard Scaling)

• Constant Field Scaling (Ideal): All dimensions (L, W, tox, junction depth) scaled by factor S (<1). Voltages and doping scaled by 1/S.

• Result: Electric fields constant. Delay scales as S, power density constant, frequency increases by 1/S, power/chip constant.

• Reality (Beyond 0.25µm): Non-ideal scaling:

  • Constant Voltage Scaling: $$\displaystyle V_{DD} $$ doesn't scale (due to I/O compatibility, noise margin). Power density increases.

  • Limited Scaling: $L$ scales, but $$\displaystyle V_{DD} $$ and $tox$ scale slower. Leads to short-channel effects, high leakage, reliability issues.

B. Effects of Scaling

!TIP: Modern scaling is a trade-off between performance, power, area, and cost (PPAC). Solutions: High-κ/metal-gate (HKMG), FinFETs/FD-SOI, 3D integration, near-threshold computing.

BOXED KEY FORMULAS & CONCEPTS

• MOSFET Saturation Current (Level 1): $$\displaystyle \boxed{I_{D(sat)} = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS}-V_{th})^2 (1 + \lambda V_{DS})} $$

• Body Effect: $$\displaystyle \boxed{V_{th} = V_{th0} + \gamma \left( \sqrt{|2\phi_F + V_{SB}|} - \sqrt{|2\phi_F|} \right)} $$

• Subthreshold Slope: $$\displaystyle \boxed{S = \ln(10) \cdot n \cdot V_T \ \text{(mV/dec)}} $$, ideal S = 60mV/dec at 300K.

• Ebers-Moll (Forward Active): $$\displaystyle \boxed{I_C = \alpha_F I_{ES} (e^{V_{BE}/V_T}-1) \approx I_S e^{V_{BE}/V_T}} $$

• Shockley Diode: $$\displaystyle \boxed{I_D = I_S (e^{V_D/(nV_T)} - 1)} $$

• Setup/Hold Constraint: $$\displaystyle \boxed{t_{cycle} > t_{CQ} + t_{su} + t_{logic} + t_{skew}} $$

• Latch-up Parasitic Structure: pnpn thyristor formed by nMOS source/n-well/p-substrate/pMOS source.

• Twin-Tub Advantage: Reduced latch-up, better isolation, independent optimization.

PAST PAPER FREQUENCY INDICATORS (High → Low):

1. MOSFET Models (Level 1/2, Short-Channel) - Very High

2. Latch-up (Origin, Prevention) - Very High

3. Twin-Tub Process - Very High

4. Algotronix Architecture - Very High

5. Register Cells (Static, Dynamic, Quasi-Static, Timing) - Very High

6. Microcoded Controllers - High

7. Systolic Arrays - High

8. Photolithography/Oxidation/Metallization - High

9. Design Rules (λ-based) - High

10. SPICE (Analyses, Noise) - High

11. Passive Component Models - Medium

12. Packaging & Testing (Burn-in) - Medium

13. Scaling Effects - Medium

14. BJT Models (Ebers-Moll) - Medium

15. Diode Models - Medium

16. Hybrid/BiCMOS - Medium

17. Interconnects (RC) - Medium

18. Body Effect/Subthreshold - Medium (appears in derivations)