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EC-701 · VLSI Design/Important Questions

VLSI Design (EC-701) - Important Questions

  1. 14 Marks Medium Priority Asked: 2025

    Write a short note on any two

    Appeared 1x (2025)

  2. 7 Marks Medium Priority Asked: 2025

    Explain the complete IC fabrication sequence from wafer preparation through to final testing, emphasizing cleanliness and process control.

    Appeared 1x (2025)

  3. 7 Marks Medium Priority Asked: 2025

    Draw and explain the cross-sectional views of a MOS transistor at various stages of fabrication.

    Appeared 1x (2025)

  4. 7 Marks Medium Priority Asked: 2025

    Explain the photolithography process and its importance in IC manufacturing.

    Appeared 1x (2025)

  5. 7 Marks Medium Priority Asked: 2025

    Explain $\lambda$-based design rules and their importance for reliable fabrication.

    Appeared 1x (2025)

  6. 7 Marks Medium Priority Asked: 2025

    Discuss the importance of IC testing in VLSI manufacturing and explain the burn-in test and its role in reliability assessment.

    Appeared 1x (2025)

  7. 7 Marks Medium Priority Asked: 2024

    Discuss the importance of packaging and testing in ensuring the reliability of integrated circuits.

    Appeared 1x (2024)

  8. 7 Marks Medium Priority Asked: 2024

    Define oxidation, lithography, and metallization.

    Appeared 1x (2024)

  9. 7 Marks Medium Priority Asked: 2024

    Calculate the total area occupied by an NMOS process compared to a CMOS process. How does the choice of technology (NMOS, CMOS, Bipolar, Hybrid) affect the design and performance of integrated circuits?

    Appeared 1x (2024)

  10. 7 Marks Low Priority Asked: 2023

    What are the different technologies used in VLSI design? Explain briefly.

    Appeared 1x (2023)

  11. 7 Marks Low Priority Asked: 2023

    "Microelectronics Field plays a vital role in VLSI designing" Prove this statement with the help of a practical example.

    Appeared 1x (2023)

  12. 7 Marks Low Priority Asked: 2023

    Explain the packaging and testing stages of IC production in detail.

    Appeared 1x (2023)

  13. 7 Marks High Priority Asked: 2025

    Explain passive component models and discuss the modeling of resistors, capacitors and inductors in integrated circuits.

    Appeared 2x (2025)

  14. 7 Marks Medium Priority Asked: 2025

    DC model of MOSFET, derivation of drain current equations for different regions of operation and ID-VDS characteristics

    Appeared 1x (2025)

  15. 7 Marks Medium Priority Asked: 2025

    Explain DC models for semiconductor devices. Derive the DC current-voltage (I-V) characteristics for a MOSFET in different regions of operation.

    Appeared 1x (2025)

  16. 7 Marks Medium Priority Asked: 2025

    Explain the Ebers-Moll model of a BJT. Derive the equations for emitter and collector currents.

    Appeared 1x (2025)

  17. 7 Marks Medium Priority Asked: 2025

    Body effect in MOSFETs and its impact on threshold voltage

    Appeared 1x (2025)

  18. 7 Marks Medium Priority Asked: 2024

    Analyze the significance of small signal models in predicting the behavior of MOSFETs at high frequencies. Provide examples of applications where these models are crucial.

    Appeared 1x (2024)

  19. 7 Marks Medium Priority Asked: 2024

    Explain short channel devices, including their applications, advantages and limitations.

    Appeared 1x (2024)

  20. 7 Marks Medium Priority Asked: 2024

    How diode and bipolar models are utilized in predicting the behavior of passive components in circuits? Explain.

    Appeared 1x (2024)

  21. 7 Marks Low Priority Asked: 2023

    Classification of MOSFET models with explanation of one model

    Appeared 1x (2023)

  22. 7 Marks Low Priority Asked: 2023

    Derive a relation for the Sub threshold operations. How we can implement this operation on short channel devices?

    Appeared 1x (2023)

  23. 7 Marks Low Priority Asked: 2023

    Derive necessary expressions for short channel devices and illustrate the results with a suitable example.

    Appeared 1x (2023)

  24. 7 Marks Medium Priority Asked: 2025

    What is circuit simulation? Explain the need and significance of circuit simulation in VLSI design.

    Appeared 1x (2025)

  25. 7 Marks Medium Priority Asked: 2025

    Discuss the different types of analyses performed in SPICE (DC, AC, transient, noise, etc.).

    Appeared 1x (2025)

  26. 7 Marks Medium Priority Asked: 2025

    Derive the expression for large signal diode current based on the Shockley diode equation. Explain the significance of reverse saturation current and ideality factor.

    Appeared 1x (2025)

  27. 7 Marks Medium Priority Asked: 2025

    Discuss the impact of base resistance and capacitance on BJT high-frequency behavior.

    Appeared 1x (2025)

  28. 7 Marks Medium Priority Asked: 2025

    Explain the Level 2 MOSFET model and how it improves upon the Level 1 model.

    Appeared 1x (2025)

  29. 7 Marks Medium Priority Asked: 2025

    How is noise modeled in SPICE simulations for MOSFETs? Explain.

    Appeared 1x (2025)

  30. 7 Marks Medium Priority Asked: 2024

    Explain the procedure for simulation of a circuit using SPICE with a suitable flowchart.

    Appeared 1x (2024)

  31. 7 Marks Medium Priority Asked: 2024

    Discuss the impact of temperature dependence on BJT performance in circuit simulations and how to mitigate temperature effects in practical designs.

    Appeared 1x (2024)

  32. 7 Marks Low Priority Asked: 2023

    Derive the relation for temperature dependence of the BJT.

    Appeared 1x (2023)

  33. 10 Marks High Priority Asked: 2025, 2024

    Explain Algotronix architecture, including its structure, functionality and significance in high-performance VLSI systems.

    Appeared 2x (2025, 2024)

  34. 7 Marks High Priority Asked: 2025, 2024

    Explain the operation and architecture of microcoded controllers in structured digital circuits.

    Appeared 2x (2025, 2024)

  35. 7 Marks High Priority Asked: 2025, 2023

    Explain the principle of quasi-static register cells, how they differ from static and dynamic registers, with a practical VLSI case study.

    Appeared 2x (2025, 2023)

  36. 7 Marks High Priority Asked: 2024, 2023, 2020

    Explain the principle and procedure of microprocessor design methods using structured logic, including a practical application and advantages in efficiency and scalability.

    Appeared 3x (2024, 2023, 2020)

  37. 7 Marks Medium Priority Asked: 2025

    Explain the design and working of register storage circuits and derive timing parameters such as setup time, hold time and propagation delay.

    Appeared 1x (2025)

  38. 7 Marks Medium Priority Asked: 2025

    Define random logic and structured logic. Explain the advantages and disadvantages of structured logic over random logic.

    Appeared 1x (2025)

  39. 7 Marks Medium Priority Asked: 2025

    What is a systolic array and what are the challenges in implementing systolic array architectures?

    Appeared 1x (2025)

  40. 7 Marks Medium Priority Asked: 2024

    Compare the storage capabilities of quasi-static and static register cells and explain their contribution to register storage circuits.

    Appeared 1x (2024)

  41. 7 Marks Medium Priority Asked: 2024

    Design a systolic array for parallel processing and discuss its advantages.

    Appeared 1x (2024)

  42. 7 Marks Low Priority Asked: 2023

    Write any five differences between Random Logic and Structured Logic.

    Appeared 1x (2023)

  43. 7 Marks Low Priority Asked: 2023

    What do you mean by Astatic register cell? Explain the multiplication process and general linear system solver mechanism.

    Appeared 1x (2023)

  44. 7 Marks High Priority Asked: 2025, 2024

    Explain / design the step-by-step fabrication of the basic n-well CMOS process, including enhancement techniques

    Appeared 2x (2025, 2024)

  45. 7 Marks Medium Priority Asked: 2025, 2020

    Explain what layout design rules are in CMOS design, their types, and why they are essential, with suitable examples.

    Appeared 2x (2025, 2020)

  46. 7 Marks Medium Priority Asked: 2025

    Twin-tub CMOS process, its fabrication steps and advantages over n-well and p-well processes.

    Appeared 1x (2025)

  47. 7 Marks Medium Priority Asked: 2025

    Describe the conditions and mechanisms that trigger latch-up in CMOS circuits, including the role of substrate resistance, injection current and power supply transients.

    Appeared 1x (2025)

  48. 7 Marks Medium Priority Asked: 2024

    Investigate the physical origin of latch-up in CMOS circuits and propose internal latch-up prevention techniques to mitigate this issue effectively.

    Appeared 1x (2024)

  49. 14 Marks Low Priority Asked: 2023

    Write short notes:

    Appeared 1x (2023)

  50. 7 Marks Low Priority Asked: 2023

    Explain the principle of the basic n-well CMOS process and discuss the twin-tub process and its fabrication disadvantages

    Appeared 1x (2023)

  51. 7 Marks Low Priority Asked: 2023

    Analyze the effects of latch-up triggering in chip fabrication and explain methods to resolve latch-up problems.

    Appeared 1x (2023)

  52. 14 Marks Medium Priority Asked: 2025

    Write short notes on any two:

    Appeared 1x (2025)

  53. 7 Marks Medium Priority Asked: 2025

    Define scaling in VLSI design. Explain its effects on power, speed and performance.

    Appeared 1x (2025)

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