Electronic Devices (EC-304) - Unit 4 Short Notes

UNIT 4: ELECTRONIC DEVICES

I. SEMICONDUCTOR FUNDAMENTALS

Intrinsic Semiconductor:

• Pure semiconductor (Si, Ge) with no impurities.

• Equal number of free electrons ($n$) and holes ($p$): $$\displaystyle n = p = n_i $$.

• $$\displaystyle n_i $$ = intrinsic carrier concentration. Strongly temperature-dependent.

• Conductivity: $$\displaystyle \sigma = q (n_i \mu_n + p \mu_p) = q n_i (\mu_n + \mu_p) $$.

Extrinsic Semiconductor:

• Doped with impurities to control conductivity.

• n-type: Donor atoms (Group V, e.g., P, As) provide free electrons. Majority carriers = electrons. $$\displaystyle n \approx N_D $$, $$\displaystyle p = n_i^2 / n $$.

• p-type: Acceptor atoms (Group III, e.g., B, Al) provide holes. Majority carriers = holes. $$\displaystyle p \approx N_A $$, $$\displaystyle n = n_i^2 / p $$.

• Mass Action Law: $$\displaystyle np = n_i^2 $$ (holds at equilibrium).

Energy Band Structure:

Elemental vs. Compound Semiconductors:

• Elemental: Si, Ge (single element).

• Compound: III-V (GaAs, GaN), II-VI (CdS, ZnSe). Used in high-frequency, optoelectronic apps.

[!TIP] Exam Focus: Carrier concentration calculations ($$\displaystyle n_i $$, $n$, $p$) from conductivity and mobility are frequent. Always use SI units: $\sigma$ in $$\displaystyle (\Omega \cdot m)^{-1} $$, $\mu$ in $$\displaystyle m^2/V \cdot s $$, $$\displaystyle q=1.6\times10^{-19} $$ C.

II. PN JUNCTION DIODE

Construction & Working:

• Formed by joining p-type and n-type semiconductors.

• Depletion Region: Immobile ions create a potential barrier ($$\displaystyle V_{bi} $$).

• Forward Bias: Reduces barrier, current flows easily.

• Reverse Bias: Increases barrier, only small reverse saturation current ($$\displaystyle I_0 $$) flows.

V-I Characteristics & Shockley Equation:

$$I = I_0 \left( e^{\frac{qV}{nkT}} - 1 \right)$$

• $$\displaystyle I_0 $$: Reverse saturation current.

• $n$: Emission coefficient (1-2).

• $kT/q \approx 26$ mV at 300K.

• Ideal Diode: $$\displaystyle n=1 $$, $$\displaystyle I_0 $$ negligible.

Breakdown Mechanisms:

• Zener Breakdown ($$\displaystyle V_Z < 5V $$): High electric field in narrow depletion region causes electron tunneling. Sharp breakdown, negative temp. coefficient.

• Avalanche Breakdown ($$\displaystyle V_Z > 7V $$): Carrier collision generates electron-hole pairs (avalanche). Gradual breakdown, positive temp. coefficient.

Transition (Depletion) Capacitance ($$\displaystyle C_T $$):

$$C_T = \frac{\epsilon A}{W}$$

• $$\displaystyle W \propto \sqrt{V_{bi} - V} $$ (reverse bias increases $W$, decreases $$\displaystyle C_T $$).

• Varactor diode exploits this voltage-controlled capacitance.

Diffusion Capacitance ($$\displaystyle C_D $$):

• Exists under forward bias.

• $$\displaystyle C_D \propto I_F $$ (forward current). Related to charge storage.

Temperature Effects:

• $$\displaystyle I_0 $$ doubles for every $$\displaystyle 10^\circ C $$ rise.

• $$\displaystyle V_{bi} $$ decreases by ~2 mV/$$\displaystyle ^\circ C $$.

• Forward voltage drop ($$\displaystyle V_F $$) decreases with temperature.

Ideal vs. Practical Diode:

III. SPECIAL PURPOSE DIODES

Zener Diode:

• Operation: Reverse breakdown region (Zener or avalanche).

• V-I Char: Sharp breakdown at $$\displaystyle V_Z $$. $$\displaystyle V_Z $$ stable over current range.

• Temp. Coefficient: Negative ($$\displaystyle V_Z<5V $$), Positive ($$\displaystyle V_Z>7V $$), Zero (~5-6V).

• Apps: Voltage regulator, reference, waveform clipping.

Tunnel Diode:

• Construction: Heavily doped p-n, very narrow depletion region.

• V-I Char: Negative resistance region due to tunneling.

• Tunneling Conditions: Heavy doping, narrow barrier, low forward voltage.

• Apps: High-speed switching, oscillators, amplifiers.

Schottky Diode:

• Construction: Metal (e.g., Al, Au) - n-type semiconductor junction.

• Char: Low forward voltage ($$\displaystyle V_F \approx 0.2-0.4V $$), fast switching (no minority carrier storage), higher reverse leakage.

• Apps: High-frequency rectifiers, clamping, RF circuits.

Varactor Diode:

• Operation: Reverse-biased p-n junction. $$\displaystyle C_T \propto (V_{bi} - V_R)^{-m} $$.

• Apps: Voltage-controlled capacitor in VCOs, TV tuners, parametric amplifiers.

Photo Diode & LED:

• Photo Diode (Photoconductive): Reverse biased. Light generates E-H pairs → increases reverse current ($$\displaystyle I_{ph} $$). Apps: detectors, optical switches.

• LED (Photoemissive): Forward biased. Electron-hole recombination emits light (direct bandgap materials like GaAsP). Apps: displays, indicators.

Solar Cell (Photovoltaic):

• Construction: Large-area p-n junction, no bias.

• Principle: Light absorption generates EMF. Open-circuit voltage $$\displaystyle V_{oc} $$, short-circuit current $$\displaystyle I_{sc} $$.

• Symbol:

  DiagramSEARCH: solar cell symbol and construction diagram

IV. DIODE CIRCUITS

Clippers:

• Function: Remove part of input waveform (clamp voltage level).

• Types: Series, Shunt, Positive/Negative biased, Combination.

• Example (Series Positive Clipper): Diode in series with load, anode to positive. Clips positive half above $$\displaystyle V_D $$.

  DiagramCANVAS: Series positive clipper circuit with input/output waveforms

Clampers:

• Function: Shift entire waveform up/down by a DC level.

• Types: Positive clamper (shifts negative), Negative clamper (shifts positive), Biased.

• Operation: Capacitor charges to peak input during negative half, acts as battery during positive half.

  DiagramCANVAS: Positive clamper circuit showing capacitor charging and output shift

Rectifiers: 1. Half-Wave Rectifier (HWR):

• Circuit: Single diode, center-tapped or without (using capacitor filter).

• Output: $$\displaystyle V_{DC} = \frac{V_m}{\pi} $$, $$\displaystyle I_{DC} = \frac{I_m}{\pi} $$.

• Ripple Factor: $$\displaystyle \gamma = 1.21 $$ (no filter).

• Efficiency: $$\displaystyle \eta = \frac{P_{DC}}{P_{AC}} = 40.6\% $$.

• PIV = $$\displaystyle V_m $$ (no CT) or $$\displaystyle 2V_m $$ (with CT).

• TUF (Transformer Utilization Factor) = 0.287.

2. Full-Wave Rectifier (FWR) - Center-Tapped:

• Circuit: Two diodes, center-tapped transformer.

• Output: $$\displaystyle V_{DC} = \frac{2V_m}{\pi} $$, $$\displaystyle I_{DC} = \frac{2I_m}{\pi} $$.

• Ripple Factor: $$\displaystyle \gamma = 0.48 $$ (no filter).

• Efficiency: $$\displaystyle \eta = 81.2\% $$.

• PIV = $$\displaystyle 2V_m $$.

• TUF = 0.573.

3. Bridge Rectifier:

• Circuit: Four diodes in bridge configuration.

• Output: Same as CT-FWR ($$\displaystyle V_{DC} = 2V_m/\pi $$).

• PIV = $$\displaystyle V_m $$.

• No center tap needed, TUF = 0.812 (highest).

Filter Circuits:

• Capacitor Filter (C-filter): Capacitor across load. Charges to peak, discharges through load. $$\displaystyle \gamma \approx \frac{1}{2\sqrt{3} f C R_L} $$ (HWR), $$\displaystyle \frac{1}{4\sqrt{3} f C R_L} $$ (FWR).

• L-Section Filter (L-input): Inductor in series, capacitor shunt. Better regulation.

• π-Filter: C-L-C. Very low ripple.

Transformer Rating for Rectifiers:

To deliver $$\displaystyle P_{DC} $$ watts:

• HWR: $$\displaystyle P_{AC} = \frac{P_{DC}}{\eta} = \frac{P_{DC}}{0.406} $$. $$\displaystyle V_{rms} = \frac{V_m}{\sqrt{2}} $$, $$\displaystyle I_{rms} = \frac{I_m}{2} $$.

• FWR/Bridge: $$\displaystyle P_{AC} = \frac{P_{DC}}{0.812} $$. $$\displaystyle V_{rms} = \frac{V_m}{\sqrt{2}} $$, $$\displaystyle I_{rms} = \frac{I_m}{\sqrt{2}} $$ (bridge).

[!TIP] Exam Focus: Transformer rating problems are common. Remember: $$\displaystyle P_{AC} = V_{rms} \cdot I_{rms} $$ (per winding). For CT-FWR, each half winding supplies current only during its half-cycle, so $$\displaystyle I_{rms} $$ per half = $$\displaystyle I_m/2 $$.

V. BIPOLAR JUNCTION TRANSISTOR (BJT)

Construction & Operation:

• NPN: n-emitter, p-base, n-collector. Conventional current: $$\displaystyle I_E = I_B + I_C $$.

• Operation: Emitter-base forward biased, collector-base reverse biased. Injector (E), Controller (B), Collector (C).

Current Equations:

• $$\displaystyle \alpha = \frac{I_C}{I_E} $$ (0.95-0.99), $$\displaystyle \beta = \frac{I_C}{I_B} $$ (20-500), $$\displaystyle \gamma = \frac{I_E}{I_B} = \beta + 1 $$.

• Relationship: $$\displaystyle \beta = \frac{\alpha}{1-\alpha} $$, $$\displaystyle \alpha = \frac{\beta}{\beta + 1} $$.

Configurations & Characteristics:

Biasing & Stabilization:

• Need: Set stable Q-point (operating point) away from saturation/cut-off despite temperature variations.

• Techniques:

  1. Fixed Bias: Simple, poor stability ($$\displaystyle S = 1+\beta $$).

  2. Collector-to-Base Bias: Slightly better ($S \approx 1+\beta$ still).

  3. Self-Bias (Voltage-Divider): Best stability. $$\displaystyle S \approx 1 + \frac{\beta}{1+\frac{R_E}{R_{th}}} $$.

  4. Emitter Bias: Excellent stability (uses $$\displaystyle V_{EE} $$).

• Stability Factor (S): $$\displaystyle S = \frac{dI_{C2}/I_{C1}}{dI_{CBO}/I_{C1}} $$ (for $$\displaystyle I_{CBO} $$ variation). Lower $S$ = better stability.

• $S'$: For $\beta$ variation. $$\displaystyle S' \approx 1 + \frac{\beta}{1+\frac{R_E}{R_{th}}} $$ (similar to S).

• Thermal Runaway: Increase in $$\displaystyle I_C $$ → power dissipation ↑ → temperature ↑ → $$\displaystyle I_C $$ ↑ further. Prevention: Use emitter resistor $$\displaystyle R_E $$, heat sinking, stable bias.

DC & AC Analysis:

• DC Load Line: $$\displaystyle V_{CE} = V_{CC} - I_C R_C $$ (CE). Q-point = intersection of load line and bias line.

• AC Load Line: $$\displaystyle v_{ce} = -i_c r_C $$, where $$\displaystyle r_C = R_C || R_L $$. Slope steeper than DC line.

• Transistor as Switch:

  • Saturation: $$\displaystyle I_C $$ max, $$\displaystyle V_{CE} \approx 0.2V $$. Diode ON.

  • Cut-off: $$\displaystyle I_C=0 $$, $$\displaystyle V_{CE}=V_{CC} $$. Diode OFF.

Small-Signal h-Parameters (CE):

• $$\displaystyle h_{ie} = \left. \frac{\Delta V_{BE}}{\Delta I_B} \right|_{V_{CE}=const} $$ (input impedance).

• $$\displaystyle h_{re} = \left. \frac{\Delta V_{BE}}{\Delta V_{CE}} \right|_{I_B=const} $$ (reverse voltage ratio, small).

• $$\displaystyle h_{fe} = \left. \frac{\Delta I_C}{\Delta I_B} \right|_{V_{CE}=const} $$ (current gain, $\beta$).

• $$\displaystyle h_{oe} = \left. \frac{\Delta I_C}{\Delta V_{CE}} \right|_{I_B=const} $$ (output admittance, $$\displaystyle =1/r_o $$).

• CE Amplifier Analysis:

$$A_v = \frac{v_o}{v_i} = - \frac{h_{fe} R_L'}{h_{ie} + (\Delta h_{fe} R_L')} \approx -\frac{h_{fe} R_L'}{h_{ie}}$$

where $$\displaystyle R_L' = R_C || R_L $$.

$$\displaystyle R_i = h_{ie} $$, $$\displaystyle R_o = r_o $$ (if considered) or high.

Ebers-Moll Model:

• Two diode models with current-controlled current sources.

• Equations:

$$I_E = I_{ES} \left( e^{\frac{V_{BE}}{V_T}} - 1 \right) - \alpha_R I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right)$$

$$I_C = \alpha_F I_{ES} \left( e^{\frac{V_{BE}}{V_T}} - 1 \right) - I_{CS} \left( e^{\frac{V_{BC}}{V_T}} - 1 \right)$$

• Useful for computer analysis, includes charge storage.

VI. BJT AMPLIFIERS

Amplifier Classes:

Multistage Amplifiers:

• Need: Increase gain, bandwidth, impedance matching.

• Coupling Methods:

  • RC Coupling: Capacitor coupling. Good for voltage amps, blocks DC. Poor low-freq response.

  • Transformer Coupling: Impedance matching, no DC path. Good for power amps, poor freq response.

  • Direct Coupling: Resistor coupling. DC amplification, excellent low-freq, poor drift stability.

• Bootstrapping: Technique to increase input impedance. Feedback capacitor returns output to input in phase (e.g., in Darlington or CC stage).

Special Amplifier Circuits:

• Darlington Amplifier: Two transistors (CE-CC). $$\displaystyle \beta_{total} = \beta_1 \beta_2 $$. Very high $$\displaystyle R_i $$, high current gain. Used in buffers, drivers.

• Push-Pull Amplifier (Class B): Two transistors (NPN/PNP or complementary) conduct alternately. Eliminates even harmonics. Crossover distortion at zero-crossing. Solutions: bias slightly into AB class.

• Cascode Amplifier: CE stage followed by CB stage. High output impedance, high gain, good high-freq response (reduces Miller effect).

VII. FIELD EFFECT TRANSISTORS (FETs) & MOSFETs

JFET (Junction FET):

• Construction: n-channel (most common) or p-channel. Gate forms reverse-biased p-n junction.

• Operation: $$\displaystyle V_{GS} $$ controls width of depletion region → controls $$\displaystyle I_D $$.

• Pinch-off ($$\displaystyle V_P $$): $$\displaystyle V_{GS} $$ where channel closes, $$\displaystyle I_D \approx 0 $$ (saturation). $$\displaystyle V_P $$ is negative for n-JFET.

• Saturation (Constant Current) Region: $$\displaystyle I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2 $$ for $$\displaystyle V_{GS} \leq V_P $$ and $$\displaystyle V_{DS} \geq V_{GS} - V_P $$.

• Ohmic Region: $$\displaystyle V_{DS} $$ small, JFET acts as voltage-controlled resistor.

• Parameters:

  • $$\displaystyle I_{DSS} $$: Drain current with $$\displaystyle V_{GS}=0 $$ (in saturation).

  • $$\displaystyle V_P $$: Pinch-off voltage (negative for n-JFET).

  • $$\displaystyle g_m = \left. \frac{\Delta I_D}{\Delta V_{GS}} \right|_{V_{DS}=const} = \frac{2I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right) $$ (at $$\displaystyle V_{GS}=0 $$, $$\displaystyle g_{m0} = \frac{2I_{DSS}}{|V_P|} $$).

  • $$\displaystyle r_{ds} = \frac{1}{g_m} $$ (in saturation).

MOSFET (Metal-Oxide-Semiconductor FET):

• Construction: Gate insulated by $$\displaystyle SiO_2 $$ from channel. No DC gate current.

• Enhancement Mode: $$\displaystyle V_{GS}=0 \rightarrow I_D=0 $$. Apply $$\displaystyle V_{GS} > V_{th} $$ (n-enh) to create channel.

• Depletion Mode: Channel exists at $$\displaystyle V_{GS}=0 $$. $$\displaystyle V_{GS} $$ can deplete channel (negative for n-dep).

• Regions:

  • Triode/Linear: $$\displaystyle V_{DS} < V_{GS} - V_{th} $$. $$\displaystyle I_D \approx k' \frac{W}{L} \left[ (V_{GS}-V_{th})V_{DS} - \frac{V_{DS}^2}{2} \right] $$.

  • Saturation/Cut-off: $$\displaystyle V_{DS} \geq V_{GS} - V_{th} $$. $$\displaystyle I_D = \frac{1}{2} k' \frac{W}{L} (V_{GS}-V_{th})^2 $$ (ideal).

• Small-Signal Model: Hybrid-π model for MOSFET. $$\displaystyle g_m = \sqrt{2k' \frac{W}{L} I_D} $$ or $$\displaystyle g_m = \frac{2I_D}{V_{GS}-V_{th}} $$.

FET Biasing:

• Self-Bias (Voltage-Divider): Most common. $$\displaystyle V_{GS} = -\frac{R_2}{R_1+R_2} V_{DD} $$ (for n-JFET) or $$\displaystyle V_{GS} = \frac{R_2}{R_1+R_2} V_{DD} $$ (for n-enh MOSFET). $$\displaystyle I_D $$ set by $$\displaystyle V_{GS} $$ on transfer curve.

• DC Analysis: Find $$\displaystyle V_{GSQ} $$ from bias network, then $$\displaystyle I_{DQ} $$ from $$\displaystyle I_D $$-$$\displaystyle V_{GS} $$ equation, then $$\displaystyle V_{DSQ} = V_{DD} - I_D R_D $$.

FET Amplifier Configurations:

• Common Source (CS): Analog to CE. High voltage gain, phase inversion, high input impedance, medium output impedance. $$\displaystyle A_v = -g_m R_D' $$.

• Common Drain (CD) / Source Follower: Analog to CC. Voltage gain ≈ 1, no phase inversion, very high input impedance, low output impedance. $$\displaystyle A_v = \frac{g_m R_S}{1+g_m R_S} $$.

• Common Gate (CG): Analog to CB. Low input impedance, high output impedance, no phase inversion, voltage gain ≈ $$\displaystyle g_m R_D $$.

Current Mirror:

• Basic Circuit: Two matched transistors (BJT or MOSFET). $$\displaystyle I_{ref} $$ sets $$\displaystyle I_{out} $$.

• BJT Mirror: $$\displaystyle Q_1 $$ diode-connected ($$\displaystyle V_{BE} $$ sets $$\displaystyle I_{ref} $$). $$\displaystyle Q_2 $$ mirrors: $$\displaystyle I_{out} \approx I_{ref} $$ if $\beta$ large.

• Apps: Active loads, bias circuits in ICs. Provides stable current source.

VIII. OTHER SEMICONDUCTOR DEVICES & APPLICATIONS

Unijunction Transistor (UJT):

• Construction: n-type bar with p-type emitter. Three terminals: B1, B2 (n-bar), E (p-emitter).

• Char: $$\displaystyle I_E $$ vs $$\displaystyle V_E $$ shows negative resistance region after peak point.

• Relaxation Oscillator: RC circuit with UJT. Capacitor charges via $R$ until peak point ($$\displaystyle V_P $$), UJT fires, capacitor discharges rapidly through B1-E, repeats. Frequency $$\displaystyle f \approx \frac{1}{RC \ln \frac{1}{1-\eta}} $$, $$\displaystyle \eta = \frac{R_{B1}}{R_{B1}+R_{B2}} $$.

Thyristor (SCR):

• Construction: Four-layer p-n-p-n (3 junctions). Terminals: Anode (p), Cathode (n), Gate (p).

• Operation: Forward blocking ($$\displaystyle J_2 $$ reverse biased). Gate pulse triggers → latches ON. Turns OFF when $$\displaystyle I_A < I_H $$ (holding current).

• V-I Char: Forward blocking → forward conducting → reverse blocking.

• Apps: AC power control (dimmers, motor speed), rectifiers, inverters, overvoltage protection.

Photo Transistor:

• Construction: Similar to BJT, but base region exposed to light (or has window).

• Operation: Light generates E-H pairs in base → increases $$\displaystyle I_B $$ → increases $$\displaystyle I_C $$. $$\displaystyle I_C = \beta I_{B(light)} $$.

• Apps: Light sensors, opto-isolators, encoders.

IX. ADVANCED TOPICS & SHORT NOTES

Thermal Runaway in BJT:

• Cause: $$\displaystyle I_C $$ ↑ → $$\displaystyle P_{diss} = V_{CE}I_C $$ ↑ → $T$ ↑ → $$\displaystyle I_{CBO} $$ ↑ (doubles/10°C) → $$\displaystyle I_C $$ ↑ further.

• Prevention: Use voltage-divider bias with emitter resistor $$\displaystyle R_E $$ (provides negative feedback), adequate heat sinking, ensure $$\displaystyle V_{CE} $$ not too low in operating region.

Frequency Response of Amplifiers:

• Low Frequency: Coupling/ bypass capacitors cause roll-off ($$\displaystyle f_L $$ determined by $RC$ time constants).

• High Frequency: Internal capacitances ($$\displaystyle C_{be} $$, $$\displaystyle C_{bc} $$ Miller effect) cause roll-off ($$\displaystyle f_H $$). Miller Effect: $$\displaystyle C_{in} = C_{bc}(1+A_v) $$ in CE.

• Bandwidth: $$\displaystyle BW = f_H - f_L $$.

Comparison of Rectifier Topologies:

Key Calculation Problems:

1. Zener Temp. Coefficient:

$$\alpha_Z = \frac{\Delta V_Z}{\Delta T} = \frac{V_{Z2} - V_{Z1}}{T_2 - T_1}$$

Example: $$\displaystyle V_{Z1}=5V@25^\circ C $$, $$\displaystyle V_{Z2}=4.8V@100^\circ C $$ → $$\displaystyle \alpha_Z = \frac{4.8-5}{100-25} = -0.00267 V/^\circ C = -2.67 mV/^\circ C $$.

2. Carrier Concentration from Conductivity:

   For extrinsic (n-type): $$\displaystyle \sigma \approx q n \mu_n \Rightarrow n = \frac{\sigma}{q \mu_n} $$.

   Given $\sigma$, $$\displaystyle \mu_p $$, for p-type: $$\displaystyle p = \frac{\sigma}{q \mu_p} $$.

3. DC Bias Point (Voltage-Divider):

$$V_{BB} = \frac{R_2}{R_1+R_2} V_{CC}, \quad V_{BB} = V_{BE} + I_E R_E \approx V_{BE} + I_C R_E$$

$$I_C \approx \frac{V_{BB} - V_{BE}}{R_E} \quad (\text{if } \beta R_E >> R_{th})$$

$$V_{CE} = V_{CC} - I_C R_C - I_E R_E \approx V_{CC} - I_C (R_C + R_E)$$

4. h-Parameters from Curves:

   • $$\displaystyle h_{ie} $$: Slope of $$\displaystyle I_B $$-$$\displaystyle V_{BE} $$ curve at constant $$\displaystyle V_{CE} $$.

   • $$\displaystyle h_{fe} $$: Slope of $$\displaystyle I_C $$-$$\displaystyle I_B $$ curve at constant $$\displaystyle V_{CE} $$.

   • $$\displaystyle h_{oe} $$: Slope of $$\displaystyle I_C $$-$$\displaystyle V_{CE} $$ curve at constant $$\displaystyle I_B $$ ($$\displaystyle =1/r_o $$).

   • $$\displaystyle h_{re} $$: Slope of $$\displaystyle V_{BE} $$-$$\displaystyle V_{CE} $$ curve at constant $$\displaystyle I_B $$ (usually negligible).

5. JFET Parameter Calculation:

   Given $$\displaystyle I_{DSS} $$, $$\displaystyle V_P $$, find $$\displaystyle I_D $$ and $$\displaystyle g_m $$ at $$\displaystyle V_{GS} $$:

$$I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2$$

$$g_m = \frac{2I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right) = \frac{2I_D}{|V_P - V_{GS}|}$$

$$\displaystyle r_{ds} = 1/g_m $$.

6. Transformer & Filter Design:

   • Transformer $$\displaystyle V_{rms} $$: For bridge, $$\displaystyle V_{rms} = \frac{V_{DC} + \text{ripple}/2}{\text{regulation factor}} $$. Approx: $$\displaystyle V_{rms} \approx \frac{V_{DC}}{0.9} $$ for capacitor filter.

   • Capacitor Filter: $$\displaystyle C \approx \frac{I_{DC}}{f \gamma V_{DC}} $$ (for HWR: $f$=input freq; for FWR: $2f$).

   • L-Section Ripple: $$\displaystyle \gamma \approx \frac{R_L}{3\sqrt{2} \omega^2 L C} $$ (FWR).

7. CS Amplifier Gain (Hybrid-π):

$$A_v = \frac{v_o}{v_i} = -g_m (R_D || r_o || R_L) \cdot \frac{r_\pi}{r_\pi + R_G}$$

where $$\displaystyle R_G = R_1 || R_2 || R_{source} $$, $$\displaystyle g_m = \frac{I_D}{V_{GS}-V_{th}} $$ or $$\displaystyle \sqrt{2\mu_n C_{ox} \frac{W}{L} I_D} $$.

SHORT NOTES (From Past Papers)

Current Mirror Circuit:

• Purpose: Generate stable reference/ bias current independent of $$\displaystyle V_{DD} $$ and $\beta$.

• BJT Version: Two transistors ($$\displaystyle Q_1 $$, $$\displaystyle Q_2 $$) with $$\displaystyle Q_1 $$ diode-connected. $$\displaystyle I_{ref} $$ through $$\displaystyle Q_1 $$ sets $$\displaystyle V_{BE} $$. $$\displaystyle Q_2 $$ mirrors: $$\displaystyle I_{out} \approx I_{ref} $$ if $\beta$ large. Improved Wilson mirror adds $$\displaystyle Q_3 $$ for better matching.

• MOSFET Version: $$\displaystyle I_{out} = I_{ref} $$ if $W/L$ ratios equal.

• Apps: Active loads in differential amps, current sources in ICs.

Push-Pull Amplifier:

• Circuit: Two transistors (complementary NPN/PNP or matched) in push-pull configuration. Input split by transformer or phase splitter.

• Operation: Each transistor conducts for 180° (Class B). Reduces even harmonic distortion.

• Crossover Distortion: Non-linear region around $$\displaystyle V_{BE} $$ where both transistors OFF. Mitigated by slight forward bias (Class AB).

• Apps: Audio power amplifiers, output stages.

Schottky Diode:

• Construction: Metal (e.g., Pt, W) - n-semiconductor junction. No minority carrier storage.

• Characteristics: Very low forward voltage ($$\displaystyle V_F \approx 0.2-0.4V $$), fast switching (no reverse recovery), higher reverse leakage current than p-n diode.

• Apps: High-frequency rectifiers (RF, microwave), clamping circuits, digital logic (TTL), power supply protection.

Ebers-Moll Model:

• Concept: BJT represented as two p-n diodes with current-controlled current sources.

• Equations: (See Section V). Includes forward ($$\displaystyle \alpha_F $$) and reverse ($$\displaystyle \alpha_R $$) transport factors.

• Use: Computer-aided analysis, includes charge storage effects (via $$\displaystyle \alpha_F $$, $$\displaystyle \alpha_R $$). Basis for more complex models (Gummel-Poon).

MOSFET:

• Types: Enhancement (normally OFF), Depletion (normally ON). n-channel/p-channel.

• Key Feature: Voltage-controlled, virtually zero gate current ($$\displaystyle I_G \approx 0 $$).

• Operation: $$\displaystyle V_{GS} $$ controls channel conductivity. Threshold voltage $$\displaystyle V_{th} $$ key parameter.

• Regions: Cut-off ($$\displaystyle V_{GS}<V_{th} $$), Triode ($$\displaystyle V_{DS}<V_{GS}-V_{th} $$), Saturation ($$\displaystyle V_{DS} \geq V_{GS}-V_{th} $$).

• Apps: Digital logic (CMOS), analog switches, amplifiers, power devices (VMOS, LDMOS).

Darlington Amplifier:

• Circuit: Two BJTs in cascade (emitter of $$\displaystyle Q_1 $$ to base of $$\displaystyle Q_2 $$). Overall $$\displaystyle \beta_{total} \approx \beta_1 \beta_2 $$.

• Characteristics: Very high input impedance ($$\displaystyle R_i \approx \beta_1 \beta_2 r_{e2} $$), high current gain, higher $$\displaystyle V_{BE} $$ ($\approx 1.4V$), slower switching (due to $$\displaystyle C_{ob2} $$ feedback).

• Apps: Input buffers, current amplifiers, driver stages, high-impedance sensors.

Pinch-off Voltage ($$\displaystyle V_P $$):

• Definition (JFET): Gate-source voltage at which channel is completely pinched off and $$\displaystyle I_D \approx 0 $$. Negative for n-channel.

• Significance: Key parameter determining $$\displaystyle I_{DSS} $$ and $$\displaystyle g_m $$. $$\displaystyle I_D = I_{DSS} (1 - V_{GS}/V_P)^2 $$.

• Not to confuse with: MOSFET threshold voltage $$\displaystyle V_{th} $$ (enhancement) or $$\displaystyle V_{GS(off)} $$ (depletion).

Tunnel Diode:

• Construction: Heavily doped p-n junction (doping ~100x normal). Very narrow depletion region (~10 nm).

• V-I Characteristics: Peak ($$\displaystyle V_P $$, $$\displaystyle I_P $$), Valley ($$\displaystyle V_V $$, $$\displaystyle I_V $$), negative resistance region ($$\displaystyle I_P $$ to $$\displaystyle I_V $$).

• Tunneling: Quantum mechanical effect where carriers cross thin barrier without energy.

• Sufficient Conditions: Heavy doping, thin barrier, low forward voltage.

• Apps: High-speed oscillators (GHz), amplifiers, switching circuits.

Clipper and Clamper:

• Clipper: Removes part of signal above/below a reference level. Types: Series/Shunt, Positive/Negative biased. Apps: Waveform shaping, protection.

• Clamper: Shifts entire waveform by a DC level (adds DC component). Types: Positive/Negative clamper, biased clamper. Apps: DC restoration, level shifting.

Class A Amplifier:

• Operation: Transistor conducts for 360° of cycle. Q-point at center of load line.

• Characteristics: Low distortion (<1%), low efficiency (25% w/o transformer, 50% with), used in preamplifiers.

• Circuit: Common emitter with resistive load or transformer load. Requires heatsinking.

LED and Solar Cell:

• LED (Light Emitting Diode):

  • Construction: Direct bandgap semiconductor (GaAs, GaP).

  • Operation: Forward biased, electron-hole recombination emits light (electroluminescence). Color depends on bandgap.

  • Char: $$\displaystyle V_F $$ higher than Si diode (1.8-3.3V), low current (10-50mA).

• Solar Cell (Photovoltaic):

  • Construction: Large-area p-n junction, no bias.

  • Operation: Photons generate E-H pairs → built-in field separates carriers → generates voltage/current.

  • Char: $I$-$V$ curve in 4th quadrant. $$\displaystyle V_{oc} $$ (open-circuit voltage), $$\displaystyle I_{sc} $$ (short-circuit current). Fill factor, efficiency key.

Voltage Regulation using IC (78xx/79xx):

• Series 78xx: Fixed positive voltage regulator (7805 → +5V). 3-terminal: Input, GND, Output.

• Series 79xx: Fixed negative voltage regulator (7905 → -5V).

• Features: Internal current limiting, thermal shutdown. Requires input at least 2V above output, capacitors for stability.

• Apps: Regulated power supplies, microcontroller circuits.

Punch Through & Base Width Modulation (Early Effect):

• Base Width Modulation (Early Effect): In reverse-biased CB junction, increase $$\displaystyle V_{CB} $$ → depletion region widens → effective base width $$\displaystyle W_B $$ ↓ → $\alpha$ ↑ slightly → $$\displaystyle I_C $$ increases with $$\displaystyle V_{CE} $$ (output conductance). Explains output resistance $$\displaystyle r_o $$ in active region.

• Punch-through: Extreme case where depletion region from collector extends through entire base → base-collector junction conducts heavily → loss of transistor action. Occurs at high $$\displaystyle V_{CB} $$ in narrow-base transistors.

Low and High Frequency Response:

• Low Frequency: Dominated by coupling/ bypass capacitors. $$\displaystyle f_L $$ determined by largest $RC$ time constant (usually input coupling cap with $$\displaystyle R_i $$ or emitter bypass cap with $$\displaystyle R_E $$). Single high-pass pole.

• High Frequency: Dominated by internal capacitances ($$\displaystyle C_{be} $$, $$\displaystyle C_{bc} $$). Miller effect multiplies $$\displaystyle C_{bc} $$ in CE. $$\displaystyle f_H $$ determined by $$\displaystyle C_{in} $$ and $$\displaystyle C_{out} $$ poles. Multiple poles roll-off at -20dB/decade each.

• Bandwidth: $$\displaystyle BW = f_H - f_L $$. Gain-bandwidth product constant for single-stage.

[!TIP] Final Exam Strategy: For 7-mark questions, always start with definition/construction, then working principle, characteristics (with diagram if possible), and applications. For numerical problems, show formula, substitution, and boxed answer. For short notes (3-4 marks), be concise: 2-3 lines definition, key feature, one main application.