UNIT 3: Electronic Devices - High-Impact Study Notes (Based on RGPV Past Papers)

1.0 SEMICONDUCTOR FUNDAMENTALS

1.1 Energy Band Structure

• Key Concept: Energy bands (Valence Band, Conduction Band) separated by Forbidden Gap (E_g).

• Conductors: Valence & conduction bands overlap. No gap. Electrons free to move.

• Insulators: Large E_g (~>5 eV). Valence band full, conduction band empty.

• Semiconductors: Small E_g (~1 eV for Si, 0.67 eV for Ge). Valence band almost full, conduction band almost empty at T=0K.

• Equilibrium Condition: In an intrinsic semiconductor, number of thermally generated electrons (n) equals number of holes (p). n = p = n_i (intrinsic carrier concentration).

  Formula: $$\displaystyle n_i^2 = N_c N_v e^{-E_g/kT} $$ where $$\displaystyle N_c, N_v $$ are effective density of states.

1.2 Intrinsic & Extrinsic Semiconductors

• Intrinsic: Pure semiconductor (Si, Ge). n = p = n_i. Conductivity: $$\displaystyle \sigma = q(n_i\mu_n + p_i\mu_p) = q n_i (\mu_n + \mu_p) $$.

• Extrinsic: Doped semiconductor.

  • n-type: Pentavalent impurity (P, As). Majority carriers = electrons. n >> p. $$\displaystyle n \approx N_D $$, $$\displaystyle p = n_i^2/N_D $$.

  • p-type: Trivalent impurity (B, Al). Majority carriers = holes. p >> n. $$\displaystyle p \approx N_A $$, $$\displaystyle n = n_i^2/N_A $$.

• Conductivity: $$\displaystyle \sigma = q(n\mu_n + p\mu_p) $$. For n-type, $$\displaystyle \sigma \approx q N_D \mu_n $$; for p-type, $$\displaystyle \sigma \approx q N_A \mu_p $$.

1.3 Carrier Transport & Temperature Effects

• Drift Current: Current due to charge carriers moving under an applied electric field (E).

  Formula: $$\displaystyle J_{drift} = \sigma E = q(n\mu_n + p\mu_p)E $$

• Diffusion Current: Current due to charge carriers moving from higher concentration to lower concentration.

  Formula: $$\displaystyle J_{diff} = q D_n \frac{dn}{dx} $$ (for electrons), $$\displaystyle J_{diff} = -q D_p \frac{dp}{dx} $$ (for holes). $$\displaystyle D_n, D_p $$ are diffusion constants.

• Temperature Effects:

  • n_i increases exponentially with T (more thermal generation).

  • Mobility (μ) decreases with T (more lattice scattering).

  • Zener Diode Vz Temperature Coefficient:

    $$\displaystyle \frac{\Delta V_Z}{\Delta T} \approx \frac{V_Z}{T} \left( \frac{E_g}{kT^2} - \frac{1}{n} \right) $$ where n=1 for avalanche, n=2 for Zener breakdown.

    Exam Tip: For Vz < 5-6V, Zener effect dominates → negative coefficient. For Vz > 6-8V, avalanche dominates → positive coefficient.

2.0 PN JUNCTION DIODE & SPECIAL PURPOSE DIODES

2.1 PN Junction Diode

• Formation: Joining p-type and n-type semiconductor. Creates Depletion Region with built-in potential $$\displaystyle V_{bi} $$.

• Biasing:

  • Forward Bias: p-side to +ve, n-side to -ve. Reduces depletion width. Low resistance. Current flows.

  • Reverse Bias: p-side to -ve, n-side to +ve. Widens depletion region. High resistance. Small reverse saturation current ($$\displaystyle I_o $$) flows.

• V-I Characteristics:

  Ideal Diode Equation: $$\displaystyle I = I_o \left( e^{qV/kT} - 1 \right) $$

  Practical Diode: Includes series resistance ($$\displaystyle r_s $$). $$\displaystyle V = V_{bi} + IR_s $$ in forward bias.

• Transition Capacitance ($$\displaystyle C_T $$): Capacitance of depletion region (acts like parallel plate capacitor).

  Derivation: $$\displaystyle C_T = \frac{\epsilon A}{W} $$, where $W$ = depletion width.

  For abrupt junction: $$\displaystyle W \propto \sqrt{V_{bi} - V} $$ → $$\displaystyle C_T \propto \frac{1}{\sqrt{V_{bi} - V}} $$

• Breakdown Mechanisms:

  • Zener Breakdown: High electric field in narrow depletion region (heavily doped) → breaks covalent bonds. Occurs for Vz < 5-6V. Sharp breakdown.

  • Avalanche Breakdown: Carriers gain enough kinetic energy to ionize atoms → chain reaction. Occurs for Vz > 6-8V. Gradual breakdown.

2.2 Special Purpose Diodes (Detailed Analysis)

3.0 RECTIFIERS, FILTERS & WAVEFORM SHAPING

3.1 Rectifiers

• Half-Wave Rectifier (HWR):

  • Circuit: Single diode, transformer (optional).

  • Output: Only positive half-cycles. $$\displaystyle V_{dc} = \frac{V_m}{\pi} $$, $$\displaystyle I_{dc} = \frac{I_m}{\pi} $$.

  • Ripple Factor (r): $$\displaystyle \boxed{r = \frac{I_{rms}}{I_{dc}} = 1.21} $$ (very high).

  • PIV (Peak Inverse Voltage): $$\displaystyle PIV = V_m $$ (for capacitor filter, PIV = $$\displaystyle V_m $$).

• Full-Wave Rectifier (FWR):

  • Center-Tapped: Two diodes, center-tapped transformer. $$\displaystyle V_{dc} = \frac{2V_m}{\pi} $$, $$\displaystyle r = 0.48 $$.

  • Bridge Rectifier: Four diodes in bridge. No center tap needed. $$\displaystyle V_{dc} = \frac{2V_m}{\pi} $$, $$\displaystyle r = 0.48 $$.

  • PIV: For bridge, $$\displaystyle PIV = V_m $$ (each diode). For CT, $$\displaystyle PIV = 2V_m $$.

• Transformer Utilization Factor (TUF): Ratio of DC power delivered to AC rating of transformer.

  HWR: TUF = 0.287, FWR: TUF = 0.693, Bridge: TUF = 0.812.

• Rectifier Efficiency (η): $$\displaystyle \eta = \frac{P_{dc}}{P_{ac}} $$. Max for HWR = 40.6%, FWR/Bridge = 81.2%.

• Design Problems:

  • Transformer Rating (VA): $$\displaystyle P_{dc} = V_{dc} I_{dc} $$. Transformer secondary VA rating $$\displaystyle \geq \frac{P_{dc}}{\eta} $$.

  • DC Output Voltage: $$\displaystyle V_{dc} = \frac{2V_m}{\pi} - 2V_d $$ (bridge, $$\displaystyle V_d $$=diode drop).

  • PIV Calculation: Based on circuit configuration and presence of filter capacitor.

3.2 Filters

• L-section (Choke Input): Inductor (L) in series, capacitor (C) in shunt.

  • Ripple Factor: $$\displaystyle r = \frac{1}{6\sqrt{2} \pi^2 f^2 L C} $$ (for FWR). Better than HWR with C-filter.

• C-section (Capacitor Input): Capacitor (C) directly across load.

  • Ripple Factor (HWR): $$\displaystyle r = \frac{1}{2\sqrt{3} f R_L C} $$

  • Ripple Factor (FWR): $$\displaystyle r = \frac{1}{4\sqrt{3} f R_L C} $$

  • Disadvantage: High peak diode current, poor regulation.

• π-filter (LC): C-L-C. Best ripple reduction.

  Design: Choose C1 for peak diode current, L for ripple, C2 for load regulation.

3.3 Waveform Shaping Circuits

• Clippers: Remove part of input signal.

  • Series Clipper: Diode in series with load. Output across load.

  • Shunt Clipper: Diode in parallel with load. Output across diode.

  • Biased Clipper: Adds DC bias to set clipping level.

  • Operation: Diode conducts when forward biased → clips signal above/below reference.

• Clampers: Shift entire signal to a DC level.

  • Positive Clamper: Clips negative peaks to 0V. Adds +V_DC to signal.

  • Negative Clamper: Clips positive peaks to 0V. Adds -V_DC to signal.

  • Operation: During negative half-cycle, diode conducts, capacitor charges to $$\displaystyle V_m + V_D $$. During positive half, diode off, capacitor discharges through load → output = $$\displaystyle V_{in} + (V_m + V_D) $$.

  Exam Tip: Clampers do not change peak-to-peak amplitude; they shift DC level.

4.0 BIPOLAR JUNCTION TRANSISTOR (BJT)

4.1 Construction & Basic Operation

• Structure: NPN (Emitter n, Base p, Collector n) or PNP.

• Modes:

  • Active: $$\displaystyle V_{BE} $$ forward, $$\displaystyle V_{BC} $$ reverse. Amplification mode.

  • Saturation: Both junctions forward. $$\displaystyle V_{CE} \approx 0.2V $$. Switch ON.

  • Cutoff: Both junctions reverse. $$\displaystyle I_C \approx 0 $$. Switch OFF.

• Current Components: $$\displaystyle I_E = I_{E0} + I_{EB} $$ (minority), $$\displaystyle I_C = I_{C0} + I_{CB} $$ (minority), $$\displaystyle I_B = I_{EB} - I_{CB} $$.

• Current Equation: $$\displaystyle \boxed{I_E = I_C + I_B} $$

• Current Gains:

  • α (CB): $$\displaystyle I_C / I_E $$, 0.95 < α < 0.99.

  • β (CE): $$\displaystyle I_C / I_B $$, 20 < β < 500.

  • γ (CC): $$\displaystyle I_E / I_B $$, γ = β + 1.

  Relationship: $$\displaystyle \beta = \frac{\alpha}{1-\alpha} $$, $$\displaystyle \alpha = \frac{\beta}{\beta + 1} $$, $$\displaystyle \gamma = \beta + 1 $$.

4.2 Transistor Configurations & Characteristics

• Common Base (CB):

  • Input: Emitter, Output: Collector.

  • Input Char: $$\displaystyle I_E $$ vs $$\displaystyle V_{EB} $$ (almost like diode). Low input impedance ($$\displaystyle r_e \approx 25\Omega $$ at 1mA).

  • Output Char: $$\displaystyle I_C $$ vs $$\displaystyle V_{CB} $$. $$\displaystyle I_C \approx \alpha I_E $$ (independent of $$\displaystyle V_{CB} $$ after depletion region). High output impedance.

  • Parameters: α, $$\displaystyle r_o $$ (output resistance).

• Common Emitter (CE) - MOST USED:

  • Input: Base, Output: Collector.

  • Input Char: $$\displaystyle I_B $$ vs $$\displaystyle V_{BE} $$. Exponential. Input impedance $$\displaystyle h_{ie} $$ or $$\displaystyle r_{\pi} = \beta r_e $$.

  • Output Char: $$\displaystyle I_C $$ vs $$\displaystyle V_{CE} $$. Shows saturation, active, cutoff. $$\displaystyle I_C = \beta I_B $$ (in active). Moderate output impedance.

  • Parameters: β, $$\displaystyle r_{\pi} $$, $$\displaystyle r_o $$.

• Common Collector (CC) - Emitter Follower:

  • Input: Base, Output: Emitter.

  • Characteristics: Voltage gain ≈ 1, high input impedance, low output impedance.

  • Application: Buffer/Impedance matching stage.

4.3 DC Biasing & Stabilization

• Need for Biasing: To set Q-point (operating point) in active region for faithful amplification.

• Stability Factor (S): Measures sensitivity of $$\displaystyle I_C $$ to $\beta$ change. $$\displaystyle S = \frac{\partial I_C}{\partial I_{CBO}} \approx \frac{1+\beta}{1+\beta(R_B/(R_E+\beta r_e))} $$.

  Goal: Minimize S (S=1 ideal).

• Fixed Bias:

  • Circuit: $$\displaystyle V_{CC} - I_B R_B - V_{BE} = 0 $$.

  • Calc: $$\displaystyle I_B = \frac{V_{CC} - V_{BE}}{R_B} $$, $$\displaystyle I_C = \beta I_B $$, $$\displaystyle V_{CE} = V_{CC} - I_C R_C $$.

  • Disadvantage: Poor stability. $$\displaystyle I_C $$ highly dependent on β. S = 1+β.

• Voltage Divider Bias (Feedback Bias):

  • Circuit: $$\displaystyle R_1, R_2 $$ form divider. $$\displaystyle V_B = V_{CC} \frac{R_2}{R_1+R_2} $$. $$\displaystyle V_E = V_B - V_{BE} $$. $$\displaystyle I_E \approx \frac{V_E}{R_E} $$, $$\displaystyle I_C \approx I_E $$.

  • Analysis: $$\displaystyle I_{B1} \gg I_B $$ assumption → $$\displaystyle V_B $$ fixed. Excellent stability.

  • Stability: $$\displaystyle S \approx 1 + \frac{R_B}{R_E} $$ where $$\displaystyle R_B = R_1 // R_2 $$.

• Self-Bias (Emitter Bias):

  • Circuit: $$\displaystyle R_B $$ from $$\displaystyle V_{CC} $$ to base, $$\displaystyle R_E $$ in emitter.

  • Analysis: $$\displaystyle V_{BE} = I_B R_B + (I_B + I_C)R_E \approx I_C R_E $$ (if $$\displaystyle R_E \gg R_B/\beta $$).

  • Calc: $$\displaystyle I_C \approx \frac{V_{CC} - V_{BE}}{R_E + \frac{R_B}{\beta}} $$.

• Bias Compensation: Use diode (matches $$\displaystyle V_{BE} $$ temp coeff.), thermistor (NTC in $$\displaystyle R_E $$), sensistor (PTC in $$\displaystyle R_B $$).

• Thermal Runaway: Increase in $$\displaystyle I_C $$ → increase in power dissipation ($$\displaystyle I_C V_{CE} $$) → increase in temperature → further increase in $$\displaystyle I_C $$. Prevention: Use voltage divider/self-bias with $$\displaystyle R_E $$, heat sink, stabilize $$\displaystyle V_{BE} $$.

4.4 Small Signal Analysis & Models

• Hybrid-π Model (High Freq): $$\displaystyle g_m = I_C / V_T $$, $$\displaystyle r_{\pi} = \beta / g_m $$, $$\displaystyle r_o = V_A / I_C $$ (Early effect).

• h-parameter Model (Low Freq):

  • $$\displaystyle h_{ie} = \left. \frac{\Delta V_{BE}}{\Delta I_B} \right|_{V_{CE}=const} $$ (input impedance)

  • $$\displaystyle h_{fe} = \left. \frac{\Delta I_C}{\Delta I_B} \right|_{V_{CE}=const} $$ (current gain = β)

  • $$\displaystyle h_{oe} = \left. \frac{\Delta I_C}{\Delta V_{CE}} \right|_{I_B=const} $$ (output admittance)

  • $$\displaystyle h_{re} = \left. \frac{\Delta V_{BE}}{\Delta V_{CE}} \right|_{I_B=const} $$ (reverse voltage ratio, small)

• CE Amplifier Analysis (h-parameters):

  • Voltage Gain: $$\displaystyle \boxed{A_v = \frac{-h_{fe} R_L'}{h_{ie} + (1+h_{fe})R_E}} $$ where $$\displaystyle R_L' = R_C // R_L $$.

  • Input Impedance: $$\displaystyle Z_{in} = R_1 // R_2 // [h_{ie} + (1+h_{fe})R_E] $$.

  • Output Impedance: $$\displaystyle Z_{out} = R_C // r_o \approx R_C $$ (if $$\displaystyle r_o $$ large).

• AC & DC Load Lines:

  • DC Load Line: $$\displaystyle V_{CE} = V_{CC} - I_C R_C $$ (ignores $$\displaystyle R_E $$ for DC). Plotted on output char.

  • AC Load Line: $$\displaystyle v_{ce} = -i_c (R_C // R_L) $$. Slope steeper than DC line.

  • Q-point: Intersection of DC load line with IB line. Signal swing limited by saturation/cutoff.

  Finding from Graphs: $$\displaystyle h_{ie} $$ = slope of input char at Q-point. $$\displaystyle h_{fe} $$ = $$\displaystyle \Delta I_C / \Delta I_B $$ at constant $$\displaystyle V_{CE} $$.

4.5 Transistor as a Switch

• Cutoff (Switch OFF): $$\displaystyle V_{BE} < 0.7V $$, $$\displaystyle I_B \approx 0 $$, $$\displaystyle I_C \approx 0 $$, $$\displaystyle V_{CE} \approx V_{CC} $$.

• Saturation (Switch ON): $$\displaystyle V_{BE} > 0.7V $$, $$\displaystyle V_{CE} \approx 0.2V $$, $$\displaystyle I_C = \frac{V_{CC} - V_{CE(sat)}}{R_C} $$.

• Design: Ensure base current $$\displaystyle I_B > I_C(\text{required})/\beta(\text{min}) $$ to force saturation.

5.0 FIELD EFFECT TRANSISTORS (FETs) & MOSFETs

5.1 Junction Field Effect Transistor (JFET)

• Construction: n-channel (or p-channel) bar with p-type (or n-type) gate regions. Voltage-controlled device.

• Operation: Reverse bias gate-source ($$\displaystyle V_{GS} < 0 $$ for n-JFET) → depletion region widens → narrows channel → controls $$\displaystyle I_D $$.

• Pinch-off Voltage ($$\displaystyle V_P $$): $$\displaystyle V_{GS} $$ at which channel closes ($$\displaystyle I_D = 0 $$). Negative for n-JFET.

• Shockley Equation (Ideal):

  $$\displaystyle \boxed{I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2} $$ for $$\displaystyle V_{GS} \leq 0 $$, $$\displaystyle V_{DS} \geq |V_{GS}| $$.

  • $$\displaystyle I_{DSS} $$: Drain current at $$\displaystyle V_{GS}=0 $$.

  • $$\displaystyle V_P $$: Pinch-off voltage (magnitude).

• Characteristics:

  • Transfer Curve: $$\displaystyle I_D $$ vs $$\displaystyle V_{GS} $$ (parabolic). Saturation region follows Shockley.

  • Drain Curves: $$\displaystyle I_D $$ vs $$\displaystyle V_{DS} $$ for various $$\displaystyle V_{GS} $$. Ohmic region → saturation (constant current).

• Parameters:

  • Transconductance ($$\displaystyle g_m $$): $$\displaystyle g_m = \frac{dI_D}{dV_{GS}} = \frac{2I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right) $$.

    At $$\displaystyle V_{GS}=0 $$: $$\displaystyle g_{m0} = \frac{2I_{DSS}}{|V_P|} $$.

  • Drain-Source Resistance ($$\displaystyle r_{ds} $$): $$\displaystyle r_{ds} = \frac{1}{g_m} $$ in saturation.

• Configurations: Common Source (CS - high gain), Common Drain (CD/Source Follower - high Zin, low Zout), Common Gate (CG - low Zin, high Zout).

5.2 Metal-Oxide-Semiconductor FET (MOSFET)

• Construction: Gate insulated by SiO2 from channel.

• Enhancement Mode: No channel at $$\displaystyle V_{GS}=0 $$. Apply $$\displaystyle V_{GS} > V_{TH} $$ (n-enhancement) to induce channel.

• Depletion Mode: Channel exists at $$\displaystyle V_{GS}=0 $$. $$\displaystyle V_{GS} $$ of opposite polarity depletes channel.

• Threshold Voltage ($$\displaystyle V_{TH} $$): Minimum $$\displaystyle V_{GS} $$ to create inversion layer (enhancement) or to pinch-off (depletion).

• Operation Regions:

  • Cutoff: $$\displaystyle V_{GS} < V_{TH} $$ (enh), $$\displaystyle I_D \approx 0 $$.

  • Triode/Ohmic: $$\displaystyle V_{GS} > V_{TH} $$, $$\displaystyle V_{DS} < V_{GS} - V_{TH} $$. $$\displaystyle I_D \approx \mu_n C_{ox} \frac{W}{L} [(V_{GS}-V_{TH})V_{DS} - V_{DS}^2/2] $$.

  • Saturation: $$\displaystyle V_{GS} > V_{TH} $$, $$\displaystyle V_{DS} \geq V_{GS} - V_{TH} $$.

    $$\displaystyle \boxed{I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS}-V_{TH})^2 (1 + \lambda V_{DS})} $$ (λ accounts for channel length modulation).

• CS Amplifier (Enhancement):

  • Voltage Gain (Low Freq): $$\displaystyle A_v = -g_m (R_D // R_L) $$, where $$\displaystyle g_m = \sqrt{2 \mu_n C_{ox} (W/L) I_D} $$ or $$\displaystyle g_m = \frac{2I_D}{V_{GS}-V_{TH}} $$.

  • Small-signal model: $$\displaystyle g_m v_{gs} $$ current source, $$\displaystyle r_o = 1/(\lambda I_D) $$.

5.3 FET Biasing

• Voltage Divider Bias (Self-Bias for FET):

  • Circuit: $$\displaystyle R_1, R_2 $$ set $$\displaystyle V_G $$. Source resistor $$\displaystyle R_S $$ provides negative feedback.

  • Analysis: $$\displaystyle V_G = V_{DD} \frac{R_2}{R_1+R_2} $$. $$\displaystyle I_D \approx \frac{V_G - V_{TH}}{R_S} $$ (if $$\displaystyle R_S $$ large enough). $$\displaystyle V_{GS} = V_G - I_D R_S $$.

  • Advantage: Stable Q-point ($$\displaystyle I_D $$ independent of $\beta$ or $$\displaystyle g_m $$ variations).

6.0 AMPLIFIERS

6.1 Classification

6.2 Power Amplifiers

• Class B Push-Pull (Complementary Symmetry):

  • Circuit: NPN and PNP transistors (or matched pair). Input transformer (or cap-coupled) splits signal 180°.

  • Operation: Each transistor conducts for one half-cycle. Efficiency high (78.5%).

  • Disadvantage: Crossover distortion at zero crossing. Mitigated by Class AB bias.

• Darlington Amplifier:

  • Construction: Two BJTs connected (emitter of Q1 to base of Q2). Overall $$\displaystyle \beta_{total} = \beta_1 \beta_2 $$.

  • Characteristics: Very high current gain, very high input impedance ($$\displaystyle Z_{in} \approx \beta_1\beta_2 R_E $$), high output impedance.

  • Applications: Buffer stages, driver stages, high-impedance sensor interfaces.

6.3 Multistage Amplifiers

• Coupling Methods:

  • RC Coupling: Capacitor couples stages. Good for audio. Disadvantage: Poor low-freq response (due to coupling caps).

  • Transformer Coupling: Impedance matching, DC isolation. Good for RF/power. Disadvantage: Bulky, expensive, poor low-freq.

  • Direct Coupling: Direct connection. Advantage: Excellent low-freq response (including DC), IC compatible. Disadvantage: Q-point drift, requires careful design.

• Frequency Response:

  • Low Frequency: Effect of coupling and bypass capacitors → roll-off. Lower 3-dB frequency ($$\displaystyle f_L $$) determined by RC time constants.

  • High Frequency: Effect of internal capacitances ($$\displaystyle C_{\mu}, C_{\pi} $$) → roll-off. Upper 3-dB frequency ($$\displaystyle f_H $$).

  • Bandwidth: $$\displaystyle BW = f_H - f_L $$.

6.4 Advanced Techniques

• Bootstrapping:

  • Need: Increase input impedance of CE amplifier (which is inherently low: $$\displaystyle r_{\pi} $$).

  • Technique: Feed back a fraction of output voltage (in-phase) to input via capacitor. Makes input impedance appear much higher ($$\displaystyle Z_{in(modified)} \approx (1+A_v)Z_{in(original)} $$).

• Cascode Amplifier:

  • Construction: CE stage (high gain) followed by CB stage (high output impedance, high bandwidth).

  • Advantages: High input impedance, high output impedance, high gain, wide bandwidth (Miller effect minimized).

7.0 SPECIAL DEVICES & ADDITIONAL TOPICS

7.1 Unijunction Transistor (UJT)

• Construction: n-type bar with p-type emitter on one side. Two bases (B1, B2). Intrinsic stand-off ratio (η): $$\displaystyle \eta = \frac{R_{B1}}{R_{B1}+R_{B2}} $$, typically 0.5-0.8.

• Operation: Emitter reverse biased initially. When $$\displaystyle V_E = V_D + \eta V_{BB} $$ (peak point), UJT fires, $$\displaystyle I_E $$ increases, $$\displaystyle V_E $$ drops to valley point ($$\displaystyle V_V $$).

• V-I Characteristics: Negative resistance region between peak ($$\displaystyle I_P, V_P $$) and valley ($$\displaystyle I_V, V_V $$).

• UJT as Relaxation Oscillator:

  • Circuit: $R, C$ connected to emitter. $$\displaystyle V_{BB} $$ to B1-B2.

  • Operation: C charges through R to $$\displaystyle V_P $$. UJT fires, C discharges through UJT to $$\displaystyle V_V $$. UJT cuts off, C recharges.

  Frequency: $$\displaystyle \boxed{f = \frac{1}{R C \ln \left( \frac{1}{1-\eta} \right)}} $$

7.2 Thyristor (SCR)

• Construction: Four-layer p-n-p-n device. Three terminals: Anode (A), Cathode (K), Gate (G).

• Two-Transistor Analogy: Upper pnp ($$\displaystyle Q_1 $$) and lower npn ($$\displaystyle Q_2 $$) transistors connected regeneratively.

  • $$\displaystyle I_{A} = I_{G1} + I_{C2} $$, $$\displaystyle I_{K} = I_{E1} + I_{B2} $$.

  • When $$\displaystyle I_{C2} $$ increases → $$\displaystyle I_{B1} $$ increases → $$\displaystyle I_{C1} $$ increases → positive feedback → latch ON.

• V-I Characteristics:

  • Forward Blocking: $$\displaystyle V_{AK} < V_{BO} $$, $$\displaystyle I_A \approx 0 $$ (off).

  • Forward Conduction: $$\displaystyle V_{AK} > V_{BO} $$ or gate pulse → latches ON. $$\displaystyle V_{AK} \approx 1V $$.

  • Reverse Blocking: Reverse biased like diode.

• Key Currents:

  • Latching Current ($$\displaystyle I_L $$): Min $$\displaystyle I_A $$ to maintain conduction after gate pulse removed.

  • Holding Current ($$\displaystyle I_H $$): Min $$\displaystyle I_A $$ to keep SCR ON. $$\displaystyle I_H < I_L $$.

• Applications: Power control (phase control), Switching, Inverters, Motor speed control.

7.3 Current Mirror Circuits

• Basic Concept: Generate a constant current ($$\displaystyle I_{ref} $$) independent of load and supply variations.

• Simple Mirror (2 transistors): $$\displaystyle Q_1 $$ diode-connected ($$\displaystyle V_{CE1}=V_{BE} $$). $$\displaystyle I_{ref} = \frac{V_{CC} - V_{BE}}{R} $$. $$\displaystyle Q_2 $$ mirrors: $$\displaystyle I_{out} \approx I_{ref} $$ if $\beta$ large and matched.

  Equation: $$\displaystyle I_{out} = I_{ref} \frac{1 + \frac{2}{\beta}}{1 + \frac{1}{\beta}} \approx I_{ref} $$ for large β.

• Applications: Active load, bias current source in ICs (e.g., op-amps), biasing differential pairs.

7.4 Voltage Regulation

• Series Voltage Regulator (Zener):

  • Circuit: Zener diode in shunt with load, series pass transistor ($$\displaystyle Q_1 $$), resistor $R$.

  • Operation: Zener maintains $$\displaystyle V_Z $$. $$\displaystyle V_{out} = V_Z + V_{BE} $$. $R$ supplies $$\displaystyle I_Z + I_{B1} $$.

  • Advantage: Better regulation than shunt Zener alone (higher load current capability).

• IC Voltage Regulators (78xx/79xx):

  • Fixed: 7805 (+5V), 7812 (+12V), 7905 (-5V). Three terminals: Input, Ground, Output.

  • Adjustable: LM317 (positive), LM337 (negative). Output $$\displaystyle V_{out} = 1.25V (1 + R_2/R_1) + I_{adj}R_2 $$.

  • Features: Thermal shutdown, current limiting, good line/load regulation.

8.0 TRANSISTOR MODELS & ANALYSIS TECHNIQUES

8.1 Ebers-Moll Model

• Description: Charge-control model. Treats transistor as two diodes (emitter and collector) with current-controlled current sources.

• Equations (NPN, Active Mode):

  $$\displaystyle I_E = I_{ES} (e^{V_{BE}/V_T} - 1) - \alpha_R I_{CS} (e^{V_{BC}/V_T} - 1) $$

  $$\displaystyle I_C = \alpha_F I_{ES} (e^{V_{BE}/V_T} - 1) - I_{CS} (e^{V_{BC}/V_T} - 1) $$

  • $$\displaystyle I_{ES}, I_{CS} $$: Reverse saturation currents of base-emitter and base-collector diodes.

  • $$\displaystyle \alpha_F $$: Forward common-base current gain (~0.99).

  • $$\displaystyle \alpha_R $$: Reverse common-base current gain (~0.5).

• Use: Good for large-signal analysis, switching circuits.

8.2 Hybrid-π Model

• Parameters (for small-signal, high-frequency):

  • $$\displaystyle g_m = \frac{I_C}{V_T} $$ (transconductance)

  • $$\displaystyle r_{\pi} = \frac{\beta}{g_m} $$ (input resistance)

  • $$\displaystyle r_o = \frac{V_A}{I_C} $$ (output resistance due to Early effect, $$\displaystyle V_A $$ = Early voltage)

  • $$\displaystyle C_{\pi} = C_{be} + C_{bc}(1 - g_m R_L') $$ (Miller effect)

  • $$\displaystyle C_{\mu} = C_{bc} $$ (feedback capacitance)

• Application: High-frequency CE amplifier analysis. $$\displaystyle A_v = -g_m (R_C // r_o // R_L) $$ at mid-frequencies.

8.3 Analysis from Graphs

• Finding h-parameters from CE Characteristics:

  • $$\displaystyle h_{ie} $$: At constant $$\displaystyle V_{CE} $$, slope of $$\displaystyle V_{BE} $$ vs $$\displaystyle I_B $$ curve at Q-point.

  • $$\displaystyle h_{fe} $$: At constant $$\displaystyle V_{CE} $$, $$\displaystyle \Delta I_C / \Delta I_B $$ around Q-point.

  • $$\displaystyle h_{oe} $$: At constant $$\displaystyle I_B $$, slope of $$\displaystyle I_C $$ vs $$\displaystyle V_{CE} $$ curve at Q-point. $$\displaystyle h_{oe} = 1/r_o $$.

  • $$\displaystyle h_{re} $$: At constant $$\displaystyle I_B $$, $$\displaystyle \Delta V_{BE} / \Delta V_{CE} $$. Usually very small (<0.001).

\boxed{\text{END OF UNIT 3 NOTES}} Exam Strategy: Focus on derivations (ripple factor, transition capacitance, gain formulas), numerical problems (biasing, rectifier design, JFET/MOSFET calculations), and comparisons (diode types, amplifier classes, biasing techniques). Always draw clear diagrams for V-I characteristics and circuits.