UNIT 2: Electronic Devices - Exam-Focused Short Notes

1.0 Semiconductor Fundamentals & Energy Bands

1.1 Intrinsic vs. Extrinsic Semiconductors

• Intrinsic Semiconductor: Pure semiconductor (Si, Ge). Equal number of free electrons ($n$) and holes ($p$): $$\displaystyle n = p = n_i $$.

  • $$\displaystyle n_i $$ = intrinsic carrier concentration.

  • Conductivity: $$\displaystyle \sigma = q(n_i\mu_n + p_i\mu_p) = q n_i (\mu_n + \mu_p) $$.

• Extrinsic Semiconductor: Doped with impurities to control conductivity.

  • n-type: Donor atoms (Group V, e.g., P, As) add free electrons. Majority carriers = electrons. $n \gg p$.

  • p-type: Acceptor atoms (Group III, e.g., B, Al) add holes. Majority carriers = holes. $p \gg n$.

  • Mass Action Law: $$\displaystyle np = n_i^2 $$ (holds at equilibrium for both intrinsic & extrinsic).

1.2 Energy Band Structure

[!TIP] At room temperature, thermal energy excites some electrons from VB to CB, creating e-h pairs in semiconductors.

1.3 Carrier Concentration & Conductivity

• n-type: $$\displaystyle n \approx N_D $$ (donor concentration), $$\displaystyle p = n_i^2 / N_D $$.

• p-type: $$\displaystyle p \approx N_A $$, $$\displaystyle n = n_i^2 / N_A $$.

• Conductivity: $$\displaystyle \sigma = q(n\mu_n + p\mu_p) $$.

• Example Problem: Given $\sigma$, $$\displaystyle \mu_p $$, find hole concentration in p-type Ge.

  • For p-type: $$\displaystyle \sigma \approx q p \mu_p $$ (since $p \gg n$).

  • $$\displaystyle \therefore p = \frac{\sigma}{q \mu_p} $$.

1.4 Equilibrium Condition

• In a semiconductor at thermal equilibrium, the rate of generation of e-h pairs equals the rate of recombination.

• Fermi Level ($$\displaystyle E_F $$): Energy level at which probability of electron occupancy is ½.

  • Intrinsic: $$\displaystyle E_F $$ near mid-gap.

  • n-type: $$\displaystyle E_F $$ shifts up towards $$\displaystyle E_C $$.

  • p-type: $$\displaystyle E_F $$ shifts down towards $$\displaystyle E_V $$.

1.5 Elemental vs. Compound Semiconductors

• Elemental: Single element. E.g., Silicon (Si), Germanium (Ge).

• Compound: Two or more elements. E.g., Gallium Arsenide (GaAs), Cadmium Sulfide (CdS).

  • Advantages: Direct bandgap (better for optoelectronics), higher electron mobility, higher temperature operation.

2.0 P-N Junction Diode & Characteristics

2.1 Construction & Working

• Formed by joining p-type and n-type semiconductors.

• Depletion Region: Formed near junction due to diffusion of carriers. Contains immobile ions. Acts as a barrier.

• Potential Barrier ($$\displaystyle V_0 $$): Built-in potential across depletion region (~0.7V Si, 0.3V Ge).

2.2 V-I Characteristics

• Forward Bias: p-side to +ve, n-side to -ve. Reduces barrier, current increases exponentially after ~0.7V (Si).

• Reverse Bias: Increases barrier, very small reverse saturation current ($$\displaystyle I_0 $$) flows (µA range). Breakdown occurs at high reverse voltage.

2.3 Diode Current Equation & Derivation

• Shockley Diode Equation:

$$I_D = I_0 \left( e^{\frac{qV_D}{n k T}} - 1 \right)$$

where:

*   $$\displaystyle I_D $$ = diode current

*   $$\displaystyle I_0 $$ = reverse saturation current

*   $q$ = electronic charge ($$\displaystyle 1.6 \times 10^{-19} $$ C)

*   $$\displaystyle V_D $$ = voltage across diode

*   $n$ = emission coefficient (1-2)

*   $k$ = Boltzmann constant ($$\displaystyle 1.38 \times 10^{-23} $$ J/K)

*   $T$ = absolute temperature (K)

Derivation from Current Components:

1. Forward Current: $$\displaystyle I_{nF} = I_{0n}(e^{qV/kT} - 1) $$ (electron injection from n→p)

2. Forward Current: $$\displaystyle I_{pF} = I_{0p}(e^{qV/kT} - 1) $$ (hole injection from p→n)

3. Total Forward: $$\displaystyle I_F = (I_{0n} + I_{0p})(e^{qV/kT} - 1) = I_0(e^{qV/kT} - 1) $$.

4. Reverse Current: $$\displaystyle I_R \approx -I_0 $$ (for $$\displaystyle V_D < 0 $$, $$\displaystyle e^{qV/kT} \approx 0 $$).

2.4 Transition (Depletion) Capacitance

• Definition: Capacitance due to change in width of depletion region with applied voltage.

• Derivation for Abrupt Junction:

  • Depletion width: $$\displaystyle W = \sqrt{\frac{2\epsilon_s}{q} \left( \frac{1}{N_A} + \frac{1}{N_D} \right) (V_0 - V)} $$

  • Capacitance: $$\displaystyle C_T = \frac{\epsilon_s A}{W} \propto (V_0 - V)^{-1/2} $$

$$\boxed{C_T = \frac{C_{T0}}{(1 - V/V_0)^{1/2}}}$$

where $$\displaystyle C_{T0} $$ is capacitance at $$\displaystyle V=0 $$.

2.5 Breakdown Mechanisms

2.6 Ideal vs. Practical Diode

3.0 Special Purpose Diodes

3.1 Zener Diode

• Construction: Heavily doped p-n junction. Operates in reverse breakdown region.

• V-I Characteristics: Similar to diode in forward bias. In reverse, after Zener voltage $$\displaystyle V_Z $$, current increases sharply with voltage.

• Zener Voltage & Temperature Coeff.:

  • $$\displaystyle V_Z $$ is nearly constant over a wide range of $$\displaystyle I_Z $$.

  • Temperature Coefficient (TC): $$\displaystyle \text{TC} = \frac{\Delta V_Z / V_Z}{\Delta T} \times 100\% $$ (%/°C).

  • Calculation: Given $$\displaystyle V_{Z1} $$ at $$\displaystyle T_1 $$, $$\displaystyle V_{Z2} $$ at $$\displaystyle T_2 $$:

$$\text{TC} = \frac{(V_{Z2} - V_{Z1}) / V_{Z1}}{(T_2 - T_1)} \times 100\%$$

• Applications:

  • Voltage Regulation (Shunt): Zener in parallel with load. $$\displaystyle V_Z $$ stabilizes $$\displaystyle V_L $$.

  • Series Regulator: Zener sets reference for transistor emitter.

3.2 Tunnel Diode

• Construction: Heavily doped p-n junction ($$\displaystyle N_A, N_D \approx 10^{19} $$/cm³). Very narrow depletion region (~10 nm).

• Working & Characteristics:

  • Tunneling: Quantum mechanical effect. Carriers penetrate barrier without sufficient energy.

  • V-I Curve: Peak Point ($$\displaystyle I_P, V_P $$), Valley Point ($$\displaystyle I_V, V_V $$). Negative Resistance Region between peak and valley.

  • Conditions for Tunneling: Heavy doping, narrow barrier, low forward bias (< $$\displaystyle V_P $$).

• Applications: High-speed switching, oscillators, amplifiers (RF range).

3.3 Varactor (Varicap) Diode

• Construction: p-n junction operated in reverse bias. Depletion width acts as dielectric of a capacitor.

• Capacitance-Voltage Relation:

$$C_j = \frac{C_{j0}}{(1 - V_R/V_{bi})^m}$$

where $m$ depends on junction profile (0.5 for abrupt, 0.33 for linear).

*   $$\displaystyle C_{j0} $$: zero-bias capacitance.

*   $$\displaystyle V_R $$: reverse bias voltage.

*   $$\displaystyle V_{bi} $$: built-in potential.

• Applications: Voltage-controlled capacitor in tuning circuits (TV, radio), frequency multipliers.

3.4 Schottky Diode

• Construction: Metal (e.g., Al, Au) - Semiconductor (n-type) junction. Majority carrier device.

• Characteristics vs. PN Diode:

  • Lower forward voltage drop (~0.2-0.3V).

  • Faster switching (no minority carrier storage, $$\displaystyle t_{rr} \approx 0 $$).

  • Higher reverse leakage current.

  • Lower breakdown voltage.

• Applications: High-frequency rectifiers, clamping circuits, RF mixers, power supplies (to reduce losses).

3.5 Photo Diode & Photo Transistor

• Photo Diode:

  • Operation: Reverse-biased p-n junction. Incident light generates e-h pairs in depletion region → increases reverse current (photocurrent).

  • Modes:

    • Photoconductive: Reverse bias, high speed, high gain. Current ∝ light intensity.

    • Photovoltaic: Zero bias, generates voltage (solar cell principle).

  • Applications: Light detectors, optical switches, fiber optic comms.

• Photo Transistor: Base exposed to light. Base current generated by light → amplified collector current. Higher sensitivity than photodiode.

3.6 LED & Solar Cell (Brief)

• LED: Recombination of e-h in direct bandgap material emits light. Forward biased. Color depends on bandgap.

• Solar Cell: Large-area p-n junction. Operates in photovoltaic mode. Generates power from light ($$\displaystyle P_{out} = V_{OC} \times I_{SC} $$).

4.0 Rectifiers & Power Supplies

4.1 Half-Wave Rectifier (HWR)

• Circuit: Single diode, transformer (optional), load $$\displaystyle R_L $$.

• Output Voltage (no filter):

$$V_{DC} = \frac{V_m}{\pi} \quad \text{(for ideal diode)}$$

where $$\displaystyle V_m = $$ peak AC voltage.

• Ripple Factor:

$$\boxed{r = \frac{V_{r(rms)}}{V_{DC}} = 1.21}$$

• Efficiency:

$$\eta = \frac{P_{DC}}{P_{AC}} \times 100\% = 40.6\%$$

• PIV: $$\displaystyle V_{PIV} = V_m $$ (for ideal diode).

4.2 Full-Wave Rectifiers

• A. Center-Tapped (CT-FWR):

  • Circuit: CT transformer, 2 diodes.

  • $$\displaystyle V_{DC} = \frac{2V_m}{\pi} $$ (each secondary half: $$\displaystyle V_m/2 $$).

  • Ripple Factor: $$\displaystyle r = 0.48 $$.

  • Efficiency: $$\displaystyle \eta = 81.2\% $$.

  • PIV: $$\displaystyle V_{PIV} = 2V_m $$.

• B. Bridge FWR:

  • Circuit: 4 diodes in bridge, no CT needed.

  • $$\displaystyle V_{DC} = \frac{2V_m}{\pi} $$ (same as CT-FWR).

  • Ripple Factor: $$\displaystyle r = 0.48 $$.

  • Efficiency: $$\displaystyle \eta = 81.2\% $$.

  • PIV: $$\displaystyle V_{PIV} = V_m $$ (each diode).

  • Advantage over CT: No CT needed, PIV lower.

4.3 Comparison: HWR vs. CT-FWR vs. Bridge

4.4 Filters & Smoothing Circuits

• Capacitor Filter (π-section): Capacitor across load. Charges to $$\displaystyle V_m $$, discharges through $$\displaystyle R_L $$ between peaks.

  • Ripple Factor (approx): $$\displaystyle r \approx \frac{1}{2\sqrt{3} f C R_L} $$ (HWR), $$\displaystyle \frac{1}{4\sqrt{3} f C R_L} $$ (FWR).

• Inductor Filter (L-section): Inductor in series with load. Opposes change in current.

  • Ripple Factor (FWR): $$\displaystyle \boxed{r = \frac{R_L}{3\sqrt{2} \omega L}} $$ (Derivation required).

• LC Filter (π-type): L in series, C in parallel. Best filtering. Ripple factor very low.

  • Design Problem: Given $$\displaystyle V_{DC} $$, $$\displaystyle I_L $$, ripple % → find $L$ and $C$.

4.5 Transformer Rating for Rectifiers

• DC Power Output: $$\displaystyle P_{DC} = V_{DC} \times I_{DC} $$.

• Transformer Secondary RMS Voltage ($$\displaystyle V_s $$):

  • HWR: $$\displaystyle V_s = V_m $$ (no filter), $$\displaystyle V_s \approx 1.8 V_{DC} $$ (with C-filter).

  • FWR: $$\displaystyle V_s = V_m/\sqrt{2} $$ (no filter), $$\displaystyle V_s \approx 1.2 V_{DC} $$ (with C-filter).

• Rating (VA): $$\displaystyle VA = V_s \times I_s $$ (RMS).

  • $$\displaystyle I_s $$ (RMS) depends on waveform:

    • HWR: $$\displaystyle I_s = I_m/2 $$

    • FWR: $$\displaystyle I_s = I_m/\sqrt{2} $$

5.0 Bipolar Junction Transistor (BJT)

5.1 Construction & Basic Operation

• NPN: n-emitter, p-base, n-collector. Conventional current: $$\displaystyle I_E = I_B + I_C $$.

• PNP: p-emitter, n-base, p-collector. Currents opposite direction.

• Operation: Emitter-base junction forward biased, collector-base junction reverse biased (active mode).

• Current Flow: Injected minority carriers from emitter into base → diffuse across thin base → collected by collector.

5.2 Transistor Current Components & Equation

• Components:

  • $$\displaystyle I_{E} = I_{E0} + I_{EB0} $$ (electron + hole currents)

  • $$\displaystyle I_{C} = I_{C0} + I_{CB0} $$ (electron + hole currents)

  • $$\displaystyle I_{B} = I_{EB0} - I_{CB0} $$

• Current Gains:

  • Common Base: $$\displaystyle \alpha = I_C / I_E $$ (0.95 - 0.99)

  • Common Emitter: $$\displaystyle \beta = I_C / I_B $$ (20 - 500)

• Deduction of Current Equation:

$$I_E = I_C + I_B$$

From $\alpha$ and $\beta$ relation:

$$\boxed{\beta = \frac{\alpha}{1-\alpha}, \quad \alpha = \frac{\beta}{1+\beta}}$$

5.3 Configurations

5.4 CE Characteristics

• Input Characteristics: $$\displaystyle I_B $$ vs. $$\displaystyle V_{BE} $$ (similar to diode curve). $$\displaystyle V_{BE} \approx 0.7 $$V for Si.

• Output Characteristics: $$\displaystyle I_C $$ vs. $$\displaystyle V_{CE} $$ for different $$\displaystyle I_B $$. Three regions:

  1. Cut-off: $$\displaystyle I_B \approx 0 $$, $$\displaystyle I_C \approx I_{CEO} $$.

  2. Active: $$\displaystyle V_{CE} > 0.7 $$V, $$\displaystyle I_C = \beta I_B $$ (constant current).

  3. Saturation: $$\displaystyle V_{CE} < V_{BE} $$, $$\displaystyle I_C < \beta I_B $$, both junctions forward biased.

5.5 Parameters from Characteristics

• h-parameters (CE, hybrid):

  • $$\displaystyle h_{ie} = \left. \frac{\Delta V_{BE}}{\Delta I_B} \right|_{V_{CE}=const} $$ (input impedance)

  • $$\displaystyle h_{re} = \left. \frac{\Delta V_{BE}}{\Delta V_{CE}} \right|_{I_B=const} $$ (reverse voltage ratio, small)

  • $$\displaystyle h_{fe} = \left. \frac{\Delta I_C}{\Delta I_B} \right|_{V_{CE}=const} $$ (current gain, $\beta$)

  • $$\displaystyle h_{oe} = \left. \frac{\Delta I_C}{\Delta V_{CE}} \right|_{I_B=const} $$ (output admittance)

• Leakage Currents:

  • $$\displaystyle I_{CBO} $$: Collector-Base reverse saturation current (with emitter open).

  • $$\displaystyle I_{CEO} $$: Collector-Emitter leakage (with base open). $$\displaystyle I_{CEO} = (1+\beta) I_{CBO} $$.

• Finding $\alpha, \beta$ from given leakage:

  Given $$\displaystyle I_{CBO} $$ and $$\displaystyle I_{CEO} $$:

$$\beta = \frac{I_{CEO} - I_{CBO}}{I_{CBO}}, \quad \alpha = \frac{\beta}{1+\beta}$$

5.6 BJT as a Switch

• Cut-off (OFF): $$\displaystyle V_{BE} < 0.7 $$V, $$\displaystyle I_B \approx 0 $$, $$\displaystyle I_C \approx 0 $$, $$\displaystyle V_{CE} \approx V_{CC} $$.

• Saturation (ON): Both junctions forward biased. $$\displaystyle V_{CE} \approx 0.2 $$V (sat), $$\displaystyle I_C = \frac{V_{CC} - V_{CE(sat)}}{R_C} $$.

• Design: Choose $$\displaystyle R_B $$ to ensure $$\displaystyle I_B > I_{B(sat)} = I_{C(sat)}/\beta $$ for saturation.

6.0 BJT Biasing & Stabilization

6.1 Need for Biasing & Q-point

• Need: Establish a stable DC operating point (Q-point: $$\displaystyle I_{CQ}, V_{CEQ} $$) in active region for faithful amplification.

• Stability: Q-point should remain stable against temperature variations and $\beta$ changes.

6.2 Fixed Bias Circuit

• Circuit: $$\displaystyle R_B $$ from $$\displaystyle V_{CC} $$ to base.

• Analysis:

$$I_B = \frac{V_{CC} - V_{BE}}{R_B}, \quad I_C = \beta I_B, \quad V_{CE} = V_{CC} - I_C R_C$$

• Stability Factor (S):

$$\boxed{S = \frac{\Delta I_C}{\Delta I_{CBO}} = 1 + \beta}$$

*   **Very poor stability** ($S \approx \beta$, large). Not used in practice.

6.3 Emitter Feedback Bias (Self-Bias)

• Circuit: $$\displaystyle R_B $$ from $$\displaystyle V_{CC} $$ to base, $$\displaystyle R_E $$ in emitter.

• Analysis (approx):

$$V_B = V_{CC} \frac{R_2}{R_1+R_2}, \quad V_E = V_B - V_{BE}, \quad I_E \approx I_C = \frac{V_E}{R_E}$$

• Stability Factor:

$$\boxed{S = \frac{1+\beta}{1+\beta \frac{R_E}{R_B+R_E}}}$$

*   **Improved stability** if $$\displaystyle R_E \gg R_B/(1+\beta) $$.

6.4 Voltage Divider Bias

• Circuit: Two resistors ($$\displaystyle R_1, R_2 $$) form voltage divider from $$\displaystyle V_{CC} $$ to ground. Base connected to tap. $$\displaystyle R_E $$ in emitter.

• Analysis (Thevenin):

$$V_{TH} = V_{CC} \frac{R_2}{R_1+R_2}, \quad R_{TH} = R_1 // R_2$$

$$I_B = \frac{V_{TH} - V_{BE}}{R_{TH} + (\beta+1)R_E}$$

$$I_C \approx \beta I_B, \quad V_{CE} = V_{CC} - I_C R_C - I_E R_E$$

• Stability Factor (S):

$$\boxed{S = \frac{1+\beta}{1+\beta \frac{R_E}{R_{TH}+(\beta+1)R_E}} \approx 1 + \frac{R_{TH}}{R_E} \quad \text{if } \beta R_E \gg R_{TH}}$$

*   **Excellent stability** ($S \approx 1$). Most widely used.

6.5 AC & DC Load Line Analysis

• DC Load Line: From $$\displaystyle I_C $$ vs $$\displaystyle V_{CE} $$ equation: $$\displaystyle V_{CE} = V_{CC} - I_C R_C $$ (ignoring $$\displaystyle R_E $$ for DC). Straight line from ($$\displaystyle V_{CC}, 0 $$) to ($$\displaystyle 0, V_{CC}/R_C $$).

• AC Load Line: For signal analysis. Slope = $$\displaystyle -1/R_{L}^{'} $$, where $$\displaystyle R_{L}^{'} = R_C // R_L $$. Passes through Q-point.

• Derivation: AC equation: $$\displaystyle v_{ce} = -i_c R_{L}^{'} $$. On top of DC bias.

6.6 Bias Stabilization & Thermal Runaway

• Thermal Runaway: Increase in $$\displaystyle I_C $$ → increases power dissipation ($$\displaystyle I_C V_{CE} $$) → increases temperature → further increases $$\displaystyle I_C $$ → destructive cycle.

• Causes: $$\displaystyle I_{CBO} $$ doubles per 10°C rise; $\beta$ increases with temperature.

• Prevention:

  1. Use Voltage Divider/Self-Bias: Negative feedback via $$\displaystyle R_E $$.

  2. Include $$\displaystyle R_E $$: Stabilizes $$\displaystyle I_E $$ (and $$\displaystyle I_C $$).

  3. Use Swamping Resistor: Small $R$ in series with $$\displaystyle R_E $$ to limit voltage drop.

  4. Choose low-power transistor, heat sink.

7.0 BJT Small Signal Analysis & Amplifiers

7.1 Hybrid-π Model & h-Parameter Model

• h-Parameter Model (CE):

  
  Input: v_be = h_ie i_b + h_re v_ce
  
  Output: i_c = h_fe i_b + h_oe v_ce
  
  

  • $$\displaystyle h_{ie} $$ (Ω), $$\displaystyle h_{fe} $$ (unitless), $$\displaystyle h_{oe} $$ (S), $$\displaystyle h_{re} $$ (unitless, small).

• Hybrid-π Model (more fundamental):

  • $$\displaystyle g_m = \frac{I_C}{V_T} $$ (transconductance, $$\displaystyle V_T \approx 26 $$mV at 300K)

  • $$\displaystyle r_\pi = \frac{\beta}{g_m} $$

  • $$\displaystyle r_o = \frac{V_A}{I_C} $$ (Early effect, $$\displaystyle V_A $$ = Early voltage)

7.2 CE Amplifier Analysis (h-parameters)

• Circuit: $$\displaystyle R_1, R_2 $$ voltage divider bias, $$\displaystyle R_E $$ (bypassed by $$\displaystyle C_E $$ for AC), $$\displaystyle R_C $$, $$\displaystyle R_L $$.

• Mid-frequency Analysis (capacitors shorted):

  • Voltage Gain: $$\displaystyle A_v = \frac{v_o}{v_i} = - \frac{h_{fe} R_{L}^{'}}{h_{ie} + (\beta+1) R_E} $$ (if $$\displaystyle R_E $$ not fully bypassed). With $$\displaystyle C_E $$, $$\displaystyle R_E $$ shorted for AC:

$$\boxed{A_v = - \frac{h_{fe} R_{L}^{'}}{h_{ie}}}$$

*   **Input Impedance:** $$\displaystyle Z_{in} = R_1 // R_2 // [h_{ie} + (\beta+1) R_E] $$.

*   **Output Impedance:** $$\displaystyle Z_{out} = R_C // r_o \approx R_C $$ (if $$\displaystyle r_o \gg R_C $$).

7.3 CC & CB Amplifiers

• CC (Emitter Follower): $$\displaystyle A_v \approx 1 $$, $$\displaystyle Z_{in} $$ very high, $$\displaystyle Z_{out} $$ low. Used for impedance matching.

• CB (Base Follower): $$\displaystyle A_v \approx \alpha R_L / r_e $$, $$\displaystyle Z_{in} $$ low, $$\displaystyle Z_{out} $$ high. Used in high-frequency applications.

7.4 Comparison of CE, CB, CC

7.5 Frequency Response

• Low Frequency: Effect of coupling/bypass capacitors. $$\displaystyle f_L $$ determined by RC time constants.

• High Frequency: Effect of junction capacitances ($$\displaystyle C_{\mu}, C_{\pi} $$). $$\displaystyle f_H $$ determined by Miller effect.

• Bandwidth: $$\displaystyle BW = f_H - f_L $$. Gain-Bandwidth Product constant for single-stage amp.

7.6 Bootstrapping Technique

• Need: Increase input impedance of CE amplifier (especially for $$\displaystyle R_1//R_2 $$ limited).

• Circuit: Feedback capacitor from output to input (via $$\displaystyle R_B $$).

• Effect: Part of output fed back in phase to input → increases effective $$\displaystyle Z_{in} $$ by factor $$\displaystyle (1+A_v) $$.

7.7 Darlington Amplifier

• Circuit: Two BJTs (Q1, Q2) connected. Emitter of Q1 to base of Q2. Collector common.

• Characteristics:

  • Overall $$\displaystyle \beta_{total} = \beta_1 \beta_2 $$ (very high, >10,000).

  • $$\displaystyle V_{BE(total)} = V_{BE1} + V_{BE2} \approx 1.2 $$V.

  • $$\displaystyle I_{E1} = I_{B2} $$, $$\displaystyle I_{E2} = \beta_2 I_{B2} $$.

• Applications: Input stage of op-amps, high-impedance sensors.

8.0 Power Amplifiers

8.1 Classification

8.2 Class A Amplifier

• Circuit: Transformer coupled or RC coupled. Q-point at center of load line.

• Operation: Transistor conducts entire cycle.

• Efficiency Derivation (Transformer coupled):

$$P_{DC} = V_{CC} I_{CQ}$$

$$P_{AC} = \frac{(I_{C(peak)} R_L^{'})^2}{2 R_L^{'}} = \frac{I_{CQ}^2 R_L^{'}}{2}$$

$$\boxed{\eta_{max} = \frac{P_{AC}}{P_{DC}} = 50\%}$$

(For RC coupled with capacitive load, $$\displaystyle \eta_{max} = 25\% $$).

8.3 Class B Power Amplifier

• Circuit: Push-Pull (two transistors, complementary or identical with phase splitter).

• Operation: Each transistor conducts 180°. Q-point at cut-off.

• Crossover Distortion: Occurs when input signal is small (< $$\displaystyle V_{BE} $$). Neither transistor conducts.

• Efficiency: $$\displaystyle \eta_{max} = \frac{\pi}{4} \approx 78.5\% $$.

8.4 Push-Pull Amplifier

• Complementary Symmetry: NPN and PNP transistors (or N-MOS & P-MOS). No transformer needed.

• Advantages: No transformer, no even harmonics, higher efficiency.

• Disadvantages: Need matched transistors, crossover distortion → biased slightly into Class AB.

8.5 Coupling Methods

9.0 Field Effect Transistors (FETs)

9.1 JFET

• Construction: n-channel (or p-channel) bar with p-n junctions forming gate. Ohmic contacts to source and drain.

• Operation: Reverse bias gate-source ($$\displaystyle V_{GS} < 0 $$ for n-channel). Depletion region controls channel width.

• Pinch-off: At $$\displaystyle V_{GS} = V_P $$ (negative), channel closes, $$\displaystyle I_D $$ saturates.

• Shockley's Equation:

$$\boxed{I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2 \quad \text{(for } V_{GS} \leq 0, V_{DS} \geq |V_P| \text{)}}$$

where $$\displaystyle I_{DSS} $$ = drain current at $$\displaystyle V_{GS}=0 $$, $$\displaystyle V_P $$ = pinch-off voltage (negative for n-channel).

• Parameters:

  • Transconductance ($$\displaystyle g_m $$): $$\displaystyle g_m = \frac{\partial I_D}{\partial V_{GS}} = \frac{2 I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right) $$.

    • At $$\displaystyle V_{GS}=0 $$: $$\displaystyle g_{m0} = \frac{2 I_{DSS}}{|V_P|} $$.

  • Drain-Source Resistance ($$\displaystyle r_{ds} $$): $$\displaystyle r_{ds} = \frac{1}{g_m} $$ (in saturation).

• Characteristics:

  • Transfer: $$\displaystyle I_D $$ vs $$\displaystyle V_{GS} $$ (parabolic).

  • Drain: $$\displaystyle I_D $$ vs $$\displaystyle V_{DS} $$ (ohmic region → saturation).

9.2 MOSFET

• Construction: Metal gate, Oxide (SiO₂) insulator, Semiconductor substrate.

• Enhancement Mode (n-channel):

  • $$\displaystyle V_{GS} > V_{TH} $$ (threshold) → inversion layer (channel) forms → conduction.

  • No channel at $$\displaystyle V_{GS}=0 $$.

• Depletion Mode (n-channel):

  • Channel exists at $$\displaystyle V_{GS}=0 $$. $$\displaystyle V_{GS} < 0 $$ depletes channel → reduces $$\displaystyle I_D $$.

• Operation Regions:

  1. Cut-off: $$\displaystyle V_{GS} < V_{TH} $$ (E), $$\displaystyle I_D=0 $$.

  2. Triode/Ohmic: $$\displaystyle V_{GS} > V_{TH} $$, $$\displaystyle V_{DS} < V_{GS}-V_{TH} $$. $$\displaystyle I_D \approx k' \frac{W}{L} [(V_{GS}-V_{TH})V_{DS} - V_{DS}^2/2] $$.

  3. Saturation: $$\displaystyle V_{GS} > V_{TH} $$, $$\displaystyle V_{DS} \geq V_{GS}-V_{TH} $$. $$\displaystyle I_D = \frac{1}{2} k' \frac{W}{L} (V_{GS}-V_{TH})^2 (1+\lambda V_{DS}) $$.

• Why Voltage Controlled? Gate current $$\displaystyle I_G \approx 0 $$ (insulator). Input impedance extremely high ($$\displaystyle >10^9 $$ Ω). $$\displaystyle I_D $$ controlled by $$\displaystyle V_{GS} $$.

9.3 FET Biasing Circuits

• Voltage Divider Bias (Self-Bias for JFET):

  • Gate resistor $$\displaystyle R_G $$ large (MΩ) → $$\displaystyle V_G \approx V_{TH} $$? No, for JFET, gate is reverse biased via $$\displaystyle R_G $$ to source.

  • Analysis: $$\displaystyle I_G \approx 0 $$, so $$\displaystyle V_G = V_{DD} \frac{R_2}{R_1+R_2} $$. $$\displaystyle V_{GS} = V_G - I_D R_S $$. Use Shockley's equation to solve for $$\displaystyle I_D, V_{GS} $$.

• Numerical: Given $$\displaystyle I_{DSS}, V_P, R_S, R_1, R_2, V_{DD} $$ → find $$\displaystyle I_{DQ}, V_{GSQ}, V_{DSQ} $$.

9.4 FET Amplifier (Common Source)

• Circuit: Similar to CE, but $$\displaystyle R_G $$ large, source resistor $$\displaystyle R_S $$ (often partially bypassed).

• Voltage Gain (using hybrid-π for MOSFET):

$$A_v = -g_m (R_D // R_L)$$

where $$\displaystyle g_m = 2\sqrt{k I_D} $$ (for MOSFET in saturation, $$\displaystyle k = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} $$).

• Comparison with BJT:

  • Higher input impedance.

  • Lower transconductance ($$\displaystyle g_m $$ smaller than BJT $$\displaystyle g_m $$).

  • Lower noise.

  • More temperature stable.

10.0 Other Terminal Devices & Models

10.1 Unijunction Transistor (UJT)

• Construction: n-type bar with p-type emitter diffused near one end. Terminals: Emitter (E), Base1 (B1), Base2 (B2). Intrinsic stand-off ratio $$\displaystyle \eta = \frac{R_{B1}}{R_{B1}+R_{B2}} $$ (0.5-0.8).

• Operation & Characteristics:

  • Reverse Bias (OFF): $$\displaystyle V_E < V_D $$ (peak point). $$\displaystyle I_E $$ small.

  • Forward Bias (ON): $$\displaystyle V_E > V_D $$. Emitter fires, $$\displaystyle I_E $$ increases, $$\displaystyle V_E $$ drops to $$\displaystyle V_V $$ (valley). Negative Resistance Region between peak and valley.

• UJT as Relaxation Oscillator:

  • Circuit: $R, C$ from $$\displaystyle V_{BB} $$ to E, $$\displaystyle R_E $$ from E to B1.

  • Operation: $C$ charges through $R$ until $$\displaystyle V_E = V_P $$. UJT fires → $C$ discharges through B1 → $$\displaystyle V_E $$ drops below $$\displaystyle V_V $$ → UJT off → repeat.

  • Frequency: $$\displaystyle f \approx \frac{1}{R C \ln \frac{1}{1-\eta}} $$.

10.2 Thyristor (SCR)

• Construction: Four-layer (PNPN), three terminals: Anode (A), Cathode (K), Gate (G).

• Two-Transistor Analogy:

  • Upper: p-n-p (Q1), Lower: n-p-n (Q2).

  • $$\displaystyle I_A = I_{G1} + I_{C2} $$, $$\displaystyle I_K = I_{E1} + I_{B2} $$.

  • Gate current $$\displaystyle I_G $$ triggers by injecting carriers into Q2 base → $$\displaystyle I_{C2} $$ increases → positive feedback → both transistors saturate → SCR latches ON.

• V-I Characteristics:

  • Forward Blocking: $$\displaystyle V_{AK} < V_{BO} $$, $$\displaystyle I_A \approx 0 $$ (high impedance).

  • Forward Conducting: $$\displaystyle V_{AK} \approx 1 $$V (low impedance) after triggering.

  • Reverse Blocking: Like diode.

• Applications: AC power control (light dimmers, motor speed), inverters, overvoltage protection.

10.3 Transistor Models

• Ebers-Moll (E-M) Model (DC):

  • Based on two diodes (emitter-base, collector-base) with current-controlled current sources.

  • Equations:

$$I_E = I_{ES} (e^{V_{BE}/V_T} - 1) - \alpha_R I_{CS} (e^{V_{BC}/V_T} - 1)$$

$$I_C = \alpha_F I_{ES} (e^{V_{BE}/V_T} - 1) - I_{CS} (e^{V_{BC}/V_T} - 1)$$

*   Useful for large-signal DC analysis.

• Hybrid-π Model (AC):

  • Small-signal model for high-frequency analysis.

  • Parameters: $$\displaystyle g_m, r_\pi, r_o, C_\pi, C_\mu $$.

11.0 Multi-Stage & Special Circuits

11.1 Current Mirror Circuit

• Basic Circuit (2-transistor):

  • Q1 (diode-connected: C-B shorted), Q2 (output).

  • $$\displaystyle I_{REF} = \frac{V_{CC} - V_{BE}}{R} $$ sets reference.

  • Since $$\displaystyle V_{BE1} = V_{BE2} $$, $$\displaystyle I_{O} = I_{C2} \approx I_{C1} = I_{REF} $$ (if $\beta$ large).

  • Improved (with emitter resistor): $$\displaystyle I_O = \frac{R_1}{R_2} I_{REF} $$ (ratio independent of $\beta$).

• Applications:

  • Biasing in ICs (provides stable $$\displaystyle I_{CQ} $$).

  • Active load in differential amplifiers (high AC resistance).

11.2 Cascode Amplifier (Brief)

• Circuit: CE stage (Q1) followed by CB stage (Q2). Common terminal = base of Q2.

• Advantages: High output impedance, high bandwidth (reduces Miller effect), good isolation between input and output.

11.3 Clipper Circuits

• Function: Remove (clip) portion of input signal above/below a reference level.

• Types:

  • Series Clipper: Diode in series with load. Reference = $$\displaystyle V_D $$ (or biased with $$\displaystyle V_{ref} $$).

  • Shunt Clipper: Diode in parallel with load (reverse biased normally).

  • Positive/Negative Clippers: Clip positive/negative peaks.

  • Combinational: Two diodes (e.g., double-ended, biased both ways).

11.4 Clamper Circuits

• Function: Shift entire signal waveform up/down by a DC level (add DC offset).

• Types:

  • Positive Clamper: Shifts signal negative → positive. Diode in parallel with load, capacitor to ground. $$\displaystyle V_{out} \approx V_{in} + V_{peak} $$.

  • Negative Clamper: Shifts signal positive → negative. $$\displaystyle V_{out} \approx V_{in} - V_{peak} $$.

• Operation: Capacitor charges to peak of input during negative half (positive clamper), then acts as battery during positive half.

11.5 Voltage Regulation

• Series Voltage Regulator (Zener-based):

  • Circuit: Zener in parallel with load, series pass transistor ($$\displaystyle Q_1 $$), Zener + resistor from $$\displaystyle V_{in} $$ to base.

  • Operation: $$\displaystyle V_Z $$ sets $$\displaystyle V_{B1} $$, so $$\displaystyle V_E = V_B - V_{BE} \approx V_Z - 0.7 $$. $$\displaystyle V_{out} $$ stable.

  • Advantage: Load current supplied by $$\displaystyle Q_1 $$, not Zener → higher power handling.

• Voltage Regulation using ICs (78xx series):

  • Fixed Positive Regulators: 7805 (+5V), 7812 (+12V).

  • Pins: Input, Ground, Output.

  • Need: Input voltage $$\displaystyle V_{in} > V_{out} + 2-3V $$, capacitors for stability.

  • Advantages: Simple, thermal protection, short-circuit protection.

Key Takeaways for Exams:

1. Derivations: Diode current equation, Transition capacitance, Ripple factor (HWR/FWR+L), Load line equation, Current equation ($$\displaystyle I_E=I_C+I_B $$), CE gain.

2. Numericals: Zener TC, Rectifier $$\displaystyle V_{DC}/PIV $$/ripple/transformer rating, BJT bias ($$\displaystyle I_C, V_{CE}, R_B $$), h-parameters from graphs, FET $$\displaystyle I_D/g_m $$ (Shockley), UJT frequency.

3. Diode Types: Be very clear on Tunnel (negative resistance, tunneling conditions), Varactor ($$\displaystyle C_j \propto (V_{bi}-V_R)^{-m} $$), Schottky (metal-semiconductor, fast).

4. BJT Configurations: Know CE characteristics regions, h-parameter definitions, biasing stability factors (S for Fixed, Self, V-divider).

5. FET vs. BJT: FET is voltage-controlled (high $$\displaystyle Z_{in} $$), JFET uses Shockley's eq, MOSFET enhancement/depletion modes.

6. Special Circuits: Clipper vs. Clamper (shift vs. remove), Current mirror (basic & ratio), UJT oscillator (f formula), SCR two-transistor analogy.

[!TIP] In exams, always draw neat diagrams for characteristics and circuits. For derivations, state assumptions (ideal diode, constant $\beta$, etc.). For numericals, box final answer with units. For comparisons, use tables.