Electronic Devices (EC-304) - Unit 1 Short Notes

I. SEMICONDUCTOR FUNDAMENTALS & MATERIAL SCIENCE

Energy Band Theory

• Conductors: Valence band overlaps with conduction band → no forbidden gap → electrons free to move.

• Semiconductors: Small forbidden gap (~1 eV for Si, 0.67 eV for Ge) → some electrons can jump to conduction band at room temperature.

• Insulators: Large forbidden gap (>5 eV) → negligible conductivity.

• Equilibrium: Mass-action law: n₀p₀ = nᵢ², where n₀, p₀ are equilibrium electron/hole concentrations, nᵢ is intrinsic carrier concentration.

Intrinsic Semiconductors

• Pure semiconductor (Si, Ge) → n₀ = p₀ = nᵢ.

• Conductivity: σ = nᵢ e (μₙ + μₚ), where e = electron charge, μₙ, μₚ = mobilities.

• Fermi level (E_F) near mid-gap.

Extrinsic Semiconductors

• N-type: Doped with Group V donors (P, As). Majority carriers = electrons, minority = holes.

  n₀ ≈ Nᴰ (donor concentration), p₀ = nᵢ²/Nᴰ.

• P-type: Doped with Group III acceptors (B, Al). Majority carriers = holes, minority = electrons.

  p₀ ≈ Nᴬ, n₀ = nᵢ²/Nᴬ.

• Temperature Effects:

  • Freeze-out region (very low T): carriers frozen to impurities.

  • Extrinsic region (room T): doped carriers dominate.

  • Intrinsic region (high T): intrinsic carriers dominate (n₀ = p₀ = nᵢ).

Carrier Transport & Calculations

• Conductivity calculation: Given σ, μₚ, find hole concentration p₀ from σ = p₀ e μₚ (if p-type).

• Fermi level position:

  • Intrinsic: E_F = Eᵢ ≈ (E_C + E_V)/2.

  • N-type: E_F moves closer to E_C.

  • P-type: E_F moves closer to E_V.

[!TIP]

Common Pitfall: In extrinsic semiconductors, majority carrier concentration ≈ doping concentration only at room temperature and when doping is much greater than nᵢ.

Exam Focus: Problems on conductivity, carrier concentration, and Fermi level shifts are frequent.

II. PN JUNCTION DIODE & CHARACTERISTICS

Formation & Operation

• Formation: Diffusion of electrons and holes across PN junction → depletion region (ionized donors/acceptors) → built-in potential barrier V_bi.

• Forward Bias: External voltage reduces barrier → minority carrier injection → diffusion current dominates → current increases exponentially.

• Reverse Bias: External voltage increases barrier width → drift current (reverse saturation current I₀) due to minority carriers.

Diode Equation

\boxed{I = I_0 \left( e^{\frac{V}{\eta V_T}} - 1 \right)}

where:

• I₀ = reverse saturation current (≈ μA for Si, μA for Ge)

• V = applied voltage

• η = emission coefficient (η=1 for low current, η=2 for high current in Si; η=1 for Ge)

• V_T = thermal voltage = kT/q ≈ 26 mV at 300 K

V-I Characteristics

• Forward: Cut-in voltage V_γ (~0.7 V Si, 0.3 V Ge). Dynamic resistance: r_d = ηV_T / I_D.

• Reverse: Reverse saturation current I₀ (nearly constant until breakdown).

  Breakdown Mechanisms:

  • Zener Breakdown: Heavy doping → narrow depletion region → high electric field → electron tunneling. Occurs at V_Z < 5 V. Negative temperature coefficient.

  • Avalanche Breakdown: Light doping → wide depletion region → carrier multiplication via impact ionization. Occurs at V_Z > 5 V. Positive temperature coefficient.

  • Punch-through: In power diodes, depletion region spans entire base → abrupt increase in current.

Temperature Effects

• I₀ ∝ T² e^{-E_g/kT} → increases with temperature (doubles per 10°C).

• V_γ decreases with temperature (~ -2 mV/°C for Si).

Equivalent Circuits

• Ideal Diode Model: Zero resistance in forward bias, infinite in reverse.

• Practical Diode Model: Includes bulk resistance r_B in series.

• Piecewise Linear Model: Approximates forward characteristic with a voltage drop V_γ and resistance r_d.

• Small-Signal Model: r_d = ηV_T / I_D.

• Capacitances:

  • Transition capacitance Cᵗ (depletion capacitance): Cᵗ ∝ 1/√(V_bi - V) for reverse bias.

  • Diffusion capacitance Cᵈ (charge storage): Cᵈ ∝ I_F (forward current).

[!TIP]

Key Formula: Dynamic resistance r_d = ηV_T / I_D → decreases as forward current increases.

Breakdown Distinction: Zener (<5V, tunneling, negative temp coeff), Avalanche (>5V, impact ionization, positive temp coeff).

III. SPECIAL PURPOSE DIODES

Zener Diode Details

• Voltage Regulator (Shunt): Zener in parallel with load. Series resistor R limits current.

  \boxed{V_Z = \text{constant}} for variations in I_Z within operating range.

• Temperature Coefficient:

  ΔV_Z = α ΔT, where α is temp coeff (mV/°C). For V_Z < 5 V, α negative; for V_Z > 5 V, α positive.

• Series Regulator: Pass transistor added to improve current handling.

Tunnel Diode

• Sufficient Conditions for Tunneling:

  1. Heavy doping (N_D, N_A > 10¹⁹ cm⁻³).

  2. Narrow depletion region (~10 nm).

• Negative Resistance: Due to tunneling; used in high-speed circuits.

Varactor Diode

• C-V Relationship: C ∝ 1/(V_R + V_bi)^n, where n depends on doping profile (n=0.5 for abrupt junction).

• Applications: Voltage-controlled oscillators (VCO), parametric amplifiers.

Schottky Diode

• Advantages: Low forward voltage, fast switching (no minority carrier storage), low reverse recovery time.

• Disadvantages: Higher reverse leakage, lower breakdown voltage.

[!TIP]

Zener Temp Coeff Calculation: Given V_Z at two temperatures, α = (V_Z2 - V_Z1)/(T₂ - T₁).

Varactor Use: Reverse bias voltage controls capacitance → frequency tuning in LC circuits.

IV. RECTIFIERS & FILTER CIRCUITS

Half-Wave Rectifier (HWR)

• Circuit: Single diode, transformer (optional).

• Operation: Conducts only during positive half-cycle.

• Derived Parameters (for ideal diode, no filter):

  \boxed{V_{dc} = \frac{V_m}{\pi}}

  \boxed{V_{rms} = \frac{V_m}{2}}

  \boxed{r = \frac{V_{rms(ac)}}{V_{dc}} = 1.21}

  \boxed{\eta = \frac{P_{dc}}{P_{ac}} = 40.6%}

  PIV = V_m

  Transformer Utilization Factor (TUF) = 0.287

Full-Wave Rectifiers

• Center-Tapped (CT-FWR):

  • Uses center-tapped transformer and two diodes.

  • V_dc = 2V_m/π, r = 0.482, η = 81.2%.

  • PIV = 2V_m.

• Bridge FWR:

  • Four diodes in bridge configuration.

  • V_dc = 2V_m/π, r = 0.482, η = 81.2%.

  • PIV = V_m.

  • TUF = 0.81 (higher than CT-FWR).

Filter Circuits

• Capacitor Filter (C-filter):

  • Capacitor across load → charges at peak, discharges between peaks.

  • Ripple factor (HWR): \boxed{r \approx \frac{1}{2\sqrt{3} f C R_L}}

    (FWR: r ≈ 1/(4√3 f² L C R_L) for L-section? Actually for capacitor filter alone, FWR: r = 1/(2√3 f C R_L)? Wait: for FWR with capacitor filter, discharge time = 1/(2f), so ΔV = I_dc/(2f C), r = ΔV/(√3 V_dc) = 1/(2√3 f C R_L). But for HWR, r = 1/(√3 f C R_L).)

  • PIV (HWR) = V_m, (FWR) = 2V_m (CT) or V_m (Bridge).

• L-Section Filter (Choke Input):

  • Inductor in series, capacitor in parallel with load.

  • For FWR with L-section: \boxed{r \approx \frac{R_L}{2\sqrt{3} f L}} (assuming large C).

• π-Section Filter: C-L-C → better ripple rejection.

Transformer Rating

• To deliver DC power P_dc:

  • HWR: VA = \frac{\pi^2}{2} P_{dc} ≈ 4.93 P_{dc}

  • FWR: VA = \frac{\pi^2}{8} P_{dc} ≈ 1.23 P_{dc}

Voltage Regulators

• Shunt Regulator: Zener diode in parallel with load. Simple but wasteful.

• Series Regulator: Pass transistor in series with load → better current handling.

• IC Regulators: 78xx (positive), 79xx (negative) → fixed output; LM317 (adjustable).

[!TIP]

Rectifier Comparison: Bridge FWR is preferred over CT-FWR due to lower PIV and no center tap.

Filter Design: For specified ripple and load current, choose C from r = 1/(2√3 f C R_L) (HWR) or r = 1/(2√3 f C R_L) (FWR capacitor filter).

Transformer VA: Always higher than DC power due to pulsating nature.

V. BIPOLAR JUNCTION TRANSISTOR (BJT)

Construction & Types

• NPN/PNP: Three regions: Emitter (heavily doped), Base (lightly doped, thin), Collector (moderately doped).

• Doping: N_E >> N_B, N_C.

Principle of Operation

• Active Mode: E-B junction forward biased, C-B junction reverse biased.

• Current Components:

  • I_E = I_E₀ + I_{ES} (emitter current)

  • I_C = I_C₀ + α I_{ES} (collector current)

  • I_B = I_E - I_C

• Current Gains:

  • α (common-base) = I_C / I_E (0.95–0.99)

  • β (common-emitter) = I_C / I_B (20–500)

  • Relationship: \boxed{\beta = \frac{\alpha}{1-\alpha}}

Configurations & Characteristics

• CE Regions:

  • Cut-off: Both junctions reverse biased → I_C ≈ 0.

  • Active: E-B forward, C-B reverse → amplification.

  • Saturation: Both forward biased → V_CE(sat) ≈ 0.2 V.

Biasing & Stabilization

• Need: Establish stable Q-point (I_CQ, V_CEQ) against temperature and β variations.

• Biasing Circuits:

  • Fixed Bias: Simple but poor stability. Stability factor S = 1 + β (high).

  • Self-Bias (Emitter Bias): R_E provides negative feedback. S' ≈ 1 + β/(1 + R_E/R_B) (improved).

  • Voltage Divider Bias: Thevenin equivalent: V_B = V_Th R₂/(R₁+R₂), R_Th = R₁//R₂.

    Stability factor S ≈ 1 + (R_Th/R_E) if R_E >> R_Th/β → excellent stability (S ≈ 1).

• Thermal Runaway: Increase in T → I_CO ↑, β ↑ → I_C ↑ → more power dissipation → further T ↑. Prevent by:

  • Emitter resistor R_E (stabilization).

  • Heat sinking.

  • Voltage divider bias.

Amplifier Analysis

• DC Load Line: From V_CC = I_C R_C + V_CE (with R_E included if present).

• AC Load Line: Slope = -1/R_L', where R_L' = R_C // R_L (if no R_E) or R_C // R_L with R_E bypassed? Actually, with emitter resistor partially bypassed, AC load line slope depends on bypass capacitor.

• Q-point: Intersection of DC load line and transistor characteristic.

• Small-Signal h-Parameter Model (CE):

  • Input: v_be = h_ie i_b + h_re v_ce

  • Output: i_c = h_fe i_b + h_oe v_ce

  • Mid-frequency voltage gain: \boxed{A_v = -h_{fe} \frac{R_L'}{h_{ie}}}

  • Input impedance: Z_in = h_ie

  • Output impedance: Z_out = 1/h_oe (≈ r_o)

• Hybrid-π Model: For high-frequency analysis: g_m = I_C/V_T, r_π = β/g_m, r_o = V_A/I_C.

BJT as Switch

• Cut-off (OFF): V_CE ≈ V_CC, I_C ≈ 0.

• Saturation (ON): V_CE ≈ V_CE(sat) (~0.2 V), I_C = (V_CC - V_CE(sat))/R_C.

• Base Resistor Design: For saturation, ensure I_B > I_C/β_min.

[!TIP]

Stability Factor: Lower S → better stability. Voltage divider bias gives S ≈ 1.

h-Parameters: From CE characteristics: h_ie = ΔV_BE/ΔI_B at constant V_CE; h_fe = ΔI_C/ΔI_B at constant V_CE.

Common Pitfall: In CE amplifier, if emitter resistor is not fully bypassed, gain reduces and input impedance increases.

VI. FIELD EFFECT TRANSISTORS (FETs)

JFET

• Construction: N-channel/P-channel. Gate forms reverse-biased PN junction with channel.

• Operation: V_GS controls depletion width → controls I_D.

• Pinch-off Voltage (V_P): V_GS at which channel closes (negative for N-channel). Saturation occurs at V_DS = |V_P|.

• Shockley’s Equation (for saturation region):

  \boxed{I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2}

  where I_DSS = drain current at V_GS = 0.

• Characteristics:

  • Transfer: I_D vs V_GS (parabolic).

  • Drain: I_D vs V_DS (ohmic, saturation, breakdown).

• Parameters:

  • Transconductance: \boxed{g_m = \frac{dI_D}{dV_{GS}} = \frac{2I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right)}

    At V_GS = 0: g_{m0} = 2I_{DSS}/|V_P|.

  • Drain-source resistance: r_{ds} = 1/g_m.

MOSFET

• Types:

  • Enhancement Mode: Normally OFF; requires V_GS > V_th (N-channel) to form channel.

  • Depletion Mode: Normally ON; V_GS can deplete channel.

• Operation Regions:

  • Cut-off: V_GS < V_th (enhancement) or V_GS < V_P (depletion).

  • Linear/Ohmic: V_DS small → behaves like resistor.

  • Saturation: V_DS ≥ V_GS - V_th (enhancement) or V_DS ≥ |V_P| (depletion).

• Saturation Current (enhancement): I_D = k (V_GS - V_th)², where k = μ_n C_ox (W/L)/2.

• Small-Signal Model: Similar to JFET but with different parameters.

FET Amplifiers

• Common Source (CS): Voltage gain A_v = -g_m R_D' (phase inversion). High voltage gain.

• Common Drain (CD / Source Follower): A_v ≈ 1, high input Z, low output Z.

• Common Gate (CG): A_v = g_m R_D, low input Z, high output Z.

FET Biasing

• Voltage Divider Self-Bias: Provides stable Q-point.

  V_GS = -I_D R_S (for N-channel), solve with Shockley’s equation.

• Design: Choose R_S and R_D to set I_DQ and V_DSQ.

[!TIP]

FET as Voltage-Controlled Device: High input impedance (gate junction reverse-biased) → voltage-controlled current source.

JFET Parameters: Given I_DSS and V_P, find I_D at any V_GS using Shockley’s equation.

MOSFET Threshold: V_th is minimum V_GS to create channel (enhancement).

VII. OTHER SEMICONDUCTOR DEVICES

Unijunction Transistor (UJT)

• Construction: N-type bar with P-type emitter at one end. Terminals: Emitter (E), Base1 (B1), Base2 (B2).

• Characteristics: I_E vs V_E shows negative resistance region after peak point.

• Intrinsic Stand-off Ratio: η = R_B1/(R_B1+R_B2) (typically 0.5–0.8).

• Relaxation Oscillator:

  • Circuit: UJT with R, C, and supply.

  • Frequency: \boxed{f = \frac{1}{R C \ln\left(\frac{1}{1-\eta}\right)}}

Thyristor (SCR)

• Construction: PNPN four-layer, three terminals: Anode (A), Cathode (K), Gate (G).

• Operation: Two-transistor analogy (PNP and NPN). Latching: once ON, stays ON until current < holding current.

• V-I Characteristics:

  • Forward blocking: J1, J3 reverse biased, J2 forward → low current until breakover.

  • Forward conducting: After triggering, low voltage drop (~1 V).

  • Reverse blocking: Similar to diode.

• Turn-on Methods: Gate triggering, forward voltage (breakover), dV/dt, temperature.

• Applications: Power control, motor speed control, inverters.

Photo Transistor

• Construction: Base exposed to light → photocurrent in base-emitter junction.

• Operation: Light generates electron-hole pairs in base → increases I_B → I_C = β I_B.

• Characteristics: I_C vs light intensity (linear).

• Applications: Light detection, opto-couplers, switching.

[!TIP]

UJT Oscillator: Frequency inversely proportional to RC and depends on η.

SCR Triggering: Gate current required to turn ON; once ON, gate loses control.

Photo Transistor: Higher sensitivity than photodiode due to current gain β.

VIII. AMPLIFIERS - CLASSIFICATION & MULTISTAGE

Power Amplifier Classes

Push-Pull Amplifier

• Circuit: Two transistors (complementary or transformer-coupled) → each conducts for half cycle.

• Advantages: Eliminates even harmonics, reduces crossover distortion (in Class AB).

• Applications: Audio power output stages.

Darlington Amplifier

• Circuit: Two transistors connected emitter-base → overall β_D ≈ β₁β₂.

• Characteristics: Very high input impedance, high current gain, V_BE drop ≈ 1.4 V.

• Applications: Driver stages, high-impedance sources.

Cascode Amplifier

• Circuit: CE stage followed by CB stage.

• Advantages: High bandwidth (reduced Miller effect), high output impedance, good isolation.

Coupling Methods

• RC Coupling: Capacitor coupling → blocks DC, good for audio. Disadvantage: poor low-frequency response.

• Transformer Coupling: Impedance matching, no DC shift. Disadvantage: bulky, frequency-sensitive.

• Direct Coupling: Direct connection → good for DC/low-frequency. Disadvantage: Q-point drift, used in ICs.

Frequency Response

• Low Frequency: Limited by coupling and bypass capacitors → lower cut-off frequency f_L.

• High Frequency: Limited by internal capacitances (Miller effect) → upper cut-off frequency f_H.

• Bandwidth: BW = f_H - f_L.

[!TIP]

Class Choice: Class A for low distortion, Class B/AB for efficiency in power stages.

Miller Effect: In CE amplifier, C_cb multiplied by (1 + A_v) → reduces f_H. Cascode minimizes this.

Coupling: RC coupling most common in multi-stage audio amplifiers.

IX. ADVANCED MODELS & CIRCUIT TECHNIQUES

Transistor Models

• Ebers-Moll Model: Two-diode representation. Equations:

  I_E = I_{ES} (e^{V_{BE}/V_T} - 1) - α_R I_{CS} (e^{V_{BC}/V_T} - 1)

  I_C = α_F I_{ES} (e^{V_{BE}/V_T} - 1) - I_{CS} (e^{V_{BC}/V_T} - 1)

• Hybrid-π Model: Small-signal high-frequency model:

  • g_m = I_C / V_T

  • r_π = β / g_m

  • r_o = V_A / I_C (Early effect)

Current Mirror

• Basic Circuit: Two transistors with emitters (or sources) connected. Reference current I_REF sets mirror current I_OUT = I_REF (if matched).

• Operation: Q1 diode-connected → V_BE sets current. Q2 mirrors current.

• Applications: Biasing in IC amplifiers (differential pairs), active loads.

Bootstrapping

• Need: Increase input impedance of amplifier (e.g., CE with emitter resistor).

• Principle: Feedback of output signal to input via capacitor → bootstraps bias network → appears as high impedance.

• Circuit: Capacitor from output to input resistor network.

Bias Stabilization Techniques

• Stability Factor (S): S = ΔI_C/ΔI_CO (with V_BE constant). Lower S → better stability.

• Methods:

  • Emitter resistor R_E (most effective).

  • Voltage divider bias.

  • Balanced bridge, thermistor/sensistor for temperature compensation.

[!TIP]

Current Mirror: Used in integrated circuits to generate stable bias currents.

Bootstrapping: Used in common-emitter amplifiers with emitter resistor to increase effective input resistance.

Stability: Voltage divider bias with R_E gives S ≈ 1 + (R_Th/R_E) → choose R_E large for good stability.

X. PRACTICAL DESIGN & PROBLEM-SOLVING

Rectifier Design

• Transformer Secondary Voltage: For desired V_dc, V_m = π V_dc (HWR) or V_m = π V_dc/2 (FWR).

• PIV: HWR: V_m; CT-FWR: 2V_m; Bridge: V_m.

• Filter Design: For capacitor filter, C = 1/(2√3 f r V_dc) (HWR) or C = 1/(2√3 f r V_dc) (FWR)? Actually, from r = 1/(2√3 f C R_L) for FWR capacitor filter, so C = 1/(2√3 f r R_L). But R_L = V_dc/I_dc. So C = I_dc/(2√3 f r V_dc).

• Transformer VA: VA = (π²/2) P_dc (HWR) or (π²/8) P_dc (FWR).

Bias Circuit Design

• Voltage Divider: Choose R₁, R₂ to set V_B with minimal loading. Then R_E for stability, R_C for desired V_CEQ.

• Fixed Bias: R_B = (V_CC - V_BE)/I_B, with I_B = I_C/β.

• Specify R_B for V_CE: From V_CE = V_CC - I_C R_C, and I_C = β (V_CC - V_BE - I_E R_E)/[R_B + (β+1)R_E] → solve for R_B.

Amplifier Analysis

• CE Amplifier Gain: A_v = -g_m R_L' (using hybrid-π) or -h_fe R_L'/h_ie.

• Lower Cut-off Frequency f_L: Due to coupling/bypass caps: f_L = 1/(2π C_eq R_in) or similar.

• Finding h-parameters: From characteristic curves:

  h_ie = ΔV_BE/ΔI_B at constant V_CE.

  h_fe = ΔI_C/ΔI_B at constant V_CE.

FET Parameter Calculations

• I_D and g_m: Use Shockley’s equation and derivative.

• r_ds: r_ds = 1/g_m.

Temperature & Breakdown Problems

• Zener Temp Coeff: α = (ΔV_Z)/(ΔT).

• Diode Current: Use diode equation I = I₀ (e^{V/(ηV_T)} - 1) at different V.

[!TIP]

Design Tip: In voltage divider bias, choose R₁//R₂ << β R_E to ensure stability.

Rectifier Design: Always check PIV rating of diodes.

Amplifier Gain: With emitter resistor partially bypassed, gain = -R_C'/r_e, where R_C' = R_C//R_L and r_e = 26mV/I_E.

Final Note: This summary covers all high-frequency topics from past papers. Focus on derivations (diode equation, rectifier parameters, BJT current equation, JFET Shockley’s equation) and numerical problems (conductivity, bias design, amplifier gain, ripple factor). Use boxed formulas for quick revision.