UNIT 5: Digital Circuits and Systems - Short Notes (RGPV Focus)

1. Number Systems and Base Conversions

Definition: A number system uses a base (radix) r with digits 0 to r-1. Positional value = digit × r^position.

Conversion Methods:

• Integer Part (Base r to Decimal): Sum of digit × r^position (position from right, starting 0).

• Fractional Part (Base r to Decimal): Sum of digit × r^{-position} (position from left after point, starting 1).

• Decimal to Base r (Integer): Repeated division by r, remainders read bottom to top.

• Decimal to Base r (Fractional): Repeated multiplication by r, integer parts read top to bottom.

• Between Non-Decimal Bases: Convert via decimal as intermediate (or direct grouping for powers of 2).

[!TIP] Common Pitfall: For fractional conversions, multiplication may not terminate. Stop after desired precision or when remainder repeats.

Binary Coded Decimal (BCD)

• Definition: 4-bit binary representation of each decimal digit (0–9). Valid codes: 0000 to 1001. 1010–1111 are invalid.

• Conversion: Write each decimal digit as its 4-bit binary equivalent. Example: $$\displaystyle (25)_{10} = (0010\ 0101)_{BCD} $$.

2. Code Converters

BCD to Excess-3 Code

• Excess-3: BCD + 3 (0011). For digit D, code = D + 3.

• Truth Table (Partial):

• Logic Equations (2-level implementation):

  • $$\displaystyle W = A + BD + BC $$

  • $$\displaystyle X = B'C + B'D + BC'D' $$

  • $$\displaystyle Y = C'D + CD' $$

  • $$\displaystyle Z = D' $$

Binary to Gray Code Converter

• Gray Code: Only one bit changes between consecutive numbers. MSB same as binary. Next bit = XOR of current binary bit and previous binary bit.

• Conversion (Binary $$\displaystyle B_3 B_2 B_1 B_0 $$ → Gray $$\displaystyle G_3 G_2 G_1 G_0 $$):

  • $$\displaystyle G_3 = B_3 $$

  • $$\displaystyle G_2 = B_3 \oplus B_2 $$

  • $$\displaystyle G_1 = B_2 \oplus B_1 $$

  • $$\displaystyle G_0 = B_1 \oplus B_0 $$

• Logic Diagram: XOR gates in cascade.

1's Complement Generator

• Operation: Invert all bits of input binary number.

• Implementation: Use NOT gates on each input line. For n-bit input, need n NOT gates.

3. Boolean Algebra and Minimization

Key Laws & Theorems

Karnaugh Map (K-map) Minimization

• Procedure:

  1. Plot minterms (for SOP) or maxterms (for POS) on K-map.

  2. Form largest possible groups of 1s (SOP) or 0s (POS) in powers of 2 (1,2,4,8,...).

  3. Groups can overlap; include all 1s/0s.

  4. Write product term for each group: variable = 1 → uncomplemented; = 0 → complemented; absent → eliminated.

  5. Combine terms for minimal expression.

• Goal: Obtain minimal SOP or minimal POS.

4. Combinational Logic Design

Encoders

• 8-to-3 Line Encoder: 8 inputs ($$\displaystyle I_0 $$–$$\displaystyle I_7 $$), 3 outputs ($$\displaystyle A_2 A_1 A_0 $$). Active-high inputs. Output = binary code of active input line.

  • Truth Table:

• Logic: $$\displaystyle A_2 = I_4 + I_5 + I_6 + I_7 $$, etc. (OR of relevant inputs).

• Priority Encoder: If multiple inputs active, output code of highest-priority input. Include valid (V) output (0 if no input active) and group signal (GS) for cascading.

Decoders

• n-to-2ⁿ Decoder: n inputs, 2^n outputs. Each output = minterm of inputs. Active-high or active-low.

• Full Adder using Decoder (3-to-8):

  • Use inputs $$\displaystyle A, B, C_{in} $$ to decoder.

  • Outputs $$\displaystyle m_1, m_2, m_4, m_7 $$ correspond to sum = 1 (minterms 1,2,4,7). Sum = OR of these outputs.

  • $$\displaystyle C_{out} = m_3 + m_5 + m_6 + m_7 $$.

Multiplexers (MUX) & Demultiplexers (DEMUX)

• MUX: 2^n data inputs, n select lines, 1 output. $$\displaystyle Y = \sum_{i=0}^{2^n-1} D_i \cdot \prod_{j=0}^{n-1} (S_j^{i_j}) $$ where $$\displaystyle S_j^{i_j} $$ is $$\displaystyle S_j $$ if $$\displaystyle i_j=1 $$, else $$\displaystyle S_j' $$.

• Implementing Boolean Functions: Use MUX with select lines as some variables. Data inputs = function values for all combinations of select variables.

  • Example (4×1 MUX, F(A,B,C,D) = Σ(0,3,5,6,8,9,11,13,15), S₁=A, S₀=C): For each combination of A,C, treat B,D as data inputs. Use external gates if needed to combine multiple minterms into one data input.

• DEMUX: 1 input, n select lines, 2^n outputs. Routes input to selected output line.

Adders & Subtractors

• Half Adder (HA): 2 inputs (A,B), outputs Sum (S) and Carry (C).

  • $$\displaystyle S = A \oplus B $$, $$\displaystyle C = A \cdot B $$.

• Full Adder (FA): 3 inputs (A,B,Cin), outputs S, Cout.

  • $$\displaystyle S = A \oplus B \oplus C_{in} $$

  • $$\displaystyle C_{out} = AB + BC_{in} + AC_{in} $$

  • Using Decoder: As above.

  • Using NAND Only: Implement XOR using NANDs: $$\displaystyle A \oplus B = (A \cdot (A \cdot B)')' + (B \cdot (A \cdot B)')' $$.

• Half Subtractor (HS): Inputs A,B; outputs Difference (D) and Borrow (B_out).

  • $$\displaystyle D = A \oplus B $$, $$\displaystyle B_{out} = A'B $$.

• Full Subtractor (FS): Inputs A,B,B_in; outputs D, B_out.

  • $$\displaystyle D = A \oplus B \oplus B_{in} $$

  • $$\displaystyle B_{out} = A'B + (A \oplus B)'B_{in} $$

  • Using HS: $$\displaystyle D = HS_1(A,B) \oplus B_{in} $$; $$\displaystyle B_{out} = (A'B) + (B_{out,HS1} \cdot B_{in}) $$.

Universal Gates (NAND/NOR)

• NAND Realization:

  • NOT: $$\displaystyle A' = A \uparrow A $$

  • AND: $$\displaystyle AB = (A \uparrow B)' = (A \uparrow B) \uparrow (A \uparrow B) $$

  • OR: $$\displaystyle A+B = (A' \cdot B')' = (A \uparrow A) \uparrow (B \uparrow B) $$

• NOR Realization:

  • NOT: $$\displaystyle A' = A \downarrow A $$

  • OR: $$\displaystyle A+B = A \downarrow B $$

  • AND: $$\displaystyle AB = (A'+B')' = (A \downarrow A) \downarrow (B \downarrow B) $$

• Any Boolean Function: Convert to SOP/POS, then replace gates with NAND/NOR equivalents (add inverters where needed).

5. Sequential Logic Circuits

Flip-Flops

[!TIP] Excitation Table: Lists required inputs (J,K,T,D) to go from current Qₙ to next Qₙ₊₁. Derived from characteristic equation.

Flip-Flop Conversion: D to JK

• Logic: Use D FF with combinational inputs. $$\displaystyle D = JQ_n' + K'Q_n $$.

• Implementation: Use NAND gates to realize $$\displaystyle JQ_n' + K'Q_n $$.

• Steps: Derive D's truth table from JK excitation table → K-map for D → logic equation → NAND implementation.

Counters

• Asynchronous (Ripple): FF outputs clock next FF. Cascading T FFs for binary up/down. MOD = 2ⁿ for n FFs.

  • MOD-4 Down Counter (T FFs): T inputs = 1 (toggle). Clock: FF0 from external clock, FF1 from Q₀', FF2 from Q₁', etc. For down, use Q outputs to clock next FF (or invert clock direction).

• Synchronous Counter: All FFs clocked simultaneously. Design steps:

  1. Draw state diagram / sequence.

  2. State table (present state → next state).

  3. Excitation table (add J,K for each FF).

  4. K-maps for each J,K input as function of present states.

  5. Minimal logic equations → circuit.

• MOD Counter: Counts M states (0 to M-1). Reset when state = M. Use NAND of relevant state bits to clear FFs (async or sync reset).

• Ring Counter: n FF in circular shift. Single '1' circulates. MOD = n. Requires initial preset.

• Johnson (Twisted Ring) Counter: Inverted output of last FF fed to input of first. MOD = 2n. Sequence: n zeros → n ones → n zeros... Self-decoding.

Shift Registers

• Universal Shift Register (4-bit): Mode control $$\displaystyle S_1 S_0 $$:

  • 00: Hold (no shift)

  • 01: Shift Right (serial input $$\displaystyle I_{SR} $$)

  • 10: Shift Left (serial input $$\displaystyle I_{SL} $$)

  • 11: Parallel Load

• Logic: Use 4:1 MUX before each D input of FFs. Select lines = $$\displaystyle S_1, S_0 $$. MUX inputs: parallel data bit, left neighbor (Q₃ for left shift), right neighbor (Q₀ for right shift), current Q (hold).

• Types:

  • SISO: Serial In → Serial Out (shift only).

  • SIPO: Serial In → Parallel Out (shift, parallel read).

  • PISO: Parallel In → Serial Out (load, then shift).

  • PIPO: Parallel In → Parallel Out (load only).

• Applications: Data storage, serial-to-parallel conversion, parallel-to-serial conversion, time delay, ring counters.

6. Logic Families

TTL (Transistor-Transistor Logic)

• Basic 2-input NAND (Totem-Pole Output):

  • Circuit: Multi-emitter input transistor → phase splitter → totem-pole (pull-up transistor + pull-down transistor).

  • Operation: Inputs high → current flows into multi-emitter → phase splitter saturates → output low (pull-down on). Inputs low → phase splitter off → pull-up on → output high.

  • Totem-Pole: Reduces power dissipation in steady state vs open-collector.

• TTL NOR Gate: Uses multi-emitter input with different transistor arrangement. Output = $(A+B)'$.

• Characteristics:

  • Propagation Delay: ~10 ns (moderate).

  • Power Dissipation: ~10 mW/gate (higher).

  • Fan-out: ~10 (good).

  • Noise Margin: Low (~0.4V).

CMOS (Complementary MOS)

• 2-input NAND: Series pMOS network (for pull-up) + parallel nMOS network (for pull-down). Inputs control gates.

  • Operation: Both inputs high → nMOS on, pMOS off → output low. Any input low → corresponding pMOS on, nMOS off → output high.

• 2-input NOR: Parallel pMOS + series nMOS.

• Characteristics:

  • Propagation Delay: Higher than TTL (~20-50 ns), but improves with technology.

  • Power Dissipation: Very low (static ~nW, dynamic ∝ frequency).

  • Fan-out: Very high (>50).

  • Noise Margin: High (~1.5V).

Comparative Analysis

[!TIP] Remember: CMOS = low power, high fan-out, slower; TTL = faster, more power; ECL = fastest, most power.

RTL vs DTL

• RTL (Resistor-Transistor Logic): Inputs via resistors to base of transistor. Simple but high power, low fan-out, poor noise margin.

• DTL (Diode-Transistor Logic): Diodes form AND at input, then transistor inverts. Better than RTL but still diode voltage drops limit noise margin and speed.

7. Display and Interfacing Devices

7-Segment LED Display

• Segments: a, b, c, d, e, f, g (and often dp).

• Common Anode (CA): All anodes connected to Vcc. Segment lights with 0 (sink current).

• Common Cathode (CC): All cathodes to GND. Segment lights with 1 (source current).

• Driving: Use decoder/driver IC (e.g., 7447 for BCD to CA display). 7447 outputs active-low (0 lights segment for CA).

• Truth Table (7447 for BCD inputs):

LCD (Liquid Crystal Display)

• Operation Principle: Liquid crystal between polarizers. Voltage applied → crystals twist → light passes/blocked. Requires AC drive (to prevent electrolysis).

• Advantages over LED: Very low power (µW), no backlight needed in reflective mode, easy on eyes.

• Disadvantages: Slow response (ms), narrow viewing angle, requires driver IC (e.g., LCD segment driver), temperature sensitive.

• Comparison:

  | Feature | LED | LCD | | :--- | :--- | :--- | | Power | Higher (mA) | Very Low (µA) | | Brightness | High | Low (needs backlight for dark) | | Viewing Angle | Wide | Narrow | | Response | Fast (ns) | Slow (ms) | | Cost | Low | Moderate-High |

8. Data Conversion Circuits

Analog-to-Digital Converters (ADCs)

• Flash (Parallel) ADC:

  • Circuit: $$\displaystyle 2^n - 1 $$ comparators (for n-bit), priority encoder, reference ladder.

  • Operation: Each comparator compares input with reference voltage. Encoder outputs binary code of highest comparator that goes high.

  • Advantages: Fastest (single clock cycle).

  • Disadvantages: Expensive, power-hungry, components double for each bit (exponential).

• Successive Approximation ADC (SAR):

  • Block Diagram: Comparator, SAR register, DAC, control logic.

  • Operation:

    1. SAR sets MSB = 1, others 0 → DAC voltage.

    2. Compare with input. If DAC < input, keep MSB=1; else clear.

    3. Repeat for next bit (MSB-1, etc.) down to LSB.

    4. After n cycles, SAR holds digital output.

  • Advantages: Moderate speed, good accuracy, single comparator.

  • Disadvantages: Slower than flash (n clock cycles).

9. Special Purpose Circuits

Schmitt Trigger

• Circuit: Op-amp with positive feedback (hysteresis) or logic gate version (e.g., NAND with feedback).

• Operation: Two threshold voltages: UTP (upper) and LTP (lower). Output switches high when input > UTP, low when input < LTP. Prevents noise-induced switching.

• Applications: Noise-immune comparator, square wave generator, debouncing.

Astable Multivibrator (using NAND gates)

• Circuit: Two NAND gates in cross-coupled configuration with RC feedback.

• Operation: Capacitor charges/discharges through R. Outputs toggle when capacitor voltage crosses threshold. Frequency: $$\displaystyle f \approx \frac{1}{1.4 RC} $$ (for 50% duty cycle, equal R,C).

• Waveform: Square wave output, capacitor voltage sawtooth.

10. Definitions & Key Parameters

• Fan-in: Number of inputs a gate can handle.

• Fan-out: Number of similar gates a gate output can drive without degradation.

• Propagation Delay ($$\displaystyle t_{pd} $$): Average time for input change to reflect at output.

• Power Dissipation: Average power consumed (static + dynamic). $$\displaystyle P = V_{CC} \cdot I_{CC} $$.

• Noise Margin: Maximum noise voltage that can be tolerated without false output.

  • $$\displaystyle NM_H = V_{OH(min)} - V_{IH(min)} $$

  • $$\displaystyle NM_L = V_{IL(max)} - V_{OL(max)} $$

• Hysteresis: Difference between UTP and LTP in Schmitt trigger. Provides noise immunity.

\boxed{\text{Exam Focus Summary}}

• High Frequency: Number conversions (incl. fractional, non-standard bases), BCD/Excess-3, Gray code, K-map (2-4 vars), MUX implementation, Full adder/subtractor designs, Flip-flop conversions, Synchronous counter design (state sequence), Universal shift register, TTL vs CMOS comparison, ADC (Flash/SAR), 7-segment display.

• Must Practice: Excitation tables for flip-flop conversions, K-map grouping rules, synchronous counter design steps (state table → excitation → K-map → equations), totem-pole TTL operation, CMOS gate structure.

• Common Pitfalls: Invalid BCD codes, K-map wrap-around groups, asynchronous ripple counter delays, excitation table derivation, MOD counter reset logic, CMOS power vs TTL misconception.