IT-305 Digital Circuits and Systems - Dec 2024 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aConvert: i) $(11011.11)_2 = (\ )_{10}$ ii) $(7825.6875) = (\ )_8$ iii) $(125.89)_{10} = (\ )_{\text{BCD}}$ iv) $(111011)_2 = (\ )_5$
   How to answer

   • Evaluate integer and fractional powers of 2 for binary to decimal conversion
   • Convert integer by repeated division by 8 and fractional part by repeated multiplication by 8
   • Convert each decimal digit into its 4-bit 8421 BCD representation
   • Convert binary integer to decimal, then convert decimal to base-5 by successive division by 5
2. 7 Marks
   bMinimize the following expression using K-map. $$f(P, Q, R, S) = \Sigma m(0, 1, 4, 5, 7, 8, 9, 12, 13, 15)$$
   How to answer

   • Plot given minterms on a 4-variable (4x4) Karnaugh map with variables P, Q, R, S
   • Form prime implicants/groups: an octet of columns 00 and 01 (R'S' + R'S = R') giving R', and a quad for minterms {5, 7, 13, 15} giving QS
   • Write minimal SOP form: f = R' + QS
3. 7 Marks
   aSimplify the Boolean expression using laws and rules of Boolean algebra. State laws used in each step. i) $Z = A + A'B + A'B'C + A'B'C'D$ ii) $A'B + B'C + AB' + B$
   How to answer

   • For part i: Use rule $X + X'Y = X + Y$ successively: $A + A'B = A + B$, then $(A + B) + A'B'C = A + B + C$, then $(A + B + C) + A'B'C'D = A + B + C + D$
   • For part ii: Combine $A'B + B = B(A' + 1) = B$, then simplify $B + AB' + B'C$: $B + AB' = B + A$, then $A + B + B'C = A + B + C$
   • Explicitly state each Boolean law used at each step (Distributive, Annulment, Identity, Complement)
4. 7 Marks
   bObtain the truth table of the following and implement it by using NAND Gates. $$F(A,B,C,D) = (AB + BC)(AC + BC)$$
   How to answer

   • Simplify the Boolean expression: $(AB + BC)(AC + BC) = B(A + C) \cdot C(A + B) = BC(A + C)(A + B) = BC(A + BC) = ABC + BC = BC$
   • Construct the 16-row truth table for 4 inputs A, B, C, D showing output F = 1 whenever B=1 and C=1
   • Express $F = BC$ in terms of NAND operations: $F = \overline{\overline{BC}}$ using two 2-input NAND gates (one for NAND, one as inverter) or equivalent universal gate implementation
   • Draw the complete circuit schematic using only NAND gates
5. 7 Marks
   aDescribe function of full subtractor circuit with its truth table, K-map simplification and logic diagram
   How to answer

   • Define full subtractor: performs subtraction of three binary bits ($A - B - B_{in}$)
   • Present 8-row truth table with inputs $A, B, B_{in}$ and outputs Difference ($D$) and Borrow Out ($B_{out}$)
   • Provide 3-variable K-maps for Difference and Borrow
   • Derive minimized equations: $D = A \oplus B \oplus B_{in}$ and $B_{out} = A'B + A'B_{in} + BB_{in}$
   • Draw logic diagram using XOR, AND, and OR gates
6. 7 Marks
   bDesign and explain a combinational circuit to convert binary to Gray code.
   How to answer

   • State conversion rules from 4-bit binary ($B_3 B_2 B_1 B_0$) to Gray code ($G_3 G_2 G_1 G_0$)
   • Show truth table for 4-bit binary to Gray converter
   • Derive expressions: $G_3 = B_3$, $G_2 = B_3 \oplus B_2$, $G_1 = B_2 \oplus B_1$, $G_0 = B_1 \oplus B_0$
   • Draw logic diagram using XOR gates
7. 7 Marks
   aDraw RS Flip Flop circuit and explain its operation with truth table. Write some applications of RS Flip Flop.
   How to answer

   • Draw circuit diagram of SR latch / flip-flop using NOR or NAND gates
   • Explain working for all four input combinations: Hold (0,0), Reset (0,1), Set (1,0), and Forbidden/Invalid (1,1) for NOR latch
   • Present the function/truth table and characteristic table
   • List applications: debouncing switches, temporary 1-bit memory storage, latching circuits
8. 7 Marks
   bDesign a synchronous counter using JK flip flop for the following sequence 000, 101, 110, 111, 011, 010, 000.
   How to answer

   • Determine number of flip-flops required: 3 flip-flops ($Q_2, Q_1, Q_0$)
   • State the excitation table for JK flip-flops ($0\to0: 0,X$; $0\to1: 1,X$; $1\to0: X,1$; $1\to1: X,0$)
   • Construct state transition table for present states and next states based on the given sequence, treating unused states 001 and 100 as don't-cares
   • Use K-maps to minimize input equations for $J_2, K_2, J_1, K_1, J_0, K_0$
   • Draw the complete circuit schematic with common clock
9. 7 Marks
   aWhat do you understand by Register? Differentiate between serial and parallel register with the help of appropriate example and diagram.
   How to answer

   • Define register as a group of flip-flops used to store and manipulate binary data
   • Explain serial register (data is loaded/retrieved bit-by-bit sequentially) with a SISO block diagram
   • Explain parallel register (all bits loaded/retrieved simultaneously in a single clock pulse) with a PIPO block diagram
   • Provide comparison table covering speed, number of clock pulses, hardware complexity, and applications
10. 7 Marks
    bCompare TTL and CMOS logic families on the basis of following: i) Propagation delay ii) Power dissipation iii) Fan-out iv) Basic gate
    How to answer

    • Tabulate comparison between TTL and CMOS for each requested parameter:
    • Propagation delay: TTL is faster (~10 ns for standard), CMOS is moderate (~25-50 ns for standard 4000 series, improves with newer families)
    • Power dissipation: TTL has higher static power dissipation (~10 mW/gate), CMOS has extremely low static power dissipation (~nW/gate, increases with frequency)
    • Fan-out: TTL typically around 10, CMOS typically > 50 (up to 100 at low frequencies)
    • Basic gate: TTL basic building block is NAND; CMOS basic building block is NOR/NAND (Inverter/transmission gate)
11. 7 Marks
    aExplain the working of basic totem pole TTL 2 input NAND gate.
    How to answer

    • Draw the circuit diagram of a standard two-input TTL NAND gate with totem-pole output stage (transistors Q1, Q2, Q3, Q4 and diode D)
    • Explain operation when both inputs are HIGH: Q1 reverse active, Q2 ON, Q4 ON (pulling output LOW), Q3 OFF
    • Explain operation when at least one input is LOW: Q1 conducts, Q2 OFF, Q4 OFF, Q3 ON (pulling output HIGH via totem-pole)
    • Highlight the role of totem-pole configuration in reducing output impedance and charging capacitance quickly
12. 7 Marks
    bWhat do you understand by logic family? Give the difference between RTL and DTL logic families.
    How to answer

    • Define logic family: a collection of integrated circuit digital logic gates manufactured using a specific circuit technology and compatible logic levels
    • Explain basic components: RTL uses resistors and transistors; DTL uses diodes and transistors
    • Compare RTL and DTL on noise margin (DTL is better), fan-out (DTL is higher), speed, and power consumption
    • State the basic gate implemented: NOR for RTL, NAND for DTL
13. 7 Marks
    aEnlist the various types of Analog to Digital (A/D) converter and explain any one of them with neat sketch.
    How to answer

    • List types of ADCs: Flash/Parallel comparator ADC, Successive Approximation Register (SAR) ADC, Dual-slope integrating ADC, Counter/Ramp type ADC, Sigma-Delta ADC
    • Select one ADC (e.g., Successive Approximation ADC or Flash ADC) and draw its functional block diagram
    • Explain the operating principle and working steps of the chosen ADC
    • Mention its key advantages and typical conversion time/application
14. 7 Marks
    bDraw the circuit diagram of Schmitt Trigger and explain its working.
    How to answer

    • Draw op-amp or transistor-based inverting/non-inverting Schmitt trigger circuit diagram with positive feedback
    • Define Upper Threshold Point (UTP) and Lower Threshold Point (LTP) with mathematical expressions
    • Explain circuit operation for input transitions above UTP and below LTP
    • Draw the hysteresis loop and input-output transfer characteristic curve
15. 14 Marks
    Write a short note on any two: i) De-Morgan's Theorem ii) Multiplexer and Demultiplexer iii) 7-Segment LED Display iv) Johnson Counter
    How to answer

    • i) De-Morgan's Theorem: State both theorems $\overline{A+B}=\overline{A}\cdot\overline{B}$ and $\overline{A\cdot B}=\overline{A}+\overline{B}$ with truth tables and logic symbol equivalences
    • ii) MUX and DEMUX: Explain data selector (MUX) and data distributor (DEMUX), relationship between select lines and data lines, with basic block diagrams
    • iii) 7-Segment LED Display: Describe common anode and common cathode configurations, segment layout (a-g), and BCD-to-7-segment decoder interface
    • iv) Johnson Counter: Explain working of n-bit inverted feedback ring counter, count states ($2n$ states), state sequence, and timing diagram