UNIT 4: Digital Circuits and Systems - Short Notes

Based on analysis of RGPV past papers (Dec 2023, Dec 2024, Jun 2023).

I. NUMBER SYSTEMS & CODES

Number System Conversions

• Integer Part: Repeated division by new base (for fractional part, repeated multiplication).

• Fractional Part: Repeated multiplication by new base; carry integer part to result.

• Base Conversion Formula (General): For a number $$\displaystyle N = d_{n-1}d_{n-2}...d_0.d_{-1}...d_{-m} $$ in base $b$:

$$N_{10} = \sum_{i=0}^{n-1} d_i \cdot b^i + \sum_{j=1}^{m} d_{-j} \cdot b^{-j}$$

• Shortcut: Binary ↔ Octal (3 bits), Binary ↔ Hex (4 bits).

[!TIP] Common Pitfall: Forgetting to multiply fractional digits by $$\displaystyle b^{-1}, b^{-2},... $$ and instead treating them as integers.

Binary Coded Decimal (BCD)

• Definition: Each decimal digit (0-9) is represented by its 4-bit binary equivalent. Valid codes: 0000 to 1001. 1010-1111 are invalid.

• Advantage: Easy conversion to/from decimal; accurate decimal representation.

• Disadvantage: Wasted 6 codes (10-15); arithmetic operations require correction (e.g., BCD addition: if sum >9 or carry=1, add 0110).

Excess-3 Code

• Definition: Non-weighted code. Each decimal digit is represented by its binary equivalent + 3.

  • Example: Decimal 2 → Binary 0010 → Excess-3: 0010 + 0011 = 0101.

• Property: Self-complementing. 1's complement of an Excess-3 code gives the code for the 9's complement of the decimal digit.

• Conversion from BCD: Simply add 0011 (3) to the BCD code. If sum > 9, it's invalid for Excess-3.

Gray Code

• Definition: Unit distance code. Only one bit changes between two successive numbers.

• Binary to Gray Conversion:

  1. MSB (G₃) = MSB (B₃)

  2. Gᵢ = Bᵢ₊₁ ⊕ Bᵢ (for i = 2,1,0)

  • Example: B = 1011 → G = 1110.

• Gray to Binary Conversion:

  1. MSB (B₃) = MSB (G₃)

  2. Bᵢ = Bᵢ₊₁ ⊕ Gᵢ (for i = 2,1,0)

• Application: Shaft position encoders, minimize switching noise.

Signed Number Representations

• 1's Complement: Invert all bits of positive number. Range: $$\displaystyle -(2^{n-1}-1) $$ to $$\displaystyle +(2^{n-1}-1) $$. Two zeros (000...0, 111...1).

• 2's Complement: Invert all bits and add 1. Range: $$\displaystyle -2^{n-1} $$ to $$\displaystyle +(2^{n-1}-1) $$. Unique zero. Standard for arithmetic.

  • To find 2's complement of X: $\overline{X} + 1$.

II. BOOLEAN ALGEBRA & LOGIC MINIMIZATION

Key Boolean Theorems (Exam Focus)

• De Morgan's Theorem:

$$\overline{A+B} = \overline{A} \cdot \overline{B}$$

$$\overline{A \cdot B} = \overline{A} + \overline{B}$$

> [!TIP] Remember: "Break the line, change the sign."

• Consensus Theorem: $$\displaystyle AB + \overline{A}C + BC = AB + \overline{A}C $$ (term $BC$ is consensus of $AB$ and $\overline{A}C$).

• Absorption: $$\displaystyle A + AB = A $$; $$\displaystyle A(A+B) = A $$.

Karnaugh Map (K-Map) Method

• Plotting: Fill cells with function value (0,1, or X for Don't Care). Use Gray code ordering for variables.

• Grouping Rules:

  • Groups must be $$\displaystyle 2^n $$ in size (1,2,4,8,...).

  • Groups must be rectangular and contain only 1s or Xs.

  • Groups should be as large as possible and as few as possible.

  • Overlapping allowed. Corner cells wrap-around.

• Terminologies:

  • Implicant: Product term covering some 1s.

  • Prime Implicant (PI): Implicant that cannot be combined further.

  • Essential Prime Implicant (EPI): PI covering a 1 not covered by any other PI.

• Minimal Expression: Sum of all EPIs + minimal set of remaining PIs to cover leftover 1s.

• Don't Care (d): Treated as 1 when helpful for grouping; otherwise ignored.

Quine-McCluskey (Tabular) Method

• Steps:

  1. List all minterms in binary, group by number of 1s.

  2. Compare adjacent groups; combine terms differing in one bit (replace differing bit with -).

  3. Repeat until no more combinations. Uncombined terms are prime implicants.

  4. Construct prime implicant chart (rows: PIs, columns: minterms).

  5. Use Petrick's method or essential prime selection to find minimal cover.

III. COMBINATIONAL LOGIC DESIGN

Design Procedure

1. Specification → 2. Truth Table → 3. K-Map/Equation → 4. Logic Diagram.

Arithmetic Circuits

• Half Adder (HA):

  • $$\displaystyle S = A \oplus B $$, $$\displaystyle C_{out} = A \cdot B $$

  • DiagramCANVAS: 2-input XOR for S, AND for Cout

• Full Adder (FA):

  • $$\displaystyle S = A \oplus B \oplus C_{in} $$

  • $$\displaystyle C_{out} = AB + BC_{in} + AC_{in} $$

  • Using Decoder: 3-to-8 decoder (enable=1). Minterms for S: m1, m2, m4, m7. For Cout: m3, m5, m6, m7. OR corresponding outputs.

• Full Subtractor (FS):

  • $$\displaystyle D = A \oplus B \oplus B_{in} $$

  • $$\displaystyle B_{out} = \overline{A}B_{in} + \overline{A}B + BB_{in} $$

  • Using HAs: $$\displaystyle D = HA(A, B) $$, $$\displaystyle B_{out} = HA(\overline{A}, B_{in}) + (A \cdot B) $$.

Parallel Binary Adder/Subtractor

• Use n FAs. For subtraction ($A - B$), use 2's complement: invert B (using NOT gates) and set initial $$\displaystyle C_{in}=1 $$.

• Control: Use XOR gates at B inputs: $$\displaystyle B_i \oplus Sub/\overline{Sub} $$. When Sub=1, B is inverted and $$\displaystyle C_{in}=1 $$.

Encoders & Decoders

• Encoder (8-to-3): 8 inputs (I0-I7), 3 outputs (A2,A1,A0). Only one input active (priority if multiple).

  • $$\displaystyle A_2 = I_4 + I_5 + I_6 + I_7 $$

  • $$\displaystyle A_1 = I_2 + I_3 + I_6 + I_7 $$

  • $$\displaystyle A_0 = I_1 + I_3 + I_5 + I_7 $$

• Priority Encoder: Outputs code of highest-priority active input. Includes valid (V) and group signal (GS) outputs.

• Decoder (n-to-2ⁿ): Each minterm output $$\displaystyle m_i = \overline{y_{n-1}}...\overline{y_0} $$ for input $$\displaystyle Y_{n-1}...Y_0 $$. Enable inputs (G or E) active-high/low.

• Decoder as Universal: Implement any SOP by ORing relevant minterm outputs.

Multiplexer (MUX) & Demultiplexer (DEMUX)

• MUX (2ⁿ × 1): n select lines (S), 2ⁿ data inputs (D), one output (Y). $$\displaystyle Y = D_0\overline{S_{n-1}}...\overline{S_0} + ... + D_{2^n-1}S_{n-1}...S_0 $$.

• Implementing Function using MUX:

  1. Using n-1 select lines: Connect n-1 variables to select lines. For each combination, determine D input as function of remaining variable (0,1, or that variable/its complement).

  2. Using external gates: If function has >2ⁿ minterms, use external gates on D inputs or output.

• DEMUX (1-to-2ⁿ): One input, n select lines, 2ⁿ outputs. $$\displaystyle O_i = D \cdot S_i'... $$ (active-low select).

• MUX as Universal: Can implement any Boolean function (like decoder).

IV. SEQUENTIAL LOGIC: FLIP-FLOPS & REGISTERS

Basic Latch

• RS Latch (NAND): Active LOW inputs.

  • $$\displaystyle Q_{next} = \overline{R + Q_{prev}} $$ (NAND cross-coupled)

  • Invalid state: R=S=0 (both outputs 1, violates complementarity).

  • Application: Simple memory, debouncing.

Edge-Triggered Flip-Flops

• Triggering: Changes state only at clock edge (positive/negative).

• JK Flip-Flop:

  • Truth Table:

    | J | K | Qₙ₊₁ | |---|---|------| | 0 | 0 | Qₙ | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | $$\displaystyle \overline{Q_n} $$ |

  • Characteristic Equation: $$\displaystyle Q_{next} = J\overline{Q} + \overline{K}Q $$

  • Excitation Table:

    | Qₙ | Qₙ₊₁ | J | K | |----|------|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | X | | 1 | 0 | X | 1 | | 1 | 1 | X | 0 |

• D Flip-Flop:

  • $$\displaystyle Q_{next} = D $$ (transfers D to Q at clock edge).

  • Excitation: $$\displaystyle D = Q_{next} $$.

• T Flip-Flop:

  • Toggles when T=1: $$\displaystyle Q_{next} = T \oplus Q $$.

  • Excitation: $$\displaystyle T = Q \oplus Q_{next} $$.

Flip-Flop Conversion Design

• Method:

  1. Present state (Q) and next state (Q⁺) from given FF's excitation table.

  2. Derive J,K (or D, T) expressions from Q and Q⁺.

  3. Simplify using K-map.

  4. Draw circuit using required FF and gates.

• Example: D to JK Conversion:

  • From JK excitation table, for given Q and Q⁺, find required J,K.

  • Compare with D FF behavior: $$\displaystyle D = Q^+ $$.

  • Thus, $$\displaystyle J = D $$ when Q=0; $$\displaystyle K = \overline{D} $$ when Q=1.

  • Expressions: $$\displaystyle J = D $$, $$\displaystyle K = \overline{D} $$.

  • Realize using NAND gates: $D$ directly to J. $$\displaystyle K = \overline{D} $$ from NAND with both inputs D.

Registers

• Register: Group of FFs storing n-bit word.

• Shift Registers:

  • SISO: Serial In, Serial Out.

  • SIPO: Serial In, Parallel Out.

  • PISO: Parallel In, Serial Out.

  • PIPO: Parallel In, Parallel Out.

• Universal Shift Register:

  • Mode Control (S1,S0):

    • 00: Hold (no shift)

    • 01: Shift Right (SIPO)

    • 10: Shift Left (SIPO)

    • 11: Parallel Load

  • Logic: Each FF input = MUX output selecting between $$\displaystyle D_{parallel} $$, $$\displaystyle Q_{prev} $$ (left shift), $$\displaystyle Q_{next} $$ (right shift), or $Q$ (hold).

• Ring Counter: n-bit circular shift register with output of last FF fed to first. Only one '1' at a time. MOD-n.

• Johnson Counter (Twisted Ring): Complement of last FF output fed to first. Sequence length = 2n. MOD-2n. Contains n zeros and n ones.

V. SEQUENTIAL LOGIC: COUNTERS

Counter Fundamentals

• Asynchronous (Ripple): FF outputs trigger next FF's clock. Slow, cumulative delay.

• Synchronous: All FFs clocked simultaneously. Fast, requires combinational logic for inputs.

• MOD-N Counter: Counts N distinct states before repeating. $$\displaystyle N \leq 2^n $$ for n FFs.

Design of Synchronous Counters (Using JK/D FFs)

• Procedure:

  1. State Diagram & State Table (present state → next state).

  2. Excitation Table: Add columns for FF inputs (J,K or D) using excitation table.

  3. K-Maps: For each FF input (J₀,K₀, J₁,K₁,... or D₀,D₁,...), plot K-map using present state as variables. Find minimal expression.

  4. Logic Diagram: Implement input equations using gates, connect to FFs.

• Example (JK): For sequence 000→110→111→011→010→000 (Dec 2024):

  • Present: Q₂ Q₁ Q₀ | Next: Q₂⁺ Q₁⁺ Q₀⁺

  • Derive J₂,K₂; J₁,K₁; J₀,K₀ from table.

  • Simplify: $$\displaystyle J_0 = Q_1 $$, $$\displaystyle K_0 = 1 $$; $$\displaystyle J_1 = Q_0 $$, $$\displaystyle K_1 = Q_2 $$; $$\displaystyle J_2 = Q_1 \overline{Q_0} $$, $$\displaystyle K_2 = 1 $$.

• Example (D): MOD-6 (0-5) using D FFs (Jun 2023):

  • D₀ = Q₀' (for 0→1,1→2,2→3,3→4,4→5,5→0)

  • D₁ = Q₁'Q₀ + Q₁Q₀'

  • D₂ = Q₂'Q₁Q₀

Asynchronous Counter Design

• MOD-4 DOWN using T FF (Dec 2023):

  • Sequence: 11 → 10 → 01 → 00 → 11.

  • T₀ = 1 (always toggle).

  • T₁ = Q₀ (toggle when LSB goes from 0→1? For DOWN, toggle on 1→0? Check: 11→10 (Q₀ 1→0, Q₁ unchanged? No). Actually for DOWN: T₁ = Q₀'? Let's derive properly.

  • Better: For DOWN count, toggle FF when lower bits are 0. For 2-bit DOWN: T₁ = Q₀'.

  • Circuit: T₀ tied to 1. T₁ = $$\displaystyle \overline{Q_0} $$.

VI. LOGIC FAMILIES & CHARACTERISTICS

Parameters

• Fan-in: Number of inputs a gate can have.

• Fan-out: Number of similar gates a gate output can drive.

• Propagation Delay ($$\displaystyle t_{pd} $$): Average time for signal change from input to output.

• Power Dissipation: $$\displaystyle P = V_{CC} \cdot I_{CC} $$ (static + dynamic).

• Noise Margin: Maximum noise voltage that doesn't affect output.

TTL (Transistor-Transistor Logic)

• Basic Gate (NAND): Multi-emitter input transistor, phase splitter, totem-pole output.

• Totem-Pole Output Stage:

  • Pull-up: Q₂ (active) + Q₄ (emitter follower) when Q₂ ON, Q₃ OFF.

  • Pull-down: Q₃ (active) when Q₂ OFF, Q₃ ON.

  • Advantage: Fast switching (Q₄ provides low impedance pull-up).

• Characteristics: Medium speed, medium power, good fan-out (~10).

CMOS (Complementary MOS)

• Inverter: PMOS (pull-up network) and NMOS (pull-down network) in series.

  • Input=0 → PMOS ON, NMOS OFF → Output=VDD.

  • Input=1 → PMOS OFF, NMOS ON → Output=0.

• 2-input NOR using PMOS (Dec 2023):

  • Pull-up network (PMOS in parallel): (A OR B) → Output high if A=0 OR B=0.

  • Pull-down network (NMOS in series): (A AND B) → Output low only if A=1 AND B=1.

  • DiagramCANVAS: PMOS transistors with sources to VDD, gates A and B connected in parallel; NMOS transistors in series between output and GND, gates A and B

• Characteristics: Very high fan-out, very low static power, high impedance inputs, slower than TTL (but modern CMOS is fast).

TTL vs CMOS Comparison

Other Families

• ECL (Emitter-Coupled Logic): Highest speed (no saturation), high power.

• RTL (Resistor-Transistor Logic): Resistor at input, single transistor. Slow, low fan-out.

• DTL (Diode-Transistor Logic): Diodes at input (wired-AND), transistor output. Improved over RTL.

VII. DATA CONVERSION & DISPLAY DEVICES

Digital-to-Analog Converters (DACs)

• Weighted Resistor: Each bit controls current through resistor weighted $$\displaystyle 2^i $$. Sum at op-amp.

  • $$\displaystyle V_{out} = -\frac{V_{ref}}{R} (b_0 2^0 R + b_1 2^1 R + ...) $$

• R-2R Ladder: Uses only two resistor values (R, 2R). Easier to fabricate.

  • $$\displaystyle V_{out} = -\frac{V_{ref}}{2^n} (b_0 2^{n-1} + b_1 2^{n-2} + ... + b_{n-1} 2^0) $$

• Resolution: $n$ bits → $$\displaystyle 2^n $$ levels. LSB size = $$\displaystyle V_{FS} / 2^n $$.

Analog-to-Digital Converters (ADCs)

• Flash (Parallel):

  • Principle: $$\displaystyle 2^n - 1 $$ comparators compare input with reference ladder. Encoder converts thermometer code to binary.

  • Speed: Fastest (one clock cycle).

  • Disadvantage: Components double for each bit (expensive for high resolution).

  • DiagramSEARCH: flash ADC comparator ladder encoder diagram

• Successive Approximation (SAR):

  • Working:

    1. SAR register initialized (MSB=1, others=0).

    2. DAC converts SAR output to analog $$\displaystyle V_{DAC} $$.

    3. Comparator: If $$\displaystyle V_{in} > V_{DAC} $$, keep MSB=1; else reset to 0.

    4. Next bit: Set next bit to 1, compare, adjust.

    5. Repeat for all bits (n cycles).

  • Speed: Moderate, fixed conversion time (n+1 cycles).

  • Advantage: Good balance of speed and cost.

  • DiagramSEARCH: successive approximation ADC block diagram

Display Devices

• 7-Segment LED Display:

  • Segments: a,b,c,d,e,f,g (and DP).

  • Common Anode (CA): All anodes tied to VCC. Segment lights with LOW.

  • Common Cathode (CC): All cathodes tied to GND. Segment lights with HIGH.

  • Driving: Use BCD-to-7-segment decoder (e.g., 7447 for CA, 7448 for CC). Outputs active-low/high accordingly.

  • Multiplexing: Connect segment lines of all digits together, digit select lines (common) cycled rapidly.

• LCD (Liquid Crystal Display):

  • Principle: Liquid crystal twists polarized light. Requires AC drive (few volts, ~100Hz).

  • Difference from LED:

    • Power: LCD much lower (µW vs mW).

    • Viewing Angle: LCD narrower, contrast varies.

    • Brightness: LED brighter, sunlight readable.

    • Drive: LCD needs AC/charge pump; LED needs DC current limiting.

    • Lifetime: LCD degrades with time/UV; LED longer.

VIII. ADDITIONAL IMPORTANT TOPICS

Schmitt Trigger

• Circuit: Comparator with positive feedback (hysteresis).

• Hysteresis: Two threshold voltages: $$\displaystyle V_{UTP} $$ (upper) and $$\displaystyle V_{LTP} $$ (lower). Width $$\displaystyle V_H = V_{UTP} - V_{LTP} $$.

• Operation:

  • Input < $$\displaystyle V_{LTP} $$ → Output = Low.

  • Input rises above $$\displaystyle V_{UTP} $$ → Output = High.

  • Input > $$\displaystyle V_{UTP} $$ → Output = High.

  • Input falls below $$\displaystyle V_{LTP} $$ → Output = Low.

• Application: Noise immunity, waveform shaping (slow edges to fast), debouncing.

Multivibrators

• Astable: No stable state. Oscillates continuously (e.g., 555 timer in astable mode).

  • $$\displaystyle T = 0.693(R_A + 2R_B)C $$ (for 555).

  • DiagramSEARCH: 555 astable multivibrator circuit

• Monostable: One stable state. Triggered to quasi-stable state for fixed time, then returns.

• Bistable (Flip-Flop): Two stable states. Memory element.

Universal Gates

• NAND & NOR are universal (can implement any Boolean function).

• Realization:

  • NOT: $$\displaystyle A' = A \text{ NAND } A $$

  • AND: $$\displaystyle A \cdot B = (A \text{ NAND } B)' $$

  • OR: $$\displaystyle A + B = (A' \text{ NAND } B') $$ (De Morgan)

• Example (Jun 2023): Show circuits for AND, OR, NOT using only NAND gates.

Race Around Condition & Master-Slave

• Problem in Clocked JK FF: When J=K=1 and clock=1, output toggles continuously (races) if propagation delay < clock pulse width.

• Remedy: Master-Slave JK FF:

  • Two FFs in series: Master (positive level) → Slave (negative edge).

  • Master changes when clock=1, but output not visible until clock=0 (slave updates). Ensures single transition per clock cycle.

Setup & Hold Time

• Setup Time ($$\displaystyle t_{su} $$): Minimum time data input must be stable before clock edge.

• Hold Time ($$\displaystyle t_h $$): Minimum time data input must be stable after clock edge.

• Violation: Causes metastability, unpredictable output.

• Constraint: $$\displaystyle t_{clock} > t_{pd} + t_{su} + t_{skew} $$ (for setup).

Final Exam Strategy:

1. Prioritize ★★★★★ topics: Counter design (specific sequences), Flip-flop conversions (D→JK), MUX implementation, TTL vs CMOS, ADC types, Code converters.

2. Practice derivations: Number conversions (fractional), K-map grouping with don't cares, excitation table → logic circuit.

3. Draw diagrams neatly: Full adder (basic & decoder), Universal shift register, TTL totem-pole, Flash/SAR ADC, 7-segment with decoder.

4. Remember formulas: 2's complement, Gray code conversion, DAC/ADC resolution, 555 astable timing.

5. Compare/contrast: TTL vs CMOS, LED vs LCD, asynchronous vs synchronous counters.

All the best!