Digital Circuits and Systems (IT-305) - Unit 3 Short Notes

UNIT 3: Digital Circuits and Systems

I. Number Systems and Code Conversions

Base Conversion Methods

• Decimal to Other Bases (Integer Part): Repeated division by target base. Remainders give digits (LSB first).

• Decimal to Other Bases (Fractional Part): Repeated multiplication by target base. Integer parts give digits (MSB first).

• Any Base to Decimal: Expand using positional notation. For number $$\displaystyle (d_n d_{n-1} ... d_0 . d_{-1} ... d_{-m})_b $$:

$$ \text{Decimal} = \sum_{i=0}^{n} d_i \times b^i + \sum_{j=1}^{m} d_{-j} \times b^{-j} $$

• Between Non-Decimal Bases: Convert via decimal as intermediate, or use repeated division/multiplication directly if bases are powers (e.g., binary↔octal/hex).

BCD (Binary Coded Decimal)

• Definition: 4-bit binary code representing decimal digits 0-9 (0000 to 1001). Codes 1010-1111 are invalid.

• Conversion:

  • Decimal → BCD: Convert each decimal digit separately to its 4-bit binary equivalent.

  • BCD → Decimal: Group into 4-bit sets, convert each set to decimal digit.

Excess-3 Code

• Definition: Non-weighted BCD code. Each decimal digit is represented by its binary equivalent plus 3 (i.e., add 0011).

  • Decimal 0 → 0011 (3), 1 → 0100 (4), ..., 9 → 1100 (12).

• Key Property: Self-complementing. 9's complement of a decimal digit is obtained by simply inverting all bits of its Excess-3 code.

• BCD to Excess-3 Converter Design:

  • Let BCD input be $$\displaystyle B_3 B_2 B_1 B_0 $$, Excess-3 output $$\displaystyle E_3 E_2 E_1 E_0 $$.

  • K-Maps or logic expressions:

$$ \begin{aligned} E_0 &= B_0 \\ E_1 &= B_1 \oplus B_0 \\ E_2 &= B_2 \oplus (B_1 B_0) \\ E_3 &= B_3 + (B_2 B_1) \end{aligned} $$

Gray Code

• Definition: Only one bit changes between successive code words. Reflective code.

• Binary to Gray Code Conversion:

  • MSB of Gray = MSB of Binary.

  • Subsequent Gray bits = XOR of current binary bit and previous binary bit.

  • $$\displaystyle G_i = B_i \oplus B_{i+1} $$ (for i from MSB-1 to LSB), with $$\displaystyle G_{n} = B_{n} $$.

• Gray to Binary Conversion:

  • MSB of Binary = MSB of Gray.

  • Subsequent Binary bits = XOR of current Gray bit and previous binary bit.

  • $$\displaystyle B_i = G_i \oplus B_{i+1} $$.

1's Complement

• Definition: Invert all bits of the binary number. For an n-bit number $N$, its 1's complement is $$\displaystyle (2^n - 1) - N $$.

• Binary to 1's Complement Converter: Simply pass each bit through a NOT gate. $$\displaystyle \overline{B_i} $$.

[!TIP] Exam Focus: Be prepared to convert fractional numbers between bases. For code converters, know the logic expressions or K-map groupings for BCD→Excess-3 and Binary→Gray.

II. Boolean Algebra and Logic Minimization

Boolean Laws and Theorems (Key for Algebraic Simplification)

Karnaugh Map (K-Map) for 2-4 Variables

• Purpose: Graphical method for minimization of SOP/POS.

• Plotting: Fill cells with 1 for minterms (SOP) or 0 for maxterms (POS). Group adjacent 1s (or 0s) in powers of 2 (1,2,4,8,...). Adjacency includes wrap-around (first/last row/column).

• Grouping Rules: Maximize group size, minimize number of groups. Each group yields a prime implicant.

• Essential Prime Implicant (EPI): A minterm covered by only one prime implicant. Must be included in final expression.

• Minimal SOP/POS: Sum (OR) of all EPIs + selection of remaining prime implicants to cover leftover minterms.

De Morgan's Theorem: Statement & Application

• Statement: The complement of a sum is the product of complements; the complement of a product is the sum of complements.

$$ \overline{A + B + C + ...} = \overline{A} \cdot \overline{B} \cdot \overline{C} \cdot ... $$

$$ \overline{A \cdot B \cdot C \cdot ...} = \overline{A} + \overline{B} + \overline{C} + ... $$

• Proof: Use truth table or algebraic manipulation.

• Applications:

  1. Gate Conversion: NAND is universal (NOT=1-input NAND, AND=NAND+NOT, OR=DeMorgan(NAND)). NOR is universal similarly.

  2. Simplification: Invert complex expressions to simpler forms.

Universal Gates: NAND & NOR Implementation

• Using NAND Only:

  • NOT: $$\displaystyle \overline{A} = A \text{ NAND } A $$

  • AND: $$\displaystyle A \cdot B = \overline{ (A \text{ NAND } B) } = (A \text{ NAND } B) \text{ NAND } (A \text{ NAND } B) $$

  • OR: $$\displaystyle A + B = \overline{ \overline{A} \cdot \overline{B} } = (\overline{A}) \text{ NAND } (\overline{B}) $$

• Using NOR Only: (Similar logic, applying DeMorgan's to OR/AND)

  • NOT: $$\displaystyle \overline{A} = A \text{ NOR } A $$

  • OR: $$\displaystyle A + B = \overline{ \overline{A+B} } = (A \text{ NOR } B) \text{ NOR } (A \text{ NOR } B) $$

  • AND: $$\displaystyle A \cdot B = \overline{ \overline{A} + \overline{B} } = (\overline{A}) \text{ NOR } (\overline{B}) $$

[!TIP] Exam Tip: For K-maps, always show the grouping with circles/ellipses. For algebraic simplification, state the law used at each step. Know how to convert any basic gate to NAND/NOR only.

III. Combinational Logic Design

Adders

Half Adder (HA)

• Function: Adds two 1-bit numbers. Outputs Sum (S) and Carry (C_out).

• Truth Table:

  | A | B | S | C_out | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 |

• Logic Equations: $$\displaystyle S = A \oplus B $$, $$\displaystyle C_{out} = A \cdot B $$

• Logic Diagram: XOR gate for S, AND gate for C_out.

Full Adder (FA)

• Function: Adds three 1-bit numbers (A, B, C_in). Outputs S and C_out.

• Truth Table & K-Map Simplification:

  | A | B | C_in | S | C_out | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |

  • K-maps for S and C_out yield:

$$ S = A \oplus B \oplus C_{in} $$

$$ C_{out} = AB + BC_{in} + AC_{in} $$

• Implementation Using 3-to-8 Decoder:

  • Connect A, B, C_in to decoder inputs (enable active).

  • Minterms for S: m1, m2, m4, m7 → OR outputs of these minterms.

  • Minterms for C_out: m3, m5, m6, m7 → OR outputs of these minterms.

• Implementation Using NAND Gates Only: Implement $S$ and $$\displaystyle C_{out} $$ expressions using only NANDs (double inversion for OR/AND).

Subtractors

Half Subtractor (HS)

• Function: Subtracts two 1-bit numbers (A - B). Outputs Difference (D) and Borrow (B_out).

• Truth Table:

  | A | B | D | B_out | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 |

• Logic Equations: $$\displaystyle D = A \oplus B $$, $$\displaystyle B_{out} = \overline{A} \cdot B $$

Full Subtractor (FS)

• Function: Subtracts three 1-bit numbers (A - B - B_in). Outputs D and B_out.

• Truth Table & K-Map:

  | A | B | B_in | D | B_out | |---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 |

  • K-maps yield:

$$ D = A \oplus B \oplus B_{in} $$

$$ B_{out} = \overline{A}B + \overline{A}B_{in} + BB_{in} $$

• Using Half Subtractors: Two HS units.

  • First HS: Inputs A, B → D1, B1.

  • Second HS: Inputs D1, B_in → Final D, B_out (OR gate combines B1 and B_out from second HS).

Encoders

8-to-3 Line Encoder

• Function: Converts one of 8 active-high input lines ($$\displaystyle I_0 $$ to $$\displaystyle I_7 $$) into 3-bit binary output ($$\displaystyle Y_2 Y_1 Y_0 $$). Assumption: Only one input is active at a time.

• Truth Table:

  | I7 | I6 | I5 | I4 | I3 | I2 | I1 | I0 | Y2 | Y1 | Y0 | |----|----|----|----|----|----|----|----|----|----|----| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | | ... | ... | ... | ... | ... | ... | ... | ... | ... | ... | ... | | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |

• Logic Equations (Active-High):

$$ \begin{aligned} Y_0 &= I_1 + I_3 + I_5 + I_7 \\ Y_1 &= I_2 + I_3 + I_6 + I_7 \\ Y_2 &= I_4 + I_5 + I_6 + I_7 \end{aligned} $$

Priority Encoder

• Concept: Encodes the highest-priority active input. If multiple inputs are active, output corresponds to highest-numbered (or lowest-numbered) active line.

• 4-to-2 Priority Encoder (I3 highest priority):

  • Truth Table includes cases where multiple inputs are 1. Output is binary of highest-priority 1.

  • Enable (E) Output: E=0 if any input is 1; E=1 if all inputs are 0 (no valid input).

  • Logic Equations (for I3 > I2 > I1 > I0):

$$ \begin{aligned} Y_1 &= I_3 + I_2 \\ Y_0 &= I_3 + (I_2 \cdot \overline{I_1}) + (I_3 \cdot \overline{I_2} \cdot I_1) \quad \text{(or simplified via K-map)} \\ E &= \overline{I_3 + I_2 + I_1 + I_0} \end{aligned} $$

Decoders

• n-to-2^n Decoder: Has n input lines, 2^n output lines. Each output corresponds to one minterm of the n inputs. Active-High or Active-Low.

• Example: 2-to-4 Decoder (Enable E):

  | E | A1 | A0 | Y3 | Y2 | Y1 | Y0 | |---|----|----|----|----|----|----| | 0 | X | X | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 |

• Application: Implementing Full Adder using Decoder (3-to-8)

  • Inputs: A, B, C_in to decoder. Enable = 1.

  • Outputs: m0 to m7 correspond to all input combinations.

  • $$\displaystyle S = \Sigma m(1,2,4,7) $$ → OR outputs m1, m2, m4, m7.

  • $$\displaystyle C_{out} = \Sigma m(3,5,6,7) $$ → OR outputs m3, m5, m6, m7.

Multiplexers (MUX) & Demultiplexers (DEMUX)

Multiplexer (4x1 MUX)

• Function: Selects one of 4 data inputs ($$\displaystyle D_0-D_3 $$) and routes it to output Y based on 2 select lines ($$\displaystyle S_1 S_0 $$).

• Truth Table:

  | S1 | S0 | Y | |----|----|---| | 0 | 0 | D0 | | 0 | 1 | D1 | | 1 | 0 | D2 | | 1 | 1 | D3 |

• Logic Diagram: 4 AND gates (each enabled by unique S1S0 combination) feeding an OR gate.

• Implementing Boolean Functions using MUX:

  • Method: Treat select lines as variables. For each combination of select lines, the MUX output is the value of the function for that combination. Connect this value (0 or 1) to the corresponding data input (or use external gates to generate it from remaining variables).

  • Example: Implement $$\displaystyle F(A,B,C,D) = \Sigma(0,3,5,6,8,9,11,13,15) $$ with A,C as select lines (S1=A, S0=C). Create truth table with A,C as rows, B,D as columns. For each (A,C) pair, determine F's value for all B,D combinations. If F is constant for that pair, tie D-input to 0/1. If F depends on B/D, use external gates.

Demultiplexer (DEMUX)

• Function: Routes one data input to one of 2^n outputs based on n select lines. Inverse of MUX.

• 1-to-4 DEMUX: Input D, Selects S1,S0. Outputs Y0-Y3. Only one Y is active (equal to D) at a time.

Code Converters as Combinational Circuits

• Binary to Gray Code Converter: Use logic from Section I. $$\displaystyle G_2 = B_2 $$, $$\displaystyle G_1 = B_2 \oplus B_1 $$, $$\displaystyle G_0 = B_1 \oplus B_0 $$. Implement with XOR gates.

• BCD to Excess-3 Code Converter: Use logic from Section I. $$\displaystyle E_0 = B_0 $$, $$\displaystyle E_1 = B_1 \oplus B_0 $$, $$\displaystyle E_2 = B_2 \oplus (B_1 B_0) $$, $$\displaystyle E_3 = B_3 + (B_2 B_1) $$. Implement with XOR, AND, OR gates.

• Binary to 1's Complement Converter: Inverter bank. $$\displaystyle \overline{B_i} $$ for each bit.

[!TIP] Common Pitfall: In MUX implementation, ensure you correctly identify which variables are select lines and which are used to generate data inputs. Always verify with a truth table.

IV. Sequential Logic: Flip-Flops and Counters

A. Flip-Flops

RS Flip-Flop (NAND-based, active-low inputs)

• Circuit: Cross-coupled NAND gates. $ \overline{S} $ and $ \overline{R} $ inputs.

• Truth Table (for $\overline{S}, \overline{R}$):

  | $\overline{S}$ | $\overline{R}$ | Q(t+1) | Comment | |---|---|---|---| | 1 | 1 | Q(t) | No change (Hold) | | 0 | 1 | 1 | Set | | 1 | 0 | 0 | Reset | | 0 | 0 | 0? | Invalid (both outputs 1) |

• Applications: Basic memory element, switch debouncing circuit.

• Race Condition: In NOR-based SRFF, $$\displaystyle S=R=1 $$ leads to unpredictable state. NAND-based uses active-low to avoid this during power-up.

D Flip-Flop (Edge-Triggered)

• Function: 1-bit memory. Output Q follows input D at clock edge (positive or negative).

• Truth Table:

  | CLK | D | Q(t+1) | |---|---|---| | ↑ | 0 | 0 | | ↑ | 1 | 1 | | Other times | X | Q(t) (No change) |

• Characteristic Equation: $$\displaystyle Q^* = D $$ (next state equals D at clock edge).

• Timing Diagram: Show clock, D, and Q. Q changes only at triggering clock edge, mirroring D just before the edge.

JK Flip-Flop

• Function: Solves invalid state of SRFF. J=K=1 toggles output.

• Truth Table:

  | J | K | CLK | Q(t+1) | |---|---|---|---| | 0 | 0 | ↑ | Q(t) (Hold) | | 0 | 1 | ↑ | 0 (Reset) | | 1 | 0 | ↑ | 1 (Set) | | 1 | 1 | ↑ | $\overline{Q(t)}$ (Toggle) |

• Excitation Table: (For design) Given present state Q and next state Q+, determine required J,K.

  | Q | Q+ | J | K | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | X | | 1 | 0 | X | 1 | | 1 | 1 | X | 0 |

• Characteristic Equation: $$\displaystyle Q^* = J\overline{Q} + \overline{K}Q $$

• Race-Around Condition: In a level-sensitive JKFF (basic latch), J=K=1 causes output to toggle multiple times within one clock pulse if propagation delay is small. Solution: Use Master-Slave JKFF (two latches, clock inverted for slave) or modern edge-triggered designs.

T Flip-Flop

• Function: Toggles output when T=1 at clock edge.

• Truth Table:

  | T | CLK | Q(t+1) | |---|---|---| | 0 | ↑ | Q(t) | | 1 | ↑ | $\overline{Q(t)}$ |

• Characteristic Equation: $$\displaystyle Q^* = T \oplus Q $$ or $$\displaystyle Q^* = T\overline{Q} + \overline{T}Q $$

• Implementation: Connect J and K of JKFF together to form T input.

Flip-Flop Conversion (Example: D to JK)

• Method: Use excitation table method.

  1. Write excitation table for target FF (JK).

  2. Express J and K in terms of D and present state Q (from DFF's characteristic equation $$\displaystyle Q^* = D $$).

  3. Create K-maps for J and K with variables D and Q.

  4. Derive minimal logic equations for J and K.

  5. Draw circuit: D input to DFF, Q output feeds back to combinational logic generating J,K inputs.

• Result for D→JK using NANDs:

  $$\displaystyle J = D $$, $$\displaystyle K = \overline{D} $$ (if using positive-edge DFF). Implement NOT with NAND.

B. Counters

Asynchronous (Ripple) Counters

• MOD-4 DOWN Counter using T FFs:

  • Connection: All T inputs = 1 (to toggle). Clock of FF1 (LSB) = external clock. Clock of FF2 = $$\displaystyle \overline{Q_1} $$ (negative edge triggered) or Q1 (positive edge, depending on FF type).

  • State Diagram (Down): 00 → 11 → 10 → 01 → 00...

  • Timing Diagram: Show clock, Q1, Q0. Q1 changes state after propagation delay from Q0's transition (ripple effect). Glitches possible.

Synchronous Counters

• Design using JK FFs (Excitation Table Method):

  1. Draw state diagram / sequence table (present state Q, next state Q+).

  2. For each FF (Q0, Q1, Q2...), create column in excitation table using JK excitation table.

  3. Plot K-maps for each J and K input with present state bits as variables.

  4. Simplify to get minimal expressions for J0, K0, J1, K1, ...

  5. Draw circuit: FFs with clock tied together (synchronous), combinational logic from present state Q to J,K inputs.

• Example: Design for Sequence 0→6→7→1→4→2→0 (3-bit, using JK FFs).

  • Sequence Table:

    | Present State (Q2 Q1 Q0) | Next State (Q2+ Q1+ Q0+) | J2 K2 | J1 K1 | J0 K0 | |---|---|---|---|---| | 0 0 0 | 0 1 1 | 0 X | 1 X | 1 X | | 0 1 1 | 0 1 1 | 0 X | 0 X | 0 X | | 0 1 1 | 0 0 1 | 0 X | X 1 | 1 X | | 0 0 1 | 1 0 0 | 1 X | X 1 | X 1 | | 1 0 0 | 0 1 0 | X 1 | 1 X | 0 X | | 0 1 0 | 0 0 0 | 0 X | X 1 | X 1 | | 0 0 0 | ... | ... | ... | ... |

  • K-maps for J2,K2 etc. yield minimal expressions.

MOD-6 Counter using D FFs

• Design: Sequence 000→001→010→011→100→101→000 (6 states). Use 3 D FFs (Q2 Q1 Q0). Unused states (110,111) must be handled (self-correcting or not).

• State Table & D Equations: $$\displaystyle D_i = Q_i^+ $$. From sequence, derive:

  $$\displaystyle D_0 = \overline{Q_2} \overline{Q_1} $$, $$\displaystyle D_1 = \overline{Q_2} Q_0 $$, $$\displaystyle D_2 = Q_1 Q_0 $$ (example, verify).

• Circuit: Synchronous D FFs with combinational logic from Q2,Q1,Q0 to D2,D1,D0.

Johnson Counter (Twisted Ring Counter)

• Operation: n-bit shift register. Inverted output of last FF ($$\displaystyle \overline{Q_{n-1}} $$) fed back to input of first FF.

• State Diagram: For n=4: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000. 2n states.

• Waveform: Show clock, Q3,Q2,Q1,Q0. Pattern: one 0 moves left, one 1 moves right.

• Applications: Frequency division (by 2n), pattern generation, synchronous divide-by-n counters.

Ring Counter

• Operation: n-bit shift register. Output of last FF ($$\displaystyle Q_{n-1} $$) fed back to input of first FF. Only one '1' at a time.

• State Diagram (n=4): 0001 → 0010 → 0100 → 1000 → 0001...

• Waveform: Single '1' circulates.

• Applications: Event counter, one-hot state machine encoding, synchronous control.

[!TIP] Exam Focus: For counter design, always start with the state diagram/sequence table. Use excitation tables for JK, characteristic equation for D/T. For asynchronous counters, clearly show ripple clock connections. For Johnson/Ring counters, draw the feedback connection and waveform for at least 2 full cycles.

V. Shift Registers

Basic Types

Universal Shift Register

• Mode Control: Two select lines $$\displaystyle S_1, S_0 $$.

  | S1 | S0 | Operation | |---|---|---| | 0 | 0 | Hold (No change) | | 0 | 1 | Shift Right (Serial In → LSB) | | 1 | 0 | Shift Left (Serial In → MSB) | | 1 | 1 | Parallel Load |

• Logic Diagram: Uses 2:1 multiplexers at the input of each flip-flop.

  • For each FF (Qi), its input D_i comes from a MUX.

  • MUX inputs: For shift right: from $$\displaystyle Q_{i-1} $$ (or SI for i=0). For shift left: from $$\displaystyle Q_{i+1} $$ (or SI for i=n-1). For parallel load: from $$\displaystyle P_i $$. For hold: from $$\displaystyle Q_i $$ (feedback).

  • Common clock for all FFs.

• Operation: Mode pins select which data source feeds each FF's input on clock edge.

[!TIP] For universal shift register, draw the block diagram with MUXes clearly labeled. State the mode table in your notes.

VI. Logic Families

A. TTL (Transistor-Transistor Logic)

2-Input NAND Gate (Totem-Pole Output)

• Circuit: Multi-emitter input transistor (T1), phase splitter (T2), totem-pole output (T3 pull-up, T4 pull-down).

• Operation:

  • Inputs High (A=1, B=1): T1 off, T2 on → T3 on (saturated), T4 off → Output Low (0).

  • Any Input Low: T1 on (one emitter conducts) → T2 off → T3 off, T4 on → Output High (1).

• Advantages: Fast switching (totem-pole reduces output capacitance charging time), good noise immunity.

2-Input NOR Gate (Open-Collector Output)

• Circuit: Input transistors in parallel (T1,T2), single output transistor T3 (collector open), pull-up resistor.

• Operation: If any input high, T1 or T2 on → T3 on → Output Low (0). Only if all inputs low, T1,T2 off → T3 off → Output High (1 via pull-up).

• Note: Open-collector allows wired-AND connection.

TTL Characteristics

B. CMOS (Complementary MOS)

CMOS Inverter

• Pull-up Network (PUN): PMOS transistors (conduct when input low).

• Pull-down Network (PDN): NMOS transistors (conduct when input high).

• Operation: Input High → PDN on (to GND), PUN off → Output Low. Input Low → PUN on (to VDD), PDN off → Output High. Never both on → low static power.

CMOS Gates Implementation

• NAND: PDN: 2 NMOS in series. PUN: 2 PMOS in parallel.

• NOR: PDN: 2 NMOS in parallel. PUN: 2 PMOS in series.

• General Rule: PDN = pull-down network for function (using NMOS). PUN = dual network (series↔parallel swap) using PMOS.

CMOS Characteristics

C. Other Logic Families (Comparative Analysis)

D. Special Circuits

Schmitt Trigger

• Circuit: Using op-amp with positive feedback or using gates (e.g., CMOS inverter with feedback).

• Hysteresis: Two different threshold voltages: $$\displaystyle V_{T+} $$ (rising) and $$\displaystyle V_{T-} $$ (falling). Width = $$\displaystyle V_{T+} - V_{T-} $$.

• Transfer Characteristic: S-shaped curve with hysteresis loop.

• Application: Noise immunity for slow-changing signals, waveform shaping (clean digital edges from analog), debouncing.

Astable Multivibrator using 555 Timer

• Circuit: 555 in astable mode. Pins: TH (2), TR (6) connected to capacitor C, DIS (7) between R_A and R_B, CV (5) optional decoupling.

• Operation: Capacitor C charges through R_A+R_B via DIS pin. When V_C > 2/3 VCC, output low, DIS on → C discharges through R_B. When V_C < 1/3 VCC, output high, DIS off → C charges again.

• Frequency Calculation:

$$ f = \frac{1.44}{(R_A + 2R_B) C} $$

Duty Cycle % = $$\displaystyle \frac{R_A + R_B}{R_A + 2R_B} \times 100 $$

• Waveform: Sawtooth on capacitor, square wave on output (pin 3).

[!TIP] Comparison Table: Be ready to draw a table comparing TTL, ECL, CMOS on fan-in, fan-out, propagation delay, power dissipation. Know the 555 astable formula and hysteresis concept.

VII. Display and Data Conversion Devices

A. Display Devices

LED 7-Segment Display

• Segments: Labeled a, b, c, d, e, f, g (and dp).

• Common Anode (CA): All anodes connected to VCC. Segment lights when its cathode is Low (0).

• Common Cathode (CC): All cathodes connected to GND. Segment lights when its anode is High (1).

• Driving: Use BCD-to-7-segment decoder/driver (e.g., 7447 for CA, 7448 for CC). Inputs: BCD (A,B,C,D). Outputs: a,b,c,d,e,f,g (active-low for 7447).

LCD (Liquid Crystal Display)

• Operation (Twisted Nematic): Liquid crystal between polarizers. Voltage applied → crystals untwist → blocks light. No voltage → crystals twist → allows light.

• Advantages over LED: Very low power (microwatts), no backlight needed for reflective, slim, large area possible.

• Disadvantages: Slow response time, narrow viewing angle, temperature sensitive, requires AC drive (to prevent electrolysis).

• Typical Difference: LED is emissive (self-light), LCD is transmissive/reflective (modulates light). LED faster, brighter; LCD lower power.

B. Analog-to-Digital Converters (ADCs)

Types

• Flash (Parallel): Uses $$\displaystyle 2^n-1 $$ comparators for n-bit. Fastest, most expensive.

• Successive Approximation: Uses SAR, comparator, DAC. Conversion time = (n+1) clock cycles.

• Dual-Slope: Integrates input for fixed time, then de-integrates. High noise rejection, slow.

• Sigma-Delta: Oversampling, noise shaping. High resolution, slow.

Successive Approximation ADC (SAR ADC)

• Block Diagram:

  Analog Input → Sample/Hold → Comparator ↔ DAC ← SAR (Control Logic)

• Working:

  1. Sample: Input voltage $$\displaystyle V_{in} $$ held by S/H.

  2. Approximation: SAR starts with MSB=1, others=0. DAC outputs $$\displaystyle V_{ref}/2 $$.

  3. Compare: Comparator output tells if $$\displaystyle V_{in} > V_{DAC} $$.

  4. Adjust: If $$\displaystyle V_{in} > V_{DAC} $$, keep MSB=1; else clear it. Move to next bit (MSB-1).

  5. Repeat for all n bits. After n cycles, SAR holds digital equivalent.

• Conversion Time: n+1 clock periods (1 for sampling, n for bit trials).

Flash ADC

• Circuit: $$\displaystyle 2^n-1 $$ comparators. Each compares $$\displaystyle V_{in} $$ with a reference voltage from resistor ladder ($$\displaystyle V_{ref} \cdot k/2^n $$).

• Encoder: Thermometer-to-binary encoder converts comparator outputs to n-bit binary.

• Advantages: Very high speed (single clock cycle).

• Disadvantages: Component count doubles with each bit (expensive, high power, large area).

[!TIP] Key Formulas: 555 frequency $$\displaystyle f = 1.44/((R_A+2R_B)C) $$. SAR ADC conversion time = n+1 cycles. For display, remember CA vs CC driving logic.

END OF UNIT 3 NOTES
Focus on past paper patterns: conversions, K-maps, adder/subtractor design, flip-flop characteristics, counter design (especially arbitrary sequences), MUX implementation, TTL/CMOS comparison, and ADC/SAR explanation.