UNIT 2: Digital Circuits and Systems – Short Notes

1. Number Systems and Code Conversions

Base Conversion Techniques

Integer Part Conversion (From Base b to Decimal):

$$ (N)_b = d_{n-1}b^{n-1} + d_{n-2}b^{n-2} + ... + d_1b^1 + d_0b^0 $$

Fractional Part Conversion:

$$ (0.F)_b = f_{-1}b^{-1} + f_{-2}b^{-2} + ... $$

[!TIP] For base conversion between non-decimal bases (e.g., base 6 to base 9), always convert via decimal as an intermediate step.

Decimal to Other Base (Integer): Repeated division by new base b, remainders give digits (LSB first). Decimal to Other Base (Fractional): Repeated multiplication by b, integer parts give digits (MSB first).

Conversion Among Binary, Octal, Hexadecimal

• Binary ↔ Octal: Group 3 bits (pad with leading/trailing zeros).

• Binary ↔ Hex: Group 4 bits.

• Octal/Hex ↔ Decimal: Use positional notation or convert via binary.

BCD (Binary Coded Decimal)

• Each decimal digit (0-9) represented by 4-bit binary.

• Valid codes: 0000 to 1001. 1010-1111 are invalid.

• Decimal to BCD: Convert each digit separately.

• BCD to Decimal: Group 4 bits, convert each group.

Excess-3 Code

• Non-weighted code. Each decimal digit d represented by binary of (d + 3).

• Example: Decimal 5 → 5+3=8 → 1000 (Excess-3).

• Key Property: Self-complementing. 9's complement obtained by 1's complementing all bits.

Gray Code

• Unit distance code. Only 1 bit changes between consecutive numbers.

• Binary to Gray (Most Significant Bit same):

$$ G_i = B_i \oplus B_{i+1} \quad (\text{for } i < n), \quad G_{n-1} = B_{n-1} $$

• Gray to Binary:

$$ B_{n-1} = G_{n-1}, \quad B_i = B_{i+1} \oplus G_i $$

1's Complement Representation

• Negative number: 1's complement of positive equivalent.

• For n-bit number N: -N = (2^n - 1) - N.

• Circuit for 3-bit: Simply invert all bits using NOT gates.

Code Converter Design Principles

1. Write truth table mapping input code (source) to output code (target).

2. Derive Boolean expression for each output bit (K-map or algebra).

3. Implement with logic gates (2-level NAND/NOR preferred).

[!TIP] Exam Focus: Be prepared to design BCD→Excess-3 and Binary→Gray converters. Remember BCD→Excess-3 adds 0011 to each digit; Gray MSB = Binary MSB.

2. Boolean Algebra and Minimization

Boolean Laws and Theorems (Key for Algebraic Simplification)

Karnaugh Map (K-map) Minimization

• Groups: Must be 2^n cells (1,2,4,8,...). Adjacent (including wrap-around).

• Implicant: Any group.

• Prime Implicant (PI): Not contained in larger group.

• Essential Prime Implicant (EPI): Covers a minterm not covered by any other PI.

• Minimal SOP: Sum of all EPIs + minimum PIs to cover remaining minterms.

• Don't Cares (d): Treat as 1 for grouping, but need not be covered. Use to enlarge groups.

SOP and POS Forms

• SOP (Sum of Products): OR of AND terms (minterms). F = Σm(...).

• POS (Product of Sums): AND of OR terms (maxterms). F = ΠM(...).

• Minimization: K-map directly gives minimal SOP. For POS, group 0s (maxterms) → minimal POS = complement of grouped 0s (apply De Morgan).

[!TIP] Exam Trap: For F = Σm(0,1,4,5), zeros are at 2,3,6,7. Minimal POS = ΠM(2,3,6,7). Always verify with truth table.

3. Combinational Logic Circuits

3.1 Encoders

8-to-3 Line Encoder:

• Inputs: I7-I0 (8 lines, active-high), Outputs: A2,A1,A0 (binary code).

• Truth Table: Only one input active at a time. If multiple active → invalid.

• Logic: A2 = I7 + I6 + I5 + I4, A1 = I7 + I6 + I3 + I2, A0 = I7 + I5 + I3 + I1.

• Enable (often E): E = I7 + I6 + ... + I0 (at least one input active).

Priority Encoder:

• Concept: Multiple inputs may be active; output corresponds to highest-priority (largest index) active input.

• Additional Output: V (valid, at least one input active).

• Design: Use priority logic (e.g., I7 has highest priority → if I7=1, output=111 regardless of others).

3.2 Decoders

• n-to-2ⁿ decoder: Each input combination activates exactly one output line (minterm generation).

• Full Adder using Decoder (3-to-8) & OR gates:

  • Connect A,B,C to decoder inputs.

  • S = Σm(1,2,4,7) → OR outputs m1,m2,m4,m7.

  • C_out = Σm(3,5,6,7) → OR outputs m3,m5,m6,m7.

3.3 Multiplexers (MUX) & Demultiplexers (DEMUX)

4×1 MUX:

• 2 select lines (S1,S0), 4 data inputs (D0-D3), 1 output Y.

• Y = (S1'S0'·D0) + (S1'S0·D1) + (S1S0'·D2) + (S1S0·D3)

• Implementing any Boolean function of n variables:

  • Use 2ⁿ:1 MUX.

  • Connect n-1 variables to select lines.

  • Connect remaining variable (or its complement) to data inputs based on truth table.

  • Or use external gates on data inputs (as in Dec 2023 Q: F(A,B,C,D)=Σ(...) with A,C as select lines).

Demultiplexer (1-to-2ⁿ):

• Reverse of MUX. 1 input, n select lines, 2ⁿ outputs.

• Y_i = S'...·Input (only one output active based on select code).

3.4 Arithmetic Circuits

Half Adder (HA):

• Inputs: A,B. Outputs: Sum = A⊕B, Carry = A·B. Full Adder (FA):

• S = A⊕B⊕C_in, C_out = AB + BC_in + AC_in.

• Using two HAs: S1 = A⊕B, C1 = A·B; S = S1⊕C_in, C_out = C1 + S1·C_in.

Half Subtractor (HS):

• Diff = A⊕B, Borrow = A'·B. Full Subtractor (FS) using HAs:

• First HA: A - B → D1 = A⊕B, B1 = A'·B.

• Second HA: D1 - B_in → Diff = D1⊕B_in, B2 = D1'·B_in.

• Borrow = B1 + B2.

[!TIP] Design Tip: FA using decoder is a classic exam question. Remember: S from minterms 1,2,4,7; C_out from 3,5,6,7.

4. Sequential Logic: Flip-Flops and Registers

4.1 Flip-Flops

SR Flip-Flop (NAND-based, active-low):

• Truth Table:

  | S' | R' | Q(t+1) | Comment | |---|---|---|---| | 1 | 1 | No change | | | 0 | 1 | 1 | Set | | 1 | 0 | 0 | Reset | | 0 | 0 | ? | Invalid |

• Applications: Simple storage, debouncing.

JK Flip-Flop:

• Truth Table:

  | J | K | Q(t+1) | |---|---|---| | 0 | 0 | Q(t) | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | Q'(t) (Toggle) |

• Characteristic Equation: $$\displaystyle Q_{t+1} = JQ' + K'Q $$

• Excitation Table:

  | Q(t) | Q(t+1) | J | K | |---|---|---|---| | 0 | 0 | 0 | X | | 0 | 1 | 1 | X | | 1 | 0 | X | 1 | | 1 | 1 | X | 0 |

D Flip-Flop:

• Truth Table: Q(t+1) = D

• Characteristic Equation: $$\displaystyle Q_{t+1} = D $$

• Applications: Data storage, delay line.

T Flip-Flop:

• Truth Table: Q(t+1) = T ⊕ Q(t) (Toggle if T=1)

• Characteristic Equation: $$\displaystyle Q_{t+1} = TQ' + T'Q $$

4.2 Registers

Register: Group of flip-flops storing one word of data. Serial vs Parallel:

Universal Shift Register (4-bit example):

• Mode Control (S1 S0):

  • 00: Hold (no change)

  • 01: Shift Right (serial input SER_in)

  • 10: Shift Left (serial input SER_in)

  • 11: Parallel Load (I3-I0 → Q3-Q0)

• Logic: Each flip-flop's D input = MUX output selecting between Q_{i-1}, Q_{i+1}, I_i, Q_i.

4.3 Shift Register Applications

Ring Counter:

• Connection: Output of last FF (Q3) fed back to input of first (D0).

• Sequence: 1000 → 0100 → 0010 → 0001 → 1000... (4-state for 4-bit).

• Applications: Modulo-n counter, event detection, synchronous control.

Johnson Counter (Twisted Ring Counter):

• Connection: Complement of last FF (Q3') fed back to first (D0).

• 4-bit Sequence: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000... (2n states).

• Applications: Divide-by-2n counter, pattern generator.

[!TIP] Exam Key: Ring counter has n states, Johnson has 2n states. Always draw feedback connection correctly.

5. Counters

5.1 Counter Types

• Asynchronous (Ripple): FF clocks cascaded (output of one drives clock of next). Ripple delay, slower.

• Synchronous: All FFs clocked simultaneously by common clock. Faster, no ripple.

5.2 Counter Design Procedure

1. State Diagram / Sequence given.

2. State Table (present state Q, next state Q⁺).

3. Excitation Table (choose FF type: T, D, JK).

4. K-maps for each FF input → Input Equations (minimal SOP).

5. Draw Circuit with FFs and combinational logic.

6. Output Logic (if output is not FF state directly).

Design Examples from Past Papers:

• MOD-4 DOWN using T-FF: States 11 → 10 → 01 → 00 → 11...

  • T inputs: T1 = Q0, T0 = 1 (always toggle).

• MOD-6 using D-FF: States 000 → 001 → 010 → 011 → 100 → 101 → 000...

  • D equations from K-map: D2 = Q1Q0 + Q2Q1', etc.

• Custom Sequence (JK-FF): e.g., 0→6→7→1→4→2→0 (Dec 2023).

  • State assign: 0=000, 6=110, 7=111, 1=001, 4=100, 2=010.

  • JK excitation: J=Q⁺·Q', K=Q·Q⁺'. Derive equations via K-map.

[!TIP] Critical: For custom sequence, ensure unused states lead to valid sequence (self-starting) or add reset logic.

6. Logic Families

6.1 TTL (Transistor-Transistor Logic)

Totem-Pole TTL 2-input NAND Gate:

• Internal: Multi-emitter input transistor, phase splitter, totem-pole output (Q1 active pull-up, Q4 active pull-down).

• Operation:

  • Any input low → Q1 saturates → Q2 off → Q4 off → Output high (via Q3 pull-up).

  • All inputs high → Q1 off → Q2 on → Q4 on → Output low.

• Advantages: Fast (no resistor pull-up), good noise immunity.

TTL 2-input NOR Gate:

• Uses open-collector output (requires external pull-up resistor).

• Slower than totem-pole due to RC time constant.

TTL Characteristics:

• Propagation Delay: ~10 ns (moderate).

• Power Dissipation: ~10 mW/gate (higher).

• Fan-out: ~10 (limited by input current).

• Noise Margin: Low (~0.4V).

6.2 CMOS (Complementary MOS)

Basic CMOS Inverter:

• Series PMOS (pull-up) and NMOS (pull-down).

• Input High → NMOS on, PMOS off → Output Low.

• Input Low → NMOS off, PMOS on → Output High.

• Static power dissipation ~0 (except during switching).

CMOS NAND (2-input):

• Series NMOS for pull-down (both must conduct for Low).

• Parallel PMOS for pull-up (either conducts for High).

PMOS Logic (2-input NOR):

• Series PMOS for pull-up (both must be off for High? Actually: NOR = (A+B)'. PMOS in parallel for A' and B'? Wait: PMOS conducts when input low. NOR output high only when A=0 and B=0 → PMOS in series? Let's correct:**

  • PMOS NOR: PMOS in parallel for pull-up? Actually: Output = (A+B)'. For output high, A=0 and B=0. So PMOS should be series? No: PMOS conducts when gate=0. To get high when A=0 and B=0, need series PMOS (both must conduct). So PMOS NOR = series PMOS.

  • But standard: CMOS NOR = parallel NMOS (pull-down), series PMOS (pull-up).

CMOS Characteristics:

• Propagation Delay: Higher than TTL (~20-50 ns), but improves with scaling.

• Power Dissipation: Very low (static ~0, dynamic αC V²f).

• Fan-out: Very high (~50+).

• Noise Immunity: High (rail-to-rail swing, symmetrical thresholds).

6.3 Comparisons

RTL vs DTL:

• RTL (Resistor-Transistor Logic): Input resistor + transistor. Slow (base charge storage), poor noise margin.

• DTL (Diode-Transistor Logic): Diode-AND + transistor. Better than RTL, but diode voltage drops limit noise margin.

• Both obsolete; replaced by TTL/CMOS.

[!TIP] Memory Aid: CMOS = low power, high fan-out. TTL = faster but power-hungry. ECL = fastest but power-hungry.

7. Data Conversion and Display

7.1 Analog-to-Digital Converters (ADCs)

Types:

• Flash (Parallel): 2ⁿ - 1 comparators, fastest, expensive (n bits).

• Successive Approximation (SAR): Uses SAR register & DAC. Medium speed, good accuracy, popular.

• Dual-Slope: Integrator-based, slow but accurate, noise immune (used in DMMs).

• Sigma-Delta: Oversampling, high resolution, used in audio.

Successive Approximation ADC:

• Block Diagram: Sample/Hold → Comparator → SAR (successive approximation register) → DAC → Control Logic.

• Working:

  1. SAR sets MSB=1, others=0 → DAC voltage V_DAC.

  2. Comparator: if V_in > V_DAC, MSB stays 1; else 0.

  3. Repeat for next bit (binary search).

  4. After n cycles, SAR holds digital output.

• Timing: n+1 clock cycles (including sample).

• Advantages: Moderate speed, good accuracy, no need for precise linearity in DAC.

• Disadvantages: Conversion time ∝ n.

Flash ADC:

• Operation: 2ⁿ - 1 comparators compare V_in with reference ladder (V_ref/2ⁿ steps). Encoder converts thermometer code to binary.

• Speed: Very fast (propagation delay only).

• Limitation: Exponential hardware; practical only up to 8 bits.

7.2 Display Devices

LED 7-Segment Display:

• Segments: a,b,c,d,e,f,g (7) + DP (decimal point).

• Common Anode (CA): All anodes tied to Vcc. Segment lights when cathode = 0.

• Common Cathode (CC): All cathodes tied to GND. Segment lights when anode = 1.

• Driving: Use BCD-to-7-segment decoder/driver (e.g., 7447 for CA, 7448 for CC). Current limiting resistors required.

LCD (Liquid Crystal Display):

• Principle: Liquid crystal rotates polarized light. Requires AC drive (typically 100-500 Hz) to prevent degradation.

• Structure: Two glass plates with ITO electrodes, liquid crystal between, polarizers.

• Pixel Addressing: Multiplexed (e.g., 1/2 duty, 1/3 bias). Segment connected to common backplane and segment electrode.

• Advantages over LED: Low power (battery operated), no glare, larger sizes possible.

• Disadvantages: Slow response, narrow viewing angle, needs backlight (transmissive), temperature sensitive.

LED vs LCD Comparison:

7.3 Signal Conditioning Circuits

Schmitt Trigger:

• Circuit: Comparator with positive feedback (hysteresis).

• Operation:

  • V_in rises: Output switches high at V_UT = V_ref + ΔV/2.

  • V_in falls: Output switches low at V_LT = V_ref - ΔV/2.

  • Hysteresis width ΔV = V_UT - V_LT.

• Application: Noise immunity for slow/ noisy signals (e.g., clock recovery from sine wave, debouncing).

[!TIP] ADC Recall: SAR is most common in microcontrollers. Flash is fastest but impractical for high bits. Schmitt trigger converts analog to digital with hysteresis.

8. Additional Topics (High-Yield Short Notes)

De Morgan's Theorem

• Statement: $$\displaystyle \overline{A+B} = A' \cdot B' $$, $$\displaystyle \overline{A \cdot B} = A' + B' $$.

• Application:

  1. Simplify expressions with complements over operations.

  2. Implement NAND/NOR as universal gates: NOT = NAND with inputs tied; AND = NAND + NAND (inverter); OR = NOR + NOR (inverter).

  3. Convert SOP to NAND-only: Double invert → apply De Morgan → all NANDs.

• Example: $$\displaystyle F = AB + CD = \overline{\overline{AB + CD}} = \overline{(\overline{AB}) \cdot (\overline{CD})} $$ → NAND(NAND(A,B), NAND(C,D)).

Universal Gates: NAND and NOR

• NAND Universal:

  • NOT: Y = NAND(A,A)

  • AND: Y = NAND(NAND(A,B), NAND(A,B))

  • OR: Y = NAND(NAND(A,A), NAND(B,B))

• NOR Universal:

  • NOT: Y = NOR(A,A)

  • OR: Y = NOR(NOR(A,B), NOR(A,B))

  • AND: Y = NOR(NOR(A,A), NOR(B,B))

• Realization: Any Boolean function can be built from NANDs or NORs only.

Astable Multivibrator (Clock Generator)

• Circuit: Two inverting gates (e.g., CMOS inverters) with RC feedback.

• Operation: Capacitor charges/discharges between threshold voltages, causing output to oscillate.

• Frequency: $$\displaystyle f \approx \frac{1}{2RC} $$ (for symmetric CMOS inverter thresholds).

• Application: Simple clock source, LED flasher.

Multiplexer and Demultiplexer (Recap)

• MUX: 2ⁿ:1 selects one of 2ⁿ inputs → single output. "Many-to-one".

• DEMUX: 1:2ⁿ routes one input to one of 2ⁿ outputs. "One-to-many".

• Applications: Data routing, parallel-to-serial conversion (MUX), serial-to-parallel (DEMUX), function implementation.

7-Segment LED Display (Recap)

• Decoder/Driver ICs: 7447 (BCD→7-seg for CA), 7448 (for CC).

• Pinout: a,b,c,d,e,f,g, DP.

• Current Limiting: Resistors (220-330 Ω) in series with each segment.

Johnson Counter (Recap)

• Feedback: Q_n' → D_0.

• States: 2n unique states.

• Decoding: Only n states have single 1 (easy to decode modulo-n). Others have multiple 1s.

• Example (4-bit): 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 → 8 states.

Final Exam Strategy:

1. Conversions: Practice integer + fractional conversions. BCD/Excess-3/Gray are guaranteed.

2. K-map: Always group largest 2^n cells. Don't cares are X—use to enlarge groups but don't need to cover.

3. Combinational Circuits: Encoder (priority vs normal), MUX implementation (use select lines wisely), FA using decoder.

4. Flip-Flops: Know characteristic equations. Conversion (D→JK) is frequent.

5. Counters: Design procedure is key. For custom sequence, state assignment matters (use binary or Gray).

6. Logic Families: Compare TTL vs CMOS on delay, power, fan-out. Know totem-pole TTL NAND structure.

7. ADC: SAR working (binary search) is must. Flash is fastest but costly.

8. Display: LED (CA/CC) vs LCD (AC drive, multiplexing). Schmitt trigger hysteresis.

All past papers (Dec 2023, Dec 2024, Jun 2023) are covered in this blueprint. Focus on highlighted topics.