UNIT 1: Digital Circuits and Systems - Short Notes

I. Number Systems and Codes

Number Base Conversions

Definition: Converting a number from one radix (base) to another.

Key Rules:

• Integer Part: Repeated division by new base (for conversion to decimal) or repeated multiplication (for conversion from decimal).

• Fractional Part: Repeated multiplication by new base. Integer part of product becomes next digit.

• Between Non-Decimal Bases: Convert via decimal as intermediate.

Common Conversions:

Example - Fractional Conversion:

Convert $$\displaystyle (25.625)_{10} $$ to binary.

• Integer: $25 \div 2$ → remainders: 1, 0, 0, 1, 1 → $$\displaystyle (11001)_2 $$

• Fraction: $$\displaystyle 0.625 \times 2 = 1.25 $$ → 1, $$\displaystyle 0.25 \times 2 = 0.5 $$ → 0, $$\displaystyle 0.5 \times 2 = 1.0 $$ → 1 → $$\displaystyle (.101)_2 $$

• Result: $$\displaystyle \boxed{(11001.101)_2} $$

BCD (Binary Coded Decimal): Each decimal digit is represented by its 4-bit binary equivalent.

• Example: $$\displaystyle (25)_{10} = (0010\ 0101)_{BCD} $$

[!TIP] Common Pitfall: BCD is not a pure binary number. $$\displaystyle (25)_{10} = (11001)_2 $$ but $$\displaystyle (25)_{BCD} = 00100101 $$. Never perform arithmetic directly on BCD digits.

Code Converters

Design Steps:

1. Write truth table mapping input code (e.g., BCD) to output code (e.g., Excess-3).

2. Derive K-maps for each output bit.

3. Obtain minimal SOP/POS expressions.

4. Realize using logic gates (NAND/NOR for 2-level).

1. BCD to Excess-3 Code Converter

• Excess-3 Code: Binary code + 3 (i.e., add 0011 to BCD).

• Truth Table:

  | BCD Input (A B C D) | Excess-3 Output (W X Y Z) | | :--- | :--- | | 0000 | 0011 | | 0001 | 0100 | | ... | ... | | 1001 | 1100 |

  (Don't care for 1010-1111)

• Minimal Expressions (using K-map):

$$W = A + BD + BC$$

$$X = B'C + B'D + BC'D'$$

$$Y = C'D' + CD$$

$$Z = D'$$

2. Binary to Gray Code Converter

• Gray Code: Only one bit changes between successive numbers.

• Conversion Formulas:

$$G_3 = B_3$$

$$G_2 = B_3 \oplus B_2$$

$$G_1 = B_2 \oplus B_1$$

$$G_0 = B_1 \oplus B_0$$

• Logic Diagram: XOR gates in cascade.

3. Binary to 1's Complement Converter

• Simply invert all bits.

• Logic: $$\displaystyle Output_i = \overline{Input_i} $$ for each bit. Use NOT gates.

II. Boolean Algebra and Logic Simplification

Boolean Laws and Theorems

[!TIP] De Morgan's Theorem: To complement a complex expression, 1) invert each literal (A→A', 0→1, 1→0), 2) change AND to OR and OR to AND, 3) break the longest bar first.

Algebraic Simplification Example

Simplify: $$\displaystyle Z = A + A'B + A'B'C + A'B'C'D $$

1. $$\displaystyle Z = A + A'(B + B'C + B'C'D) $$ (Distributive)

2. $$\displaystyle Z = A + A'(B + B'(C + C'D)) $$ (Distributive)

3. $$\displaystyle Z = A + A'(B + B'(C + D)) $$ (Absorption: $$\displaystyle C + C'D = C + D $$)

4. $$\displaystyle Z = A + A'(B + B') $$ (Absorption: $$\displaystyle B + B'(C+D) = B + (C+D) $$ but $$\displaystyle B+B'=1 $$)

5. $$\displaystyle Z = A + A' \cdot 1 $$ (Inverse: $$\displaystyle B+B'=1 $$)

6. $$\displaystyle Z = A + A' $$ (Identity)

7. $$\displaystyle \boxed{Z = 1} $$ (Inverse)

Karnaugh Map (K-map) Minimization

Purpose: Graphical method for SOP/POS minimization.

• 2-var: 4 cells (00, 01, 11, 10 - Gray code order).

• 3-var: 8 cells (000 to 111).

• 4-var: 16 cells (0000 to 1111).

Grouping Rules:

• Groups must be powers of 2 (1, 2, 4, 8, 16).

• Groups must be rectangular and contiguous (adjacent horizontally/vertically, edges wrap).

• Aim for largest possible groups.

• Essential Prime Implicant (EPI): A minterm covered by only one prime implicant. Must be in final expression.

• Prime Implicant (PI): Largest group of 1's that cannot be combined further.

Result Forms:

• Minimal SOP: Sum of all EPIs + necessary PIs to cover remaining 1's.

• Minimal POS: Product of all EPIs (for 0's) + necessary PIs.

[!TIP] K-map Adjacency: Cells are adjacent if they differ by only one bit. Wraparound: top/bottom and left/right edges are adjacent.

Universal Gates

Definition: A gate type with which any Boolean function can be implemented.

• NAND and NOR are universal.

Realization using NAND only:

Realization using NOR only:

III. Combinational Logic Design

Encoders

Definition: Converts $$\displaystyle 2^n $$ input lines to $n$-bit binary code. One input active at a time.

8-to-3 Line Encoder

• Inputs: $$\displaystyle I_0 $$ to $$\displaystyle I_7 $$ (active-high)

• Outputs: $$\displaystyle A_2, A_1, A_0 $$ (binary code)

• Truth Table:

  | $$\displaystyle I_7 $$ | $$\displaystyle I_6 $$ | ... | $$\displaystyle I_0 $$ | $$\displaystyle A_2 $$ | $$\displaystyle A_1 $$ | $$\displaystyle A_0 $$ | | :--- | :--- | :--- | :--- | :--- | :--- | :--- | | 0 | 0 | ... | 1 | 0 | 0 | 0 | | 0 | 1 | ... | 0 | 1 | 1 | 0 | | ... | ... | ... | ... | ... | ... | ... | | 1 | 0 | ... | 0 | 1 | 1 | 1 |

• Logic Equations:

  $$\displaystyle A_0 = I_1 + I_3 + I_5 + I_7 $$

  $$\displaystyle A_1 = I_2 + I_3 + I_6 + I_7 $$

  $$\displaystyle A_2 = I_4 + I_5 + I_6 + I_7 $$

Priority Encoder

• Concept: If multiple inputs are active, output corresponds to highest-priority input (e.g., $$\displaystyle I_7 $$ has highest priority).

• Additional Outputs: V (Valid, 1 if any input active), GS (Group Signal, 1 if higher-priority input active).

• Design: Uses additional logic to inhibit lower-priority outputs.

Decoders

Definition: Converts $n$-bit binary input to $$\displaystyle 2^n $$ unique active output lines. n-to-$$\displaystyle 2^n $$ line decoder.

Implementation of Full Adder using Decoder

• Full Adder Truth Table:

  | A | B | Cin | Sum | Cout | | :--- | :--- | :--- | :--- | :--- | | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |

• Design: Use 3-to-8 decoder (inputs A, B, Cin). Connect minterms where Sum=1 to an OR gate for Sum output. Connect minterms where Cout=1 to another OR gate for Cout.

  • Sum = $$\displaystyle m_1 + m_2 + m_4 + m_7 $$

  • Cout = $$\displaystyle m_3 + m_5 + m_6 + m_7 $$

Multiplexers (MUX) and Demultiplexers (DEMUX)

4×1 Multiplexer

• Structure: 4 data inputs ($$\displaystyle D_0-D_3 $$), 2 select lines ($$\displaystyle S_1 S_0 $$), 1 output ($Y$).

• Operation: $$\displaystyle Y = D_i $$ where $i$ is binary number formed by $$\displaystyle S_1 S_0 $$.

• Truth Table:

  | $$\displaystyle S_1 $$ | $$\displaystyle S_0 $$ | $Y$ | | :--- | :--- | :--- | | 0 | 0 | $$\displaystyle D_0 $$ | | 0 | 1 | $$\displaystyle D_1 $$ | | 1 | 0 | $$\displaystyle D_2 $$ | | 1 | 1 | $$\displaystyle D_3 $$ |

Implementing Boolean Functions using MUX

• Method: Connect select lines to some variables. Data inputs ($$\displaystyle D_i $$) are either constants (0,1), variables, or their complements, based on K-map.

• Example: $$\displaystyle F(A,B,C,D) = \Sigma(0,3,5,6,8,9,11,13,15) $$ with A,C as select lines ($$\displaystyle S_1=A, S_0=C $$).

  1. Plot K-map with A,C as select variables.

  2. For each combination of A,C (00,01,10,11), determine expression for F in terms of B,D.

  3. Connect corresponding $$\displaystyle D_i $$ with that expression.

Specific Combinational Circuits

Full Adder

• Truth Table: (See Decoder section)

• K-map for Sum & Cout:

  • Sum = $$\displaystyle A \oplus B \oplus C_{in} $$

  • Cout = $$\displaystyle AB + AC_{in} + BC_{in} $$

• Gate-Level Diagram: Two half-adders + OR gate, or direct implementation using XOR/AND/OR.

Full Subtractor

• Inputs: A (minuend), B (subtrahend), Bin (borrow-in).

• Outputs: Diff (difference), Bout (borrow-out).

• Truth Table:

  | A | B | Bin | Diff | Bout | | :--- | :--- | :--- | :--- | :--- | | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 |

• Logic Equations:

  Diff = $A \oplus B \oplus Bin$

  Bout = $\overline{A}B + \overline{A}Bin + BBin$

Half Subtractor

• Inputs: A, B

• Outputs: Diff, Bout (borrow for this stage)

• Equations: Diff = $A \oplus B$, Bout = $\overline{A}B$

Design using Half Subtractors

Full Subtractor = Two Half Subtractors + OR gate.

• First HS: inputs A, B → outputs Diff1, Bout1.

• Second HS: inputs Diff1, Bin → outputs Diff (final), Bout2.

• Final Bout = Bout1 + Bout2.

IV. Sequential Logic Design

Flip-Flops

Definition: Basic 1-bit memory element. Changes state on clock edge (edge-triggered).

RS Flip-Flop (NAND-based, active-low inputs)

• Circuit: Two cross-coupled NAND gates.

• Truth Table (S', R' inputs):

  | S' | R' | Q(t+1) | Comment | | :--- | :--- | :--- | :--- | | 1 | 1 | Q(t) | No change (Hold) | | 0 | 1 | 1 | Set | | 1 | 0 | 0 | Reset | | 0 | 0 | ? | Invalid (both 0 violates $$\displaystyle \overline{Q}Q=0 $$)

• Applications: Simple latch, debouncing circuits.

JK Flip-Flop (Positive Edge-Triggered)

• Truth Table:

  | J | K | Q(t+1) | Comment | | :--- | :--- | :--- | :--- | | 0 | 0 | Q(t) | Hold | | 0 | 1 | 0 | Reset | | 1 | 0 | 1 | Set | | 1 | 1 | $\overline{Q(t)}$ | Toggle |

• Excitation Table: (What inputs cause a given transition?)

  | Q(t) → Q(t+1) | J | K | | :--- | :--- | :--- | | 0 → 0 | 0 | X | | 0 → 1 | 1 | X | | 1 → 0 | X | 1 | | 1 → 1 | X | 0 |

• Characteristic Equation: $$\displaystyle Q(t+1) = J\overline{Q} + \overline{K}Q $$

D Flip-Flop

• Truth Table:

  | D | Q(t+1) | | :--- | :--- | | 0 | 0 | | 1 | 1 |

• Characteristic Equation: $$\displaystyle Q(t+1) = D $$

• Use: Single delay element, data storage.

T Flip-Flop

• Truth Table:

  | T | Q(t+1) | | :--- | :--- | | 0 | Q(t) | | 1 | $\overline{Q(t)}$ |

• Characteristic Equation: $$\displaystyle Q(t+1) = T \oplus Q(t) $$

• Use: Frequency division by 2 (toggle mode).

Flip-Flop Conversions

Example: Convert D-FF to JK-FF

1. Objective: Create a circuit with JK inputs but D-FF behavior. Use D-FF's characteristic: $$\displaystyle Q_{next} = D $$.

2. JK's Desired Behavior: $$\displaystyle Q_{next} = J\overline{Q} + \overline{K}Q $$.

3. Equate: $$\displaystyle D = J\overline{Q} + \overline{K}Q $$.

4. Logic Diagram: Use NAND gates to implement $$\displaystyle D = J\overline{Q} + \overline{K}Q $$. (Use De Morgan: $$\displaystyle \overline{\overline{J\overline{Q}} \cdot \overline{\overline{K}Q}} $$).

5. Final Equations:

   $$\displaystyle D = JQ' + K'Q $$

   Realize with 2-input NANDs.

Counters

Asynchronous (Ripple) Counter

• MOD-4 DOWN Counter using T-FFs:

  • Connect $\overline{Q}$ of each FF to T of next lower-order FF.

  • Clock applied only to LSB FF.

  • Sequence: $11 \to 10 \to 01 \to 00 \to 11...$

  • State Diagram: 4 states (00,01,10,11).

Synchronous Counter Design (Custom Sequence)

Example: Sequence $0 \to 6 \to 7 \to 1 \to 4 \to 2 \to 0$ (3-bit, using JK-FFs)

1. State Assignment: Assign binary codes to states (e.g., 000=0, 110=6, 111=7, 001=1, 100=4, 010=2).

2. State Table:

   | Present State (Q2 Q1 Q0) | Next State (Q2+ Q1+ Q0+) | J2 K2 | J1 K1 | J0 K0 | | :--- | :--- | :--- | :--- | :--- | | 0 0 0 | 1 1 0 | 1 X | 1 X | 0 X | | 1 1 0 | 1 1 1 | 0 X | 0 X | 1 X | | ... | ... | ... | ... | ... |

3. Excitation Tables: Use JK excitation table to fill J,K columns from present/next states.

4. K-maps for J2,K2, J1,K1, J0,K0: Minimize each.

5. Logic Equations & Diagram: Implement minimized equations with gates, connect to FF clocks (common clock for synchronous).

MOD-N Counters

• MOD-6 Counter using D-FFs:

  • Design a synchronous counter for states 000 to 101 (6 states).

  • Use 3 D-FFs. State table for 0→1→2→3→4→5→0.

  • Derive D-input equations from state table ($$\displaystyle D_i = Q_{next} $$).

  • Reset: Use combinational logic to detect state 110 (6) and asynchronously reset all FFs to 000.

Special Counters

• Ring Counter: n D-FFs in circular shift. Output of last FF feeds input of first. MOD-n, only one '1' at a time.

• Johnson Counter (Twisted Ring): Output of last FF inverted before feeding first. MOD-2n, pattern has n '0's and n '1's.

Registers

Universal Shift Register

• Mode Control ($$\displaystyle S_1 S_0 $$):

  | $$\displaystyle S_1 $$ | $$\displaystyle S_0 $$ | Operation | | :--- | :--- | :--- | | 0 | 0 | Hold (No change) | | 0 | 1 | Shift Right (Serial In → MSB) | | 1 | 0 | Shift Left (LSB → Serial Out) | | 1 | 1 | Parallel Load |

• Structure: n D-FFs. Each FF's D input selected via multiplexers controlled by $$\displaystyle S_1,S_0 $$. MUX inputs: parallel data, left neighbor Q, right neighbor Q, own Q (hold).

Serial vs Parallel Registers

V. Logic Families

TTL (Transistor-Transistor Logic)

Basic Totem-Pole TTL 2-input NAND Gate

• Input Stage: Multi-emitter input transistor (T1). Any low input saturates T1.

• Phase Splitter: T2. Inverts signal from T1.

• Output Stage: Totem-pole (T3 pull-up, T4 pull-down). Provides low output impedance.

• Operation (Inputs A,B both HIGH):

  1. T1 off (emitter-base reverse biased).

  2. T2 on (base current from R1 via T1 collector).

  3. T3 off (base-emitter reverse biased via T2), T4 on → Output LOW.

• Output HIGH: Any input LOW → T1 on → T2 off → T3 on, T4 off.

2-input TTL NOR Gate

• Structure: Input stage is parallel (unlike NAND's multi-emitter). T1a and T1b are separate transistors with emitters tied to ground.

• Operation: Both inputs HIGH → both T1a, T1b off → T2 on → T4 on → Output LOW.

  Any input LOW → corresponding T1 on → T2 off → T3 on → Output HIGH.

CMOS Logic

Basic CMOS Inverter

• Structure: Complementary pair: pMOS (upper, pull-up) and nMOS (lower, pull-down).

• Operation:

  • Input LOW: pMOS ON, nMOS OFF → Output HIGH (VDD).

  • Input HIGH: pMOS OFF, nMOS ON → Output LOW (GND).

• Key Feature: Static power dissipation ≈ 0 (except during switching). High input impedance.

Other Logic Families

PMOS 2-input NOR Gate

• Structure: All pMOS transistors in parallel between output and VDD.

• Logic: Output = NOR(A,B) = (A+B)'.

  • Both inputs LOW → both pMOS ON → Output HIGH.

  • Any input HIGH → corresponding pMOS OFF → Output LOW (via load device).

• Disadvantage: Requires enhancement-load (always-on pMOS) or depletion-load. Slow, high power.

RTL vs DTL vs TTL

ECL (Emitter-Coupled Logic)

• Principle: Operates in active region (never saturates). Uses differential amplifier.

• Characteristics:

  • Very high speed (propagation delay ~1ns).

  • High power dissipation.

  • Low noise margin.

  • Outputs are complementary (wired-OR possible).

Comparative Analysis: TTL vs CMOS vs ECL

VI. Data Conversion and Output Devices

Analog-to-Digital Converters (ADCs)

Types: Flash (Parallel), Successive Approximation, Dual-Slope, Sigma-Delta.

Successive-Approximation ADC (SAR ADC)

• Block Diagram: Sample/Hold → Comparator → Successive Approximation Register (SAR) → DAC → Control Logic.

• Working Principle:

  1. Sample: Input voltage $$\displaystyle V_{in} $$ held by S/H circuit.

  2. Approximate: SAR starts with MSB=1, others=0. DAC converts this digital code to analog $$\displaystyle V_{DAC} $$.

  3. Compare: Comparator compares $$\displaystyle V_{in} $$ vs $$\displaystyle V_{DAC} $$.

     • If $$\displaystyle V_{in} > V_{DAC} $$: MSB remains 1.

     • If $$\displaystyle V_{in} < V_{DAC} $$: MSB cleared to 0.

  4. Iterate: SAR sets next bit to 1, compares again. Repeats for all bits (n cycles for n-bit).

  5. Result: SAR output is digital equivalent of $$\displaystyle V_{in} $$.

• Speed: Moderate (n clock cycles). Accuracy: High.

Flash ADC (Parallel ADC)

• Circuit: $$\displaystyle 2^n - 1 $$ comparators for n-bit. Each compares $$\displaystyle V_{in} $$ with a reference from resistor ladder.

• Operation: Comparator outputs go to priority encoder. Highest-order comparator with HIGH output determines digital code.

• Advantage: Fastest (propagation delay only through encoder).

• Disadvantage: Expensive (components double for each bit), high power.

Schmitt Trigger

• Circuit (Op-amp): Positive feedback from output to non-inverting input. Hysteresis.

• Working:

  • Upper Threshold ($$\displaystyle V_{UT} $$): Output switches from LOW to HIGH when $$\displaystyle V_{in} > V_{UT} $$.

  • Lower Threshold ($$\displaystyle V_{LT} $$): Output switches from HIGH to LOW when $$\displaystyle V_{in} < V_{LT} $$.

  • Hysteresis Width: $$\displaystyle V_{UT} - V_{LT} $$.

• Applications: Noise discriminator, square wave generator, debouncing.

Display Devices

LED 7-Segment Display

• Structure: 7 LEDs (a-g) arranged in '8' shape. + decimal point (dp).

• Common Anode: All anodes tied to VCC. Segment lights with LOW (sink current).

• Common Cathode: All cathodes tied to GND. Segment lights with HIGH (source current).

• Decoder/Driver: BCD-to-7-segment decoder (e.g., 7447) converts 4-bit BCD to segment signals.

LCD (Liquid Crystal Display)

• Working Principle: Liquid crystal twists polarized light when voltage applied. Requires AC drive (no DC).

• Structure: Two polarizers (crossed), glass plates with electrodes, liquid crystal layer.

• Typical Difference from LED:

  | Feature | LED | LCD | | :--- | :--- | :--- | | Power | Higher (per segment) | Very Low | | Viewing Angle | Wide | Limited | | Brightness | Bright (self-emissive) | Requires backlight (transmissive) | | Drive | DC | AC (to prevent degradation) | | Response | Fast | Slower |

Clock Generation

Astable Multivibrator (using 555 Timer)

• Circuit: 555 timer with external R1, R2, C.

• Operation:

  • Capacitor C charges through R1+R2 until $$\displaystyle 2/3 V_{CC} $$ → Threshold triggers → discharge pin active → C discharges through R2 until $$\displaystyle 1/3 V_{CC} $$ → Trigger resets → cycle repeats.

• Frequency: $$\displaystyle f = \frac{1.44}{(R1 + 2R2)C} $$

• Duty Cycle: $$\displaystyle > 50\% $$ (controlled by R1, R2 ratio).

• Waveform: Square wave at pin 3 output.

[!TIP] RGPV Exam Focus: Be prepared to derive frequency formula for 555 astable, draw circuit, and explain charging/discharging paths.