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CY-304 ยท Digital Systems/Quick Revision Short Notes

Digital Systems (CY-304) - Unit 4 Short Notes

How unit 4 is examined

Converters (flash, SAR, dual slope, R-2R, numericals), sample and hold, multivibrators, Schmitt trigger and the 555 timer, then logic families (TTL, NMOS, PMOS, CMOS) and TTL-to-MOS interfacing; the A/D-D/A, Schmitt, 555, logic-family and interfacing topics carry most marks.

Introduction to A/D & D/A convertors & their types

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. <mark>An A/D converter changes a continuous analog voltage into an n-bit binary word, and a D/A converter changes an n-bit binary word back into an analog voltage.</mark>

Key points.

  1. Resolution (step size) of an n-bit converter with full-scale range $V_{FS}$ is $V_{FS}/2^n$; more bits give a finer step.
  2. Nyquist sampling theorem: the sampling rate must satisfy $f_s \ge 2f_m$ (highest signal frequency) or aliasing occurs; a low-pass filter reconstructs the signal.
  3. Shannon's theorem: the maximum error-free data rate of a channel is $C = B\log_2(1+S/N)$ bits/s, where B is bandwidth and S/N is the signal-to-noise ratio.
  4. Flash (simultaneous) ADC is the fastest because all comparators work at once, but it needs $2^n-1$ comparators, so it is costly for many bits.
  5. Successive approximation ADC needs only one comparator and takes n clock cycles, so it is a good speed/cost compromise.
  6. Dual slope ADC is slow but accurate and noise-immune, and its result does not depend on R or C.
  7. R-2R DAC needs only two resistor values, so it is easier to make accurately than a binary-weighted DAC.

Diagram (flash ADC). The 3-bit flash ADC uses 8 equal resistors, 7 comparators and a priority encoder. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-01" viewBox="0 0 553 252" width="553" height="252" role="img" aria-label="3-bit flash ADC: reference ladder, 7 comparators, priority encoder; a 2-bit version has 3 comparators"><style>#dsfig-u4-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-01 .t{fill:#16181D;font-weight:500}#dsfig-u4-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-01 .dot{fill:#16181D}#dsfig-u4-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-01 .ah{fill:#454C5A}#dsfig-u4-01 .ah.hi{fill:#2340B8}#dsfig-u4-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-01 .e{stroke:#B1B7C3}html.dark #dsfig-u4-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-01 .t{fill:#E6E8ED}html.dark #dsfig-u4-01 .t.inv{fill:#0F1115}html.dark #dsfig-u4-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-01 .dot{fill:#E6E8ED}html.dark #dsfig-u4-01 .ann{fill:#8FA3FF}html.dark #dsfig-u4-01 .lbl{fill:#858D9C}html.dark #dsfig-u4-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-01 .ah{fill:#B1B7C3}html.dark #dsfig-u4-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L105,40" marker-end="url(#ah15)"/><path class="e" d="M145,40 L234,40" marker-end="url(#ah15)"/><path class="e" d="M274,40 L363,40" marker-end="url(#ah15)"/><path class="e" d="M403,40 L492,40" marker-end="url(#ah15)"/><path class="e" d="M137.4,196.8 L242.4,56.8" marker-end="url(#ah15)"/><g class="wl"><rect x="163.4" y="31" width="54.3" height="18" rx="9"/><text class="t" x="190.5" y="40" dy=".35em" text-anchor="middle">k*Vr/8</text></g><g class="wl"><rect x="296" y="31" width="47.1" height="18" rx="9"/><text class="t" x="319.5" y="40" dy=".35em" text-anchor="middle">D1-D7</text></g><g class="wl"><rect x="421.4" y="31" width="54.3" height="18" rx="9"/><text class="t" x="448.5" y="40" dy=".35em" text-anchor="middle">B2B1B0</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vr</text><circle class="n" cx="126" cy="40" r="18"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">Lad</text><circle class="n" cx="255" cy="40" r="18"/><text class="t" x="255" y="40" dy=".35em" text-anchor="middle">Cmp</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Enc</text><circle class="n" cx="513" cy="40" r="18"/><text class="t" x="513" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="126" cy="212" r="18"/><text class="t" x="126" y="212" dy=".35em" text-anchor="middle">Vin</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">3-bit flash ADC: reference ladder, 7 comparators, priority encoder; a 2-bit version has 3 comparators</figcaption></figure> Flash operation. The ladder gives references $Vr/8, 2Vr/8, \dots, 7Vr/8$. Every comparator whose reference is below $V_{in}$ outputs 1, and the priority encoder converts the highest 1 into a 3-bit code in one step.

Diagram (SAR ADC). <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-02" viewBox="0 0 510 252" width="510" height="252" role="img" aria-label="8-bit SAR ADC: sample-hold, comparator, SAR register, 8-bit DAC, clock"><style>#dsfig-u4-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-02 .t{fill:#16181D;font-weight:500}#dsfig-u4-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-02 .dot{fill:#16181D}#dsfig-u4-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-02 .ah{fill:#454C5A}#dsfig-u4-02 .ah.hi{fill:#2340B8}#dsfig-u4-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-02 .e{stroke:#B1B7C3}html.dark #dsfig-u4-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-02 .t{fill:#E6E8ED}html.dark #dsfig-u4-02 .t.inv{fill:#0F1115}html.dark #dsfig-u4-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-02 .dot{fill:#E6E8ED}html.dark #dsfig-u4-02 .ann{fill:#8FA3FF}html.dark #dsfig-u4-02 .lbl{fill:#858D9C}html.dark #dsfig-u4-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-02 .ah{fill:#B1B7C3}html.dark #dsfig-u4-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L105,40" marker-end="url(#ah16)"/><path class="e" d="M145,40 L216.8,40" marker-end="url(#ah16)"/><path class="e" d="M256.8,40 L328.6,40" marker-end="url(#ah16)"/><path class="e" d="M368.6,40 L449,40" marker-end="url(#ah16)"/><path class="e" d="M344.1,58.2 L304,191.9" marker-end="url(#ah16)"/><path class="e" d="M291.7,194.1 L244.7,59.8" marker-end="url(#ah16)"/><g class="wl"><rect x="251.1" y="117" width="33.6" height="18" rx="9"/><text class="t" x="267.9" y="126" dy=".35em" text-anchor="middle">Vda</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vin</text><circle class="n" cx="126" cy="40" r="18"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">SH</text><circle class="n" cx="237.8" cy="40" r="18"/><text class="t" x="237.8" y="40" dy=".35em" text-anchor="middle">Cmp</text><circle class="n" cx="349.6" cy="40" r="18"/><text class="t" x="349.6" y="40" dy=".35em" text-anchor="middle">SAR</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="298" cy="212" r="18"/><text class="t" x="298" y="212" dy=".35em" text-anchor="middle">DAC</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">8-bit SAR ADC: sample-hold, comparator, SAR register, 8-bit DAC, clock</figcaption></figure> SAR steps. The SAR sets the MSB to 1, the DAC output is compared with $V_{in}$, and the bit is kept if $V_{da} \le V_{in}$ and cleared otherwise. The same is done for each next bit, so an 8-bit result takes 8 clock cycles (binary search).

Dual slope ADC. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-03" viewBox="0 0 467 252" width="467" height="252" role="img" aria-label="Dual slope ADC: integrator, comparator, control logic, counter"><style>#dsfig-u4-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-03 .t{fill:#16181D;font-weight:500}#dsfig-u4-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-03 .dot{fill:#16181D}#dsfig-u4-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-03 .ah{fill:#454C5A}#dsfig-u4-03 .ah.hi{fill:#2340B8}#dsfig-u4-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-03 .e{stroke:#B1B7C3}html.dark #dsfig-u4-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-03 .t{fill:#E6E8ED}html.dark #dsfig-u4-03 .t.inv{fill:#0F1115}html.dark #dsfig-u4-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-03 .dot{fill:#E6E8ED}html.dark #dsfig-u4-03 .ann{fill:#8FA3FF}html.dark #dsfig-u4-03 .lbl{fill:#858D9C}html.dark #dsfig-u4-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-03 .ah{fill:#B1B7C3}html.dark #dsfig-u4-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L148,40" marker-end="url(#ah17)"/><path class="e" d="M188,40 L277,40" marker-end="url(#ah17)"/><path class="e" d="M317,40 L406,40" marker-end="url(#ah17)"/><path class="e" d="M427,59 L427,191" marker-end="url(#ah17)"/><path class="e" d="M408,40 L61,40" marker-end="url(#ah17)"/><g class="wl"><rect x="66.6" y="31" width="75.9" height="18" rx="9"/><text class="t" x="104.5" y="40" dy=".35em" text-anchor="middle">Vin/-Vref</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">S</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">Int</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">Cmp</text><circle class="n" cx="427" cy="40" r="18"/><text class="t" x="427" y="40" dy=".35em" text-anchor="middle">Ctl</text><circle class="n" cx="427" cy="212" r="18"/><text class="t" x="427" y="212" dy=".35em" text-anchor="middle">Cnt</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Dual slope ADC: integrator, comparator, control logic, counter</figcaption></figure> Run-up integrates $V_{in}$ for fixed time $T_1$. Run-down integrates $-V_{ref}$ until the output returns to zero in time $T_2$. Equating charge gives $T_2 = T_1 V_{in}/V_{ref}$, so R and C cancel, and the counter holds $T_2$ as the digital output.

R-2R DAC. A ladder of R and 2R resistors with switches $b_3\dots b_0$ to $V_{ref}$ or ground feeds an inverting op-amp. At every node the resistance looking toward the end is R, so each bit's current halves as it moves toward the MSB: $$V_{out} = -V_{ref}\left(\frac{b_3}{2}+\frac{b_2}{4}+\frac{b_1}{8}+\frac{b_0}{16}\right) = -V_{ref}\frac{D}{2^n}$$

Example (Jun 2023). Need $5/2^n \le 0.005$, so $2^n \ge 1000$. Since $2^9=512$ and $2^{10}=1024$: n = 10 bits.

Example (Dec 2023). $V_{out}=D\times 10$ mV. 10001010 = 138, so 1380 mV; 00010000 = 16, so 160 mV. Answers: 1.38 V and 0.16 V.

Answer frame. Open with the definition; for flash/SAR/dual slope/R-2R draw the named block diagram with all labels; develop principle, steps, timing, then the formula; close with the advantage (flash fastest, SAR n clocks, dual slope accurate, R-2R two resistor values). For the note question give one paragraph each on A/D-D/A, Nyquist and Shannon.

Pitfall: For accuracy questions use $V_{FS}/2^n \le$ step and round n up, never down.

Asked: [7 marks] (May 2019, Dec 2020) Discuss 3-bit flash A/D converter; describe 2-bit simultaneous A/D converter. Asked: [14 marks] (Nov 2022) Notes on A/D and D/A convertors, CMOS logic, Shannon's theorem, Nyquist sampling theorem. Asked: [7 marks] (Dec 2024) With a neat diagram explain the operation of R-2R DAC. Asked: [7 marks] (Jun 2020) With a neat diagram, explain 8-bit successive approximation ADC. Asked: [7 marks] (Jun 2023) An n-bit ADC converts 0-5 V to accuracy of 5 mV; find n. Asked: [7 marks] (Dec 2023) 8-bit D/A of 10 mV/bit resolution; find output for 10001010 and 00010000. Asked: [7 marks] (Dec 2023) Describe the operation of dual slope A/D converter with diagrams.

Sample and hold circuits

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>A sample and hold (S/H) circuit samples the analog input on command and holds that value constant on a capacitor so the ADC can convert it.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-04" viewBox="0 0 542.8 252" width="542.8" height="252" role="img" aria-label="S/H: analog switch, hold capacitor C, input and output op-amp buffers, control clock"><style>#dsfig-u4-04 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-04 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-04 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-04 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-04 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-04 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-04 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-04 .t{fill:#16181D;font-weight:500}#dsfig-u4-04 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-04 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-04 .dot{fill:#16181D}#dsfig-u4-04 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-04 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-04 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-04 .ah{fill:#454C5A}#dsfig-u4-04 .ah.hi{fill:#2340B8}#dsfig-u4-04 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-04 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-04 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-04 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-04 .e{stroke:#B1B7C3}html.dark #dsfig-u4-04 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-04 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-04 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-04 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-04 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-04 .t{fill:#E6E8ED}html.dark #dsfig-u4-04 .t.inv{fill:#0F1115}html.dark #dsfig-u4-04 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-04 .dot{fill:#E6E8ED}html.dark #dsfig-u4-04 .ann{fill:#8FA3FF}html.dark #dsfig-u4-04 .lbl{fill:#858D9C}html.dark #dsfig-u4-04 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-04 .ah{fill:#B1B7C3}html.dark #dsfig-u4-04 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-04 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-04 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-04 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L130.8,40" marker-end="url(#ah18)"/><path class="e" d="M170.8,40 L235.6,40" marker-end="url(#ah18)"/><path class="e" d="M289.6,40 L356,40" marker-end="url(#ah18)"/><path class="e" d="M410,40 L474.8,40" marker-end="url(#ah18)"/><path class="e" d="M263.6,66 L263.6,193"/><path class="e" d="M151.8,193 L151.8,61" marker-end="url(#ah18)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vin</text><circle class="n" cx="151.8" cy="40" r="18"/><text class="t" x="151.8" y="40" dy=".35em" text-anchor="middle">SW</text><rect class="n" x="238.6" y="25" width="50" height="30" rx="15"/><text class="t" x="263.6" y="40" dy=".35em" text-anchor="middle">Buf1</text><rect class="n" x="359" y="25" width="50" height="30" rx="15"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Buf2</text><circle class="n" cx="495.8" cy="40" r="18"/><text class="t" x="495.8" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="263.6" cy="212" r="18"/><text class="t" x="263.6" y="212" dy=".35em" text-anchor="middle">Cap</text><circle class="n" cx="151.8" cy="212" r="18"/><text class="t" x="151.8" y="212" dy=".35em" text-anchor="middle">Clk</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">S/H: analog switch, hold capacitor C, input and output op-amp buffers, control clock</figcaption></figure>

Key points.

  1. In sample mode the control pulse closes the switch, and the capacitor charges quickly so the output follows the input.
  2. In hold mode the switch opens and the capacitor keeps the last voltage, so the output stays constant.
  3. The input buffer has low output resistance so the capacitor charges fast, and the output buffer has very high input resistance so the capacitor does not discharge.
  4. It is needed because the ADC needs a fixed input during conversion time; a changing input would give wrong bits, especially in SAR ADCs.
  5. Acquisition time is the time to charge to the input, aperture time is the delay in opening the switch, and droop is the slow voltage loss during hold.

Answer frame. Open with the definition; draw the diagram plus waveforms (input, control pulse, staircase output); explain sample then hold mode; close with the need in ADC and the three parameters.

Asked: [7 marks] (Nov 2018, Jun 2023, Dec 2025) Discuss / explain the working of sample and hold circuit; why is it required in ADC systems.

Voltage to Frequency & Frequency to Voltage conversion

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Low weight</span>

Definition. <mark>A V-F converter produces an output pulse train whose frequency is proportional to the input voltage; an F-V converter does the reverse.</mark>

Key points.

  1. An op-amp integrator charges its capacitor with a current $V_{in}/R$, so the output ramps at a rate proportional to $V_{in}$.
  2. When the ramp reaches the threshold of the comparator, the comparator fires and a reset switch (or monostable) discharges the capacitor, producing one output pulse.
  3. A larger $V_{in}$ ramps faster and gives more pulses per second, so $f_{out}=V_{in}/(RCV_{th}) \propto V_{in}$.
  4. In an F-V converter each input pulse triggers a monostable of fixed width, and a low-pass RC filter averages the pulses so that $V_{out} \propto f_{in}$.

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-05" viewBox="0 0 467 252" width="467" height="252" role="img" aria-label="V-F converter: integrator, comparator, reset switch"><style>#dsfig-u4-05 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-05 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-05 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-05 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-05 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-05 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-05 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-05 .t{fill:#16181D;font-weight:500}#dsfig-u4-05 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-05 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-05 .dot{fill:#16181D}#dsfig-u4-05 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-05 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-05 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-05 .ah{fill:#454C5A}#dsfig-u4-05 .ah.hi{fill:#2340B8}#dsfig-u4-05 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-05 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-05 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-05 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-05 .e{stroke:#B1B7C3}html.dark #dsfig-u4-05 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-05 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-05 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-05 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-05 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-05 .t{fill:#E6E8ED}html.dark #dsfig-u4-05 .t.inv{fill:#0F1115}html.dark #dsfig-u4-05 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-05 .dot{fill:#E6E8ED}html.dark #dsfig-u4-05 .ann{fill:#8FA3FF}html.dark #dsfig-u4-05 .lbl{fill:#858D9C}html.dark #dsfig-u4-05 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-05 .ah{fill:#B1B7C3}html.dark #dsfig-u4-05 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-05 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-05 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-05 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah19" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh19" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L148,40" marker-end="url(#ah19)"/><path class="e" d="M188,40 L277,40" marker-end="url(#ah19)"/><path class="e" d="M317,40 L406,40" marker-end="url(#ah19)"/><path class="e" d="M298,59 L298,191" marker-end="url(#ah19)"/><path class="e" d="M286.6,196.8 L181.6,56.8" marker-end="url(#ah19)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vin</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">Int</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">Cmp</text><circle class="n" cx="427" cy="40" r="18"/><text class="t" x="427" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="298" cy="212" r="18"/><text class="t" x="298" y="212" dy=".35em" text-anchor="middle">Rst</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">V-F converter: integrator, comparator, reset switch</figcaption></figure>

Asked: [7 marks] (Jun 2023) With circuit diagram explain the working of V-F converters.

Multivibrators: Bistable, Monostable, Astable

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>A multivibrator is a two-state regenerative circuit: bistable has two stable states, monostable has one stable state and one temporary state, and astable has none and oscillates.</mark>

Key points.

  1. A bistable multivibrator (flip-flop) stays in either state until a trigger pulse flips it, so it is used as a memory element and in counters.
  2. A monostable multivibrator rests in its stable state, a trigger pulse throws it to the quasi-stable state, and it returns after the time $T=0.693RC$ (with a transistor circuit) or $T=1.1RC$ (555 timer), giving a pulse of fixed width.
  3. Monostable applications are pulse stretching, time delay/timer, switch debouncing, frequency dividing and pulse-width generation.
  4. An astable multivibrator is a free-running square-wave generator: the two transistors switch alternately as the coupling capacitors charge and discharge.
  5. Astable output frequency for a symmetrical transistor circuit is $f\approx 1/(1.386RC)$; with a 555, $f=1.44/((R_A+2R_B)C)$.

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.ptr{fill:#8FA3FF}html.dark #dsfig-u4-06 .ah{fill:#B1B7C3}html.dark #dsfig-u4-06 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-06 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-06 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-06 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah20" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh20" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M55.8,115.5 L151.5,51.6" marker-end="url(#ah20)"/><path class="e" d="M169,61 L169,191" marker-end="url(#ah20)" marker-start="url(#ah20)"/><path class="e" d="M184.8,201.5 L280.5,137.6" marker-end="url(#ah20)"/><g class="wl"><rect x="73.8" y="74" width="61.5" height="18" rx="9"/><text class="t" x="104.5" y="83" dy=".35em" text-anchor="middle">trigger</text></g><g class="wl"><rect x="155.8" y="117" width="26.4" height="18" rx="9"/><text class="t" x="169" y="126" dy=".35em" text-anchor="middle">RC</text></g><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">T</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">Q1</text><circle class="n" cx="169" cy="212" r="18"/><text class="t" x="169" y="212" dy=".35em" text-anchor="middle">Q2</text><circle class="n" cx="298" cy="126" r="18"/><text class="t" x="298" y="126" dy=".35em" text-anchor="middle">Out</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Monostable: trigger switches Q1/Q2, the RC coupling sets the pulse width T</figcaption></figure> <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-07" viewBox="0 0 381 252" width="381" height="252" role="img" aria-label="Astable: two transistors cross-coupled by capacitors, no stable state"><style>#dsfig-u4-07 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-07 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-07 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-07 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-07 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-07 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-07 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-07 .t{fill:#16181D;font-weight:500}#dsfig-u4-07 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-07 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-07 .dot{fill:#16181D}#dsfig-u4-07 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-07 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-07 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-07 .ah{fill:#454C5A}#dsfig-u4-07 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rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-07 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah21" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh21" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M53.4,112.6 L111.2,54.8" marker-end="url(#ah21)"/><path class="e" d="M139.4,53.4 L197.2,111.2" marker-end="url(#ah21)"/><path class="e" d="M198.6,139.4 L140.8,197.2" marker-end="url(#ah21)"/><path class="e" d="M112.6,198.6 L54.8,140.8" marker-end="url(#ah21)"/><path class="e" d="M231,126 L320,126" marker-end="url(#ah21)"/><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">Q1</text><circle class="n" cx="212" cy="126" r="18"/><text class="t" x="212" y="126" dy=".35em" text-anchor="middle">Q2</text><circle class="n" cx="126" cy="40" r="18"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">C1</text><circle class="n" cx="126" cy="212" r="18"/><text class="t" x="126" y="212" dy=".35em" text-anchor="middle">C2</text><circle class="n" cx="341" cy="126" r="18"/><text class="t" x="341" y="126" dy=".35em" text-anchor="middle">Out</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Astable: two transistors cross-coupled by capacitors, no stable state</figcaption></figure> Bistable: two cross-coupled transistors with direct resistor coupling; a set or reset pulse gives a permanent state.

Answer frame. Monostable: define, draw circuit and input/output waveform, explain trigger, quasi-stable period $T$, then list applications. Astable: define as free-running, draw circuit and square wave, explain alternate charge/discharge, give the frequency formula.

Asked: [7 marks] (May 2019) Draw and explain monostable multivibrator. Asked: [7 marks] (Dec 2020) Describe the application of monostable multivibrator. Asked: [7 marks] (Jun 2020) Draw and explain astable multivibrator.

Schmitt trigger

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Definition. <mark>A Schmitt trigger is a comparator with positive feedback that has two different threshold voltages, the upper (UTP) and lower (LTP) trip points, so its output switches with hysteresis.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-08" viewBox="0 0 424 252" width="424" height="252" role="img" aria-label="Op-amp Schmitt trigger: input to inverting pin, R1 and R2 feed a fraction of output to the non-inverting pin (R1 to ground or Vref)"><style>#dsfig-u4-08 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-08 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-08 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-08 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-08 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-08 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-08 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-08 .t{fill:#16181D;font-weight:500}#dsfig-u4-08 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-08 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-08 .dot{fill:#16181D}#dsfig-u4-08 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-08 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-08 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-08 .ah{fill:#454C5A}#dsfig-u4-08 .ah.hi{fill:#2340B8}#dsfig-u4-08 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-08 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-08 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-08 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-08 .e{stroke:#B1B7C3}html.dark #dsfig-u4-08 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-08 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-08 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-08 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-08 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-08 .t{fill:#E6E8ED}html.dark #dsfig-u4-08 .t.inv{fill:#0F1115}html.dark #dsfig-u4-08 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-08 .dot{fill:#E6E8ED}html.dark #dsfig-u4-08 .ann{fill:#8FA3FF}html.dark #dsfig-u4-08 .lbl{fill:#858D9C}html.dark #dsfig-u4-08 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-08 .ah{fill:#B1B7C3}html.dark #dsfig-u4-08 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-08 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-08 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-08 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah22" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh22" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L191,40" marker-end="url(#ah22)"/><path class="e" d="M231,40 L363,40" marker-end="url(#ah22)"/><path class="e" d="M370.6,53.4 L226.8,197.2" marker-end="url(#ah22)"/><path class="e" d="M231,212 L320,212" marker-end="url(#ah22)"/><path class="e" d="M329.6,196.8 L224.6,56.8" marker-end="url(#ah22)"/><g class="wl"><rect x="109.2" y="31" width="33.6" height="18" rx="9"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">-in</text></g><g class="wl"><rect x="259.7" y="203" width="33.6" height="18" rx="9"/><text class="t" x="276.5" y="212" dy=".35em" text-anchor="middle">+in</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vin</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">Amp</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">R2</text><circle class="n" cx="341" cy="212" r="18"/><text class="t" x="341" y="212" dy=".35em" text-anchor="middle">R1</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Op-amp Schmitt trigger: input to inverting pin, R1 and R2 feed a fraction of output to the non-inverting pin (R1 to ground or Vref)</figcaption></figure>

Key points.

  1. The positive feedback fraction is $\beta=R_1/(R_1+R_2)$, where $R_1$ connects the non-inverting pin to $V_{ref}$ (or ground) and $R_2$ to the output.
  2. When the output is $+V_{sat}$, the trip point is $V_{UT}=\beta V_{sat}+(1-\beta)V_{ref}$; when the output is $-V_{sat}$, it is $V_{LT}=-\beta V_{sat}+(1-\beta)V_{ref}$.
  3. With $V_{ref}=0$: $V_{UT}=+V_{sat}R_1/(R_1+R_2)$ and $V_{LT}=-V_{sat}R_1/(R_1+R_2)$.
  4. Input rising above UT drives the output to $-V_{sat}$; input falling below LT drives it to $+V_{sat}$; between them the output holds its state.
  5. Hysteresis voltage is $V_H=V_{UT}-V_{LT}=2\beta V_{sat}$, which gives noise immunity because noise smaller than $V_H$ cannot cause false switching.
  6. Applications are squaring a slow or sine wave, wave shaping, noise removal in digital signals and a level detector.

Example (Dec 2023). Design for $V_{UT}=2$ V, $V_{LT}=-1$ V, $V_{sat}=\pm13$ V. $V_{UT}-V_{LT}=26\beta=3 \Rightarrow \beta=3/26$, so $R_1/(R_1+R_2)=3/26 \Rightarrow R_2/R_1=23/3$. $(1-\beta)V_{ref}=V_{UT}-13\beta=2-1.5=0.5 \Rightarrow V_{ref}=0.5\times 26/23=0.565$ V. Check: $V_{LT}=0.5-1.5=-1$ V. Answer: R1 = 3 kฮฉ, R2 = 23 kฮฉ, Vref = 0.565 V (any pair in ratio 3:23).

Answer frame. Open with the definition and hysteresis; draw circuit plus the Vout-Vin hysteresis loop (UT, LT, ยฑVsat); develop working, formulas, then the numerical; close with the wave-shaping and noise-immunity uses. For the 14-mark "draw and explain" add waveforms.

Asked: [14 marks] (Jun 2023, Dec 2024) Short notes on any two: Schmitt trigger, PLA, look ahead carry generator, Karnaugh map. Asked: [7 marks] (Dec 2023) Explain how a Schmitt trigger works with a neat diagram; design one with UT 2 V, LT -1 V, Vsat ยฑ13 V. Asked: [14 marks] (Nov 2019) Draw and explain A/D converter, bistable multivibrator and Schmitt trigger.

IC 555 & its applications

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Definition. <mark>The 555 is an 8-pin timer IC containing two comparators, an SR flip-flop, a discharge transistor and a three-resistor divider, used as a monostable or astable multivibrator.</mark>

Diagram (internal). <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-09" viewBox="0 0 553 338" width="553" height="338" role="img" aria-label="555 internal: 3 x 5k divider, upper comparator (threshold), lower comparator (trigger), SR flip-flop, output stage, discharge transistor"><style>#dsfig-u4-09 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-09 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-09 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-09 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-09 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-09 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-09 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-09 .t{fill:#16181D;font-weight:500}#dsfig-u4-09 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-09 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-09 .dot{fill:#16181D}#dsfig-u4-09 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text-anchor="middle">R</text></g><g class="wl"><rect x="309.9" y="203" width="19.2" height="18" rx="9"/><text class="t" x="319.5" y="212" dy=".35em" text-anchor="middle">S</text></g><g class="wl"><rect x="438.9" y="160" width="19.2" height="18" rx="9"/><text class="t" x="448.5" y="169" dy=".35em" text-anchor="middle">3</text></g><g class="wl"><rect x="374.4" y="224.5" width="19.2" height="18" rx="9"/><text class="t" x="384" y="233.5" dy=".35em" text-anchor="middle">7</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Th</text><circle class="n" cx="40" cy="298" r="18"/><text class="t" x="40" y="298" dy=".35em" text-anchor="middle">Tr</text><circle class="n" cx="169" cy="169" r="18"/><text class="t" x="169" y="169" dy=".35em" text-anchor="middle">Div</text><circle class="n" cx="255" cy="83" r="18"/><text class="t" x="255" y="83" dy=".35em" text-anchor="middle">C1</text><circle class="n" cx="255" cy="255" r="18"/><text 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Key points.

  1. The divider of three 5 kฮฉ resistors sets $2V_{cc}/3$ at the upper comparator and $V_{cc}/3$ at the lower comparator (pin 5 control voltage can change them).
  2. If trigger (pin 2) falls below $V_{cc}/3$, the flip-flop is set: the output (pin 3) goes high and the discharge transistor is off.
  3. If threshold (pin 6) rises above $2V_{cc}/3$, the flip-flop is reset: the output goes low and the transistor discharges the capacitor via pin 7.
  4. Pin 4 (reset), when made low, forces the output low irrespective of other inputs.
  5. In the monostable mode, a trigger pulse gives one output pulse of width $T=1.1RC$.
  6. In the astable mode, the circuit oscillates continuously as below.

Astable derivation. $R_A$ from $V_{cc}$ to pin 7, $R_B$ between pin 7 and pins 2/6, capacitor C to ground. C charges through $R_A+R_B$ from $V_{cc}/3$ to $2V_{cc}/3$ and discharges through $R_B$ from $2V_{cc}/3$ to $V_{cc}/3$. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-10" viewBox="0 0 510 338" width="510" height="338" role="img" aria-label="Astable 555 with RA, RB, C, pins 2 and 6 tied together and pin 7 at RA-RB junction"><style>#dsfig-u4-10 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-10 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-10 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-10 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-10 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-10 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-10 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-10 .t{fill:#16181D;font-weight:500}#dsfig-u4-10 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-10 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-10 .dot{fill:#16181D}#dsfig-u4-10 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-10 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-10 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-10 .ah{fill:#454C5A}#dsfig-u4-10 .ah.hi{fill:#2340B8}#dsfig-u4-10 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-10 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-10 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-10 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-10 .e{stroke:#B1B7C3}html.dark #dsfig-u4-10 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-10 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-10 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-10 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-10 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-10 .t{fill:#E6E8ED}html.dark #dsfig-u4-10 .t.inv{fill:#0F1115}html.dark #dsfig-u4-10 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-10 .dot{fill:#E6E8ED}html.dark #dsfig-u4-10 .ann{fill:#8FA3FF}html.dark #dsfig-u4-10 .lbl{fill:#858D9C}html.dark #dsfig-u4-10 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-10 .ah{fill:#B1B7C3}html.dark #dsfig-u4-10 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-10 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-10 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-10 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah24" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh24" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L148,40" marker-end="url(#ah24)"/><path class="e" d="M169,59 L169,148" marker-end="url(#ah24)"/><path class="e" d="M169,188 L169,277" marker-end="url(#ah24)"/><path class="e" d="M183.2,285.4 L299.5,182.9" marker-end="url(#ah24)"/><path class="e" d="M334.2,169 L449,169" marker-end="url(#ah24)"/><g class="wl"><rect x="148.6" y="95.5" width="40.8" height="18" rx="9"/><text class="t" x="169" y="104.5" dy=".35em" text-anchor="middle">pin7</text></g><g class="wl"><rect x="152.2" y="224.5" width="33.6" height="18" rx="9"/><text class="t" x="169" y="233.5" dy=".35em" text-anchor="middle">2+6</text></g><g class="wl"><rect x="383" y="160" width="19.2" height="18" rx="9"/><text class="t" x="392.6" y="169" dy=".35em" text-anchor="middle">3</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Vcc</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">RA</text><circle class="n" cx="169" cy="169" r="18"/><text class="t" x="169" y="169" dy=".35em" text-anchor="middle">RB</text><circle class="n" cx="169" cy="298" r="18"/><text class="t" x="169" y="298" dy=".35em" text-anchor="middle">C</text><circle class="n" cx="315.2" cy="169" r="18"/><text class="t" x="315.2" y="169" dy=".35em" text-anchor="middle">Ic</text><circle class="n" cx="470" cy="169" r="18"/><text class="t" x="470" y="169" dy=".35em" text-anchor="middle">Out</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Astable 555 with RA, RB, C, pins 2 and 6 tied together and pin 7 at RA-RB junction</figcaption></figure> Charging: $v_c=V_{cc}-\tfrac{2V_{cc}}{3}e^{-t/(R_A+R_B)C}$; it reaches $2V_{cc}/3$ when $e^{-t/\tau}=1/2$, so $T_{high}=0.693(R_A+R_B)C$. Discharging is the same with $R_B$ only: $T_{low}=0.693R_BC$. $$T=0.693(R_A+2R_B)C,\quad f=\frac{1.44}{(R_A+2R_B)C},\quad \text{duty}=\frac{R_A+R_B}{R_A+2R_B}$$

Answer frame. Internal question: draw the block diagram, explain the trigger/threshold/reset/control action, then describe two applications (astable, monostable with $1.1RC$). Derivation question: draw the astable circuit and capacitor waveform between $V_{cc}/3$ and $2V_{cc}/3$, derive $T_{high}$, $T_{low}$, then $f$.

Asked: [14 marks] (Nov 2019) Short notes on any two: IC 555, TTL family, sampling theorem. Asked: [7 marks] (Dec 2023) Derive the frequency of oscillation of an astable multivibrator using IC 555 timer. Asked: [7 marks] (Dec 2025) Explain the internal block diagram and working of IC 555 timer; discuss any two applications.

TTL, PMOS, CMOS and NMOS logic

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Definition. <mark>TTL is a bipolar-transistor logic family, while NMOS, PMOS and CMOS use MOSFETs, CMOS being the complementary pairing of PMOS pull-up and NMOS pull-down transistors.</mark>

Key points.

  1. TTL advantages are high speed, good fan-out (about 10), good noise margin and wide availability in many ICs.
  2. In a two-input TTL NAND, a multi-emitter transistor Q1 forms the inputs, Q2 is the phase splitter, and Q3 and Q4 form the totem-pole output (typical values: 4 kฮฉ, 1.6 kฮฉ, 1 kฮฉ, 130 ฮฉ, $V_{cc}=5$ V).
  3. If any input is low, Q1 conducts, Q2 and Q3 are off, Q4 is on, and Y is high; if both inputs are high, Q1 is reverse-biased, Q2 and Q3 saturate and Y is low.
  4. An NMOS inverter has an NMOS driver with a load transistor or resistor to $V_{DD}$; it draws current when the output is low, so it dissipates static power.
  5. A PMOS inverter is similar but uses PMOS transistors; it is slower (lower hole mobility) and needs negative supply voltages.
  6. A CMOS inverter has a PMOS pull-up and an NMOS pull-down with common gates and drains, so exactly one is on in any steady state.
  7. For $V_{in}=0$: PMOS on, NMOS off, $V_{out}=V_{DD}$; for $V_{in}=V_{DD}$: PMOS off, NMOS on, $V_{out}=0$.
  8. CMOS characteristics are negligible static power, high noise immunity (about 45% of $V_{DD}$), a wide supply range (3-15 V), very high input impedance and high fan-out, but it is slower than TTL.
A B | Q1  Q2  Q3  Q4 | Y     (TTL NAND)
0 0 | on  off off on | 1
0 1 | on  off off on | 1
1 0 | on  off off on | 1
1 1 | rev on  on  off| 0

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-11" viewBox="0 0 355.2 389.6" width="355.2" height="389.6" role="img" aria-label="CMOS inverter: PMOS pull-up, NMOS pull-down; VTC switches sharply at about VDD/2"><style>#dsfig-u4-11 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-11 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-11 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-11 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-11 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-11 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-11 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-11 .t{fill:#16181D;font-weight:500}#dsfig-u4-11 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-11 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-11 .dot{fill:#16181D}#dsfig-u4-11 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-11 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-11 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-11 .ah{fill:#454C5A}#dsfig-u4-11 .ah.hi{fill:#2340B8}#dsfig-u4-11 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-11 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-11 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-11 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-11 .e{stroke:#B1B7C3}html.dark #dsfig-u4-11 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-11 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-11 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-11 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-11 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-11 .t{fill:#E6E8ED}html.dark #dsfig-u4-11 .t.inv{fill:#0F1115}html.dark #dsfig-u4-11 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-11 .dot{fill:#E6E8ED}html.dark #dsfig-u4-11 .ann{fill:#8FA3FF}html.dark #dsfig-u4-11 .lbl{fill:#858D9C}html.dark #dsfig-u4-11 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-11 .ah{fill:#B1B7C3}html.dark #dsfig-u4-11 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-11 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-11 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-11 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah25" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh25" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M186.2,59 L186.2,107"/><path class="e" d="M203.4,134 L298,178.2"/><path class="e" d="M203.4,238.4 L298,194.2"/><path class="e" d="M186.2,265.4 L186.2,330.6"/><path class="e" d="M57.6,179 L166.8,134" marker-end="url(#ah25)"/><path class="e" d="M57.6,193.4 L166.8,238.4" marker-end="url(#ah25)"/><circle class="n" cx="186.2" cy="40" r="18"/><text class="t" x="186.2" y="40" dy=".35em" text-anchor="middle">Vdd</text><circle class="n" cx="186.2" cy="126" r="18"/><text class="t" x="186.2" y="126" dy=".35em" text-anchor="middle">P</text><circle class="n" cx="315.2" cy="186.2" r="18"/><text class="t" x="315.2" y="186.2" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="186.2" cy="246.4" r="18"/><text class="t" x="186.2" y="246.4" dy=".35em" text-anchor="middle">N</text><circle class="n" cx="186.2" cy="349.6" r="18"/><text class="t" x="186.2" y="349.6" dy=".35em" text-anchor="middle">Gnd</text><circle class="n" cx="40" cy="186.2" r="18"/><text class="t" x="40" y="186.2" dy=".35em" text-anchor="middle">In</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">CMOS inverter: PMOS pull-up, NMOS pull-down; VTC switches sharply at about VDD/2</figcaption></figure> The VTC has a flat output high for low input, a steep transition near $V_{DD}/2$ (both transistors on) and a flat output low for high input.

CMOS gates. NOR $Y=\overline{A+B}$: two PMOS in series (pull-up) and two NMOS in parallel (pull-down). NAND $Y=\overline{AB}$: two PMOS in parallel and two NMOS in series. AND and OR are the NAND and NOR followed by a CMOS inverter.

Answer frame. Open with the family definition; draw the circuit (TTL NAND, or NMOS/PMOS/CMOS inverters side by side, or gate networks) with $V_{DD}$ and ground labelled; develop operation by input state; close with a comparison of power (CMOS lowest) and speed (TTL faster).

Asked: [7 marks] (Nov 2018, May 2019) Advantages of TTL; draw a two-input TTL NAND, label values and give its function table. Asked: [7 marks] (May 2019, Jun 2020) Implement using CMOS: NOR, NAND; and AND, OR. Asked: [7 marks] (Dec 2023) Draw and explain PMOS, NMOS and CMOS logic. Asked: [7 marks] (Dec 2024) Describe circuit and performance of CMOS inverter and state characteristics of CMOS.

Interfacing between TTL to MOS

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. <mark>Interfacing connects two different logic families so that the output levels and currents of the driver meet the input requirements of the load.</mark>

Key points.

  1. TTL and CMOS have different levels: TTL gives $V_{OH(min)}=2.4$ V and $V_{OL(max)}=0.4$ V, but 5 V CMOS needs $V_{IH(min)}\approx3.5$ V and accepts $V_{IL(max)}\approx1.5$ V.
  2. Hence a TTL high (2.4 V) may not be read as high by CMOS, and interfacing is needed.
  3. For TTL driving CMOS, an external pull-up resistor (about 1-4.7 kฮฉ) from the TTL output to +5 V raises the high level to nearly 5 V; the low level stays valid.
  4. If CMOS runs at a higher $V_{DD}$ (more than 5 V), a level shifter is used: an open-collector buffer with the pull-up connected to $V_{DD}$.
  5. For CMOS driving TTL, the voltage levels are compatible, but a standard CMOS gate can sink only a small current (TTL input low needs 1.6 mA), so the fan-out is limited to one low-power load.
  6. A CMOS buffer (such as CD4049/4050) or a 74HC/HCT gate is used to drive more TTL loads; it also protects the gate and gives fan-out.

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Answer frame. Open with the level incompatibility; draw both circuits (TTL-to-CMOS with pull-up, CMOS-to-TTL with buffer); develop voltage, then current, then fan-out; close with the interface rule of the driver levels meeting the load's requirements.

Asked: [7 marks] (Dec 2020, Nov 2022, Dec 2025) How is interfacing of TTL to MOS achieved; explain with example; need for interfacing and TTL-to-CMOS techniques.

Last-minute revision

  • Resolution = $V_{FS}/2^n$; 0-5 V to 5 mV needs n = 10 bits.
  • 8-bit DAC at 10 mV/bit: 10001010 gives 1.38 V, 00010000 gives 0.16 V.
  • Flash ADC needs $2^n-1$ comparators (7 for 3 bits, 3 for 2 bits); SAR needs n clocks.
  • Dual slope: $T_2=T_1V_{in}/V_{ref}$, independent of R and C.
  • R-2R DAC: $V_{out}=-V_{ref}D/2^n$, only R and 2R resistors.
  • Nyquist $f_s \ge 2f_m$; Shannon $C=B\log_2(1+S/N)$.
  • Schmitt: $V_H=V_{UT}-V_{LT}$; design 2 V / -1 V / ยฑ13 V gives R1:R2 = 3:23, Vref = 0.565 V.
  • 555: trip levels $V_{cc}/3$ and $2V_{cc}/3$; monostable $T=1.1RC$.
  • 555 astable: $T_{high}=0.693(R_A+R_B)C$, $T_{low}=0.693R_BC$, $f=1.44/((R_A+2R_B)C)$.
  • CMOS: PMOS pull-up, NMOS pull-down, negligible static power; NOR has series PMOS, NAND has series NMOS.
  • TTL to CMOS needs a pull-up to +5 V because $V_{OH}$ 2.4 V is below CMOS $V_{IH}$ 3.5 V.

Memory hooks

  • Flash = "all at once": $2^n-1$ comparators; SAR = "guess bit by bit from the MSB".
  • Schmitt = two thresholds, so hysteresis; noise smaller than $V_H$ is ignored.
  • 555 levels: one-third to trigger, two-thirds to threshold (T for trigger low, T for threshold high).
  • CMOS NAND: N in series; CMOS NOR: P in series (the series network is the one that matches the gate word "AND").
  • TTL high is too weak for CMOS, so pull it up.

Coverage checklist

  • Introduction to A/D & D/A convertors & their types: flash (May 2019, Dec 2020), notes A/D-D/A, CMOS, Shannon, Nyquist (Nov 2022), R-2R (Dec 2024), SAR (Jun 2020), n-bit (Jun 2023), 8-bit DAC (Dec 2023), dual slope (Dec 2023), A/D converter (Nov 2019 under Schmitt).
  • sample and hold circuits: Nov 2018, Jun 2023, Dec 2025.
  • Voltage to Frequency & Frequency to Voltage conversion: V-F converters (Jun 2023).
  • Multivibrators :Bistable, Monostable, Astable: monostable (May 2019), applications of monostable (Dec 2020), astable (Jun 2020), bistable (Nov 2019 under Schmitt).
  • Schmitt trigger: short notes (Jun 2023, Dec 2024), design (Dec 2023), Nov 2019.
  • IC 555 & Its applications: Nov 2019, Dec 2023, Dec 2025.
  • TTL, PMOS, CMOS and NMOS logic: TTL NAND (Nov 2018, May 2019), CMOS gates (May 2019, Jun 2020), PMOS NMOS CMOS (Dec 2023), CMOS inverter (Dec 2024).
  • Interfacing between TTL to MOS: Dec 2020, Nov 2022, Dec 2025.
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