CY-304 Digital System - Jun 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   ai) Express the Boolean function $F = xy + z$ in a product of maxterm form. ii) How do you add two decimal numbers in the BCD form if the sum is greater than 9?
   How to answer

   • For (i): Expand F = xy + z using distributive law: F = (xy + z) = (x + z)(y + z), then expand into complete product of maxterms: (x + y + z)(x + y' + z)(x + z + y')(x' + y + z) etc. or find minterms first and take remaining maxterms.
   • State final canonical product of maxterms $\prod M(...)$.
   • For (ii): Explain BCD addition rule: if sum > 9 or carry occurs, add 6 (0110 in binary) to the sum.
   • Provide an example illustrating the addition of 0110 correction.
2. 7 Marks
   bExplain how the basic gates can be realized using NAND gates.
   How to answer

   • Define universal property of NAND gate.
   • Realize NOT gate: tie both inputs of a NAND gate together.
   • Realize AND gate: NAND gate followed by a NAND inverter.
   • Realize OR gate: invert inputs A and B using NAND inverters, then feed to a third NAND gate (De Morgan's theorem).
   • Draw circuit diagrams for each realization.
3. 7 Marks
   aDesign a Full adder circuit with truth table and logic diagrams.
   How to answer

   • Define full adder (3 inputs: A, B, Cin; 2 outputs: Sum, Cout).
   • Draw the full adder truth table with 8 input combinations.
   • Derive simplified Boolean expressions: Sum = A ⊕ B ⊕ Cin, Cout = AB + Cin(A ⊕ B) or AB + BCin + ACin.
   • Draw the complete logic diagram using basic gates or XOR and NAND/AND-OR gates.
4. 7 Marks
   bUsing four-input multiplexers, implement the following functions: i) $f(A, B, C) = \Sigma m(0, 2, 3, 6, 7)$ control variables A and B. ii) $f(A, B, C) = \Sigma m(1, 3, 4, 6, 7)$ control variables B and C.
   How to answer

   • For (i): Construct implementation table with select lines S1=A, S0=B and data inputs I0, I1, I2, I3 derived in terms of C.
   • Determine inputs: I0 = C', I1 = C, etc. and draw the 4:1 MUX block diagram.
   • For (ii): Construct implementation table with select lines S1=B, S0=C and data inputs I0, I1, I2, I3 derived in terms of A.
   • Determine inputs: I0, I1, I2, I3 in terms of A and draw the second 4:1 MUX block diagram.
5. 7 Marks
   aShow how the J-K flip-flop can be operated as a toggle flip-flop.
   How to answer

   • Recall truth table/characteristic equation of JK flip-flop: $Q_{next} = J Q' + K' Q$.
   • Show condition for toggle: J = 1 and K = 1 leads to $Q_{next} = Q'$.
   • Explain connection: tie inputs J and K together to form a single input T.
   • Draw circuit diagram of JK flip-flop configured as T flip-flop and give truth table.
6. 7 Marks
   bHow does the architecture of PLA differ from ROM and PAL?
   How to answer

   • Define ROM, PAL, and PLA in terms of AND and OR arrays.
   • Create a comparative table showing: ROM (Fixed AND array / Programmable OR array), PAL (Programmable AND array / Fixed OR array), PLA (Programmable AND array / Programmable OR array).
   • Discuss trade-offs in terms of flexibility, ease of programming, speed, and cost.
7. 7 Marks
   aDraw and explain the sample and hold circuits.
   How to answer

   • State the purpose and principle of a sample-and-hold (S/H) circuit in data acquisition/ADC.
   • Draw the circuit schematic with analog switch (FET/MOSFET), hold capacitor ($C_H$), and op-amp voltage buffers.
   • Explain Sample mode: switch closed, capacitor charges to follow input voltage.
   • Explain Hold mode: switch open, capacitor retains charge/voltage.
   • Discuss key performance parameters: acquisition time, aperture time, droop rate.
8. 7 Marks
   bExplain how a Schmitt Trigger circuit works with a neat diagram. Design an Schmitt trigger with $V_{UT} = 2\text{V}$, $V_{LT} = -1\text{V}$. Assume $+V_{sat} = +13\text{V}$, $-V_{sat} = -13\text{V}$.
   How to answer

   • Explain Schmitt trigger working principle and hysteresis curve.
   • Sketch op-amp based Schmitt trigger circuit (non-inverting or inverting with reference voltage $V_{ref}$).
   • Calculate hysteresis voltage: $V_H = V_{UT} - V_{LT} = 2 - (-1) = 3\text{ V}$.
   • Write equations relating $V_{UT}$, $V_{LT}$, $+V_{sat}$, $-V_{sat}$, resistors $R_1, R_2$, and $V_{ref}$.
   • Calculate resistor ratio and reference voltage, choose practical resistor values.
9. 7 Marks
   aWhat is mutual information and how it is related to channel capacity. For a standard voice band communication channel the signal to noise ratio is 30dB and transmission bandwidth is 3KHz. What will be the Shannon limit for information in bits/sec?
   How to answer

   • Define mutual information $I(X; Y) = H(X) - H(X|Y)$ and channel capacity $C = \max_{p(x)} I(X;Y)$.
   • Convert SNR from dB to linear: $SNR = 10^{30/10} = 1000$.
   • Apply Shannon-Hartley theorem: $C = B \log_2(1 + SNR) = 3000 \times \log_2(1001)$.
   • Calculate $C \approx 3000 \times 9.9672 \approx 29,901.6\text{ bits/sec}$.
10. 7 Marks
    bDraw block diagram of PCM system and explain it.
    How to answer

    • Draw block diagram of PCM transmitter: Low Pass Filter, Sampler, Quantizer, Encoder.
    • Draw block diagram of PCM receiver: Regenerative repeater, Decoder, Reconstruction Low Pass Filter.
    • Explain function of each block: anti-aliasing, sampling at Nyquist rate, mapping continuous amplitudes to discrete levels, binary encoding.
11. 7 Marks
    aReduce the expression $f = \Sigma m(3, 4, 5, 7, 9, 13, 14, 15)$ using K-maps and implement the real minimal expression using NOR logic.
    How to answer

    • Plot 4-variable K-map for minterms 3, 4, 5, 7, 9, 13, 14, 15.
    • To implement in NOR logic, group 0s to get minimal POS form or simplify $f'$ and invert.
    • Obtain simplified expression for $f$ in POS form.
    • Implement the resulting POS expression using two-level NOR-NOR logic circuit.
12. 7 Marks
    bExplain the BCD-to-decimal decoder.
    How to answer

    • Define BCD-to-decimal decoder (also called 4-line to 10-line decoder).
    • State inputs (4 BCD bits A, B, C, D) and outputs (10 decimal outputs D0 to D9).
    • Provide truth table showing decimal digits 0-9 and illegal states (10-15 as don't cares/inactive).
    • Give logic equations for outputs and sketch logic diagram.
13. 7 Marks
    aDerive the expression for the period of a pulse generated when 555 timer is used as a monostable multivibrator.
    How to answer

    • Draw circuit diagram of 555 timer in monostable mode with external resistor R and capacitor C.
    • Write the capacitor voltage charging equation: $v_c(t) = V_{CC} (1 - e^{-t/RC})$.
    • Set boundary condition: output switches when capacitor voltage reaches threshold $\frac{2}{3} V_{CC}$ at $t = T$.
    • Solve: $\frac{2}{3} V_{CC} = V_{CC} (1 - e^{-T/RC}) \implies e^{-T/RC} = \frac{1}{3}$.
    • Conclude: $T = RC \ln(3) \approx 1.0986 RC \approx 1.1 RC$.
14. 7 Marks
    bExplain: Coincident selection addressing.
    How to answer

    • Define coincident selection addressing (2D selection using intersecting X (row) and Y (column) lines).
    • Explain why it reduces address decoding hardware compared to 1D addressing (e.g., $2^{k/2} + 2^{k/2}$ vs $2^k$).
    • Describe how a specific memory cell/word is selected at the coincidence of active row and column lines.
    • Draw diagram of coincident selection memory organization with X and Y decoders.
15. 7 Marks
    aAn 8-bit D/A converter has a resolution of 10mV/bit. Find the analog output voltage for the inputs i) 10001010 ii) 00010000
    How to answer

    • Formula: $V_{out} = \text{Resolution} \times D_{10}$.
    • For (i): $(10001010)_2 = 128 + 8 + 2 = 138_{10}$. $V_{out} = 10\text{ mV} \times 138 = 1380\text{ mV} = 1.38\text{ V}$.
    • For (ii): $(00010000)_2 = 16_{10}$. $V_{out} = 10\text{ mV} \times 16 = 160\text{ mV} = 0.16\text{ V}$.
16. 7 Marks
    bWrite a brief note on interfacing CMOS with TTL.
    How to answer

    • Explain logic voltage level differences: TTL ($V_{OH,min} = 2.4\text{V}, V_{OL,max} = 0.4\text{V}$) vs CMOS ($V_{IH,min} = 3.5\text{V}, V_{IL,max} = 1.5\text{V}$ for 5V supply).
    • TTL driving CMOS: TTL $V_{OH}$ is insufficient to guarantee CMOS $V_{IH}$; use a pull-up resistor to $V_{DD}$ or a level converter/CMOS buffer.
    • CMOS driving TTL: voltage levels are compatible, check sink current capability ($I_{OL}$ of CMOS vs $I_{IL}$ of TTL).
    • Draw interfacing circuits (TTL driving CMOS with pull-up resistor, and CMOS driving TTL).