CY-304 Digital Systems / Digital Circuits and System - Dec 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   ai) Add $(83)_{10}$ and $(34)_{10}$ in BCD. ii) Convert the base-7 number $(35614)_7$ to base-12.
   How to answer

   • Express 83 and 34 in 8421 BCD
   • Perform binary addition and add 0110 (6) to digits > 9 or with carry
   • Convert (35614)_7 to decimal: $3\times 7^4 + 5\times 7^3 + 6\times 7^2 + 1\times 7^1 + 4\times 7^0$
   • Convert resulting decimal to base-12 by successive division by 12
2. 7 Marks
   bExplain how the basic gates can be realized using NOR gates?
   How to answer

   • Realization of NOT gate using NOR gate
   • Realization of OR gate using NOR gates
   • Realization of AND gate using NOR gates
   • Logic diagrams and Boolean expressions for each
3. 7 Marks
   aDesign a Half adder circuit with truth table and logic diagrams.
   How to answer

   • Define half adder function (adds two 1-bit inputs)
   • Truth table for inputs A, B and outputs Sum, Carry
   • Boolean expressions: $\text{Sum} = A \oplus B$, $\text{Carry} = A \cdot B$
   • Logic diagram using XOR and AND gate
4. 7 Marks
   bA combinational circuit is defined by the following Boolean functions. Design circuit with a decoder and external gates: $$F_1(x, y, z) = x'y'z' + xz$$ $$F_2(x, y, z) = xyz' + x'z$$
   How to answer

   • Expand $F_1$ and $F_2$ into canonical sum of minterms
   • $F_1(x,y,z) = m_0 + m_5 + m_7 = \Sigma m(0, 5, 7)$
   • $F_2(x,y,z) = m_6 + m_1 + m_3 = \Sigma m(1, 3, 6)$
   • Use a 3-to-8 decoder with inputs $x, y, z$
   • Combine appropriate minterm outputs using OR gates (or NAND gates if active-low decoder) to produce $F_1$ and $F_2$
5. 7 Marks
   aExplain the working of the master slave JK flip-flop.
   How to answer

   • Reason for master-slave configuration (elimination of race-around condition)
   • Logic circuit diagram showing master and slave flip-flops with inverted clock
   • Operation when Clock = 1 (master active, slave isolated)
   • Operation when Clock = 0 (slave active, master isolated, transfer of state to output)
6. 7 Marks
   bDesign a 3-bit binary UP/DOWN counter with a direction control M, Use T flip-flop.
   How to answer

   • Define states and mode control M ($M=0$ for UP, $M=1$ for DOWN or vice versa)
   • State table and excitation table using T flip-flops
   • K-maps to derive inputs $T_0, T_1, T_2$ in terms of $M, Q_0, Q_1, Q_2$
   • Logic expressions for T inputs
   • Complete logic circuit diagram with interconnected T flip-flops and gates
7. 7 Marks
   aDraw and explain the PMOS, NMOS and CMOS logic.
   How to answer

   • Draw and explain NMOS inverter (pull-down network with load resistor/transistor)
   • Draw and explain PMOS inverter
   • Draw and explain CMOS inverter (complementary pull-up PMOS and pull-down NMOS)
   • Briefly compare power dissipation and operational characteristics
8. 7 Marks
   bExplain how a Schmitt Trigger circuit works with a neat diagram. Design an Schmitt trigger with $V_{UT} = 2\text{V}$, $V_{LT} = -1\text{V}$. Assume $+V_{\text{sat}} = +13\text{V}$, $-V_{\text{sat}} = -13\text{V}$.
   How to answer

   • Working principle of Schmitt trigger and hysteresis curve
   • Circuit schematic with op-amp, positive feedback resistors, and reference voltage
   • Formulate equations for $V_{UT}$ and $V_{LT}$ using $+V_{sat}$ and $-V_{sat}$
   • Calculate resistance ratio $R_1/R_2$ and reference voltage $V_{ref}$ from given thresholds
9. 7 Marks
   aWhat is mutual information and how it is related to channel capacity? For a standard voice band communication channel the signal to noise ratio is $30\text{ dB}$ and transmission bandwidth is $3\text{ KHz}$. What will be the Shannon limit for information in bits/sec?
   How to answer

   • Define mutual information $I(X; Y) = H(X) - H(X|Y)$
   • Relation to channel capacity $C = \max_{p(x)} I(X; Y)$
   • Convert SNR from dB to linear: $SNR = 10^{30/10} = 1000$
   • Calculate Shannon capacity: $C = 3000 \times \log_2(1 + 1000) \approx 3000 \times 9.967 = 29,901\text{ bits/sec}$
10. 7 Marks
    bExplain BFSK modulation schemes.
    How to answer

    • Principle of BFSK (two distinct carrier frequencies for bit '0' and bit '1')
    • Mathematical representation of transmitted signals $s_1(t)$ and $s_2(t)$
    • Block diagram of BFSK transmitter / modulator
    • Block diagram of coherent/non-coherent BFSK detector
11. 7 Marks
    aReduce the expression $Y = \Sigma m(1, 4, 8, 12, 13, 15) + d(3, 14)$ using K-maps and implement the real minimal expression using basic logic gates.
    How to answer

    • Plot minterms (1, 4, 8, 12, 13, 15) and don't-care terms (3, 14) on 4-variable K-map
    • Group adjacent cells into quads/pairs to find prime implicants
    • Obtain simplified minimal SOP Boolean expression
    • Draw circuit diagram realizing the reduced expression using AND, OR, NOT gates
12. 7 Marks
    bWhat are the different types of parallel adders? Explain carry save and carry look-ahead adders.
    How to answer

    • List types of parallel adders (Ripple Carry, Carry Look-ahead, Carry Save, Carry Select, etc.)
    • Carry Look-Ahead Adder: Carry propagate $P_i$ and generate $G_i$, lookahead logic equations, block diagram, and speed advantage
    • Carry Save Adder: Concept of saving carries rather than propagating, structure and application in multi-operand addition
13. 7 Marks
    aDerive the frequency of oscillation of an astable multivibrator using IC 555 timer.
    How to answer

    • Draw astable multivibrator circuit using 555 timer with timing components $R_A, R_B, C$
    • Derive charging time: $T_{high} = 0.693(R_A + R_B)C$
    • Derive discharging time: $T_{low} = 0.693 R_B C$
    • Calculate total time period $T = T_{high} + T_{low} = 0.693(R_A + 2R_B)C$
    • Derive frequency expression $f = 1/T = \frac{1.44}{(R_A + 2R_B)C}$
14. 7 Marks
    bExplain: DRAM and FLASH RAM.
    How to answer

    • DRAM: working principle (1-transistor 1-capacitor cell), need for periodic refresh, volatile nature
    • FLASH memory/RAM: floating-gate MOSFET structure, non-volatile nature, block erase/read/write mechanism (NAND/NOR flash)
    • Key operational differences and typical use cases
15. 7 Marks
    aAn 8-bit D/A converter has a resolution of $10\text{ mV/bit}$. Find the analog output voltage for the inputs: i) 10001010 ii) 00010000
    How to answer

    • Formula: $V_{out} = (\text{Decimal equivalent of digital input}) \times \text{Resolution}$
    • For i) 10001010: decimal value $= 128 + 8 + 2 = 138$; $V_{out} = 138 \times 10\text{ mV} = 1380\text{ mV} = 1.38\text{ V}$
    • For ii) 00010000: decimal value $= 16$; $V_{out} = 16 \times 10\text{ mV} = 160\text{ mV} = 0.16\text{ V}$
16. 7 Marks
    bDescribe the operation of dual slope A/D converter with necessary diagrams.
    How to answer

    • Block diagram of Dual Slope ADC (integrator, comparator, control logic, counter)
    • Explanation of integration of unknown input voltage $V_{in}$ for fixed time $T_1$ (run-up)
    • Explanation of integration of reference voltage $-V_{ref}$ until integrator output reaches zero in time $T_2$ (run-down)
    • Derive relation $T_2 = T_1 \frac{V_{in}}{V_{ref}}$, showing independence from $R$ and $C$
    • Integrator output waveform plot showing dual slopes