CY-304 Digital System/Digital Circuits and System - Dec 2025 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aConvert the following:

   1. i)$(753)_{8}$ to decimal
   2. ii)$(4A3)_{16}$ to binary
   3. iii)$(101101.101)_{2}$ to decimal
   4. iv)$(45.625)_{10}$ to Binary
   5. v)$(110101101)_{2}$ to Hexadecimal
   6. vi)$(74)_{10}$ to Excess-3 code
   7. vii)$(11011101)_{2}$ to Gray code
   How to answer

   • Octal, hex, binary, decimal inter-conversion by positional weights
   • Fractional conversion by successive multiplication/division by base
   • Excess-3 by adding 3 to each BCD digit, Gray by XOR successive bits
2. 7 Marks
   bSimplify the following function using 3-variable K-map: $$F(A,B,C)=\sum m(1,2,3,5,7)$$ Also draw the simplified logic diagram.
   How to answer

   • Plot 3-variable K-map for $\sum m(1,2,3,5,7)$
   • Form groups of 1,2,4 minterms and derive prime implicants
   • Write minimized SOP expression
   • Draw AND-OR / NAND logic diagram for minimized function
3. 7 Marks
   aImplement the Boolean function using only NAND gates: $$F(A,B,C)=AB+A'C$$
   How to answer

   • Convert $F=AB+A'C$ to NAND-only form using double inversion/De Morgan
   • Show realization with NAND gates as AND-OR invert
   • Draw logic diagram with only NAND gates
4. 7 Marks
   bExplain the working of a Full Adder with truth table and logic diagram. Why is it required in arithmetic circuits?
   How to answer

   • Define full adder inputs A,B,Cin and outputs Sum, Cout
   • Give truth table for 8 combinations and Boolean expressions
   • Show logic diagram using XOR, AND, OR gates
   • Explain need for cascading in multi-bit arithmetic
5. 7 Marks
   aImplement the Boolean function $F(A,B,C)=\sum m(1,3,6,7)$ using a 4:1 multiplexer.
   How to answer

   • Use A,B as select lines of 4:1 MUX, C as data input
   • Derive implementation table for minterms 1,3,6,7
   • Assign D0-D3 as 0,1,C,C' accordingly
   • Draw MUX connection diagram
6. 7 Marks
   bDesign a decimal-to-BCD encoder and explain its working.
   How to answer

   • Define decimal-to-BCD encoder: 10 inputs to 4 outputs
   • Give truth table / encoding for digits 0-9
   • Derive OR-logic for BCD bits
   • Explain priority / one-hot working
7. 7 Marks
   aExplain the working of a Master-Slave J-K flip-flop with timing diagram.
   How to answer

   • Structure: master J-K gated by clock, slave by inverted clock
   • Explain race-around avoidance and toggling
   • Describe operation for J,K = 00,01,10,11
   • Sketch timing diagram showing master/slave response
8. 7 Marks
   bExplain asynchronous counters and synchronous counters. Compare them with respect to speed and hardware complexity.
   How to answer

   • Define ripple vs clocked-together counting
   • Compare propagation delay/speed and max frequency
   • Compare hardware: clocking, wiring complexity
   • Give applications of each
9. 7 Marks
   aImplement the Boolean functions using PLA: $$F1=A'B+AC$$ $$F2=AB+BC'$$ Draw the PLA programming table.
   How to answer

   • Simplify F1,F2 and identify product terms
   • Draw PLA AND-OR structure with fuses
   • Give PLA programming table (inputs, product terms, outputs)
10. 7 Marks
    bExplain the working of a Sample and Hold circuit with neat diagram. Why is it required in ADC systems.
    How to answer

    • Circuit: switch, capacitor, buffer/op-amp
    • Sample mode tracking and hold mode storage operation
    • Neat circuit diagram and waveforms
    • Need in ADC to hold constant input during conversion
11. 7 Marks
    aExplain the internal block diagram and working of IC 555 Timer. Discuss any two applications of IC 555
    How to answer

    • Internal blocks: comparators, RS flip-flop, discharge transistor, resistor divider
    • Explain threshold, trigger, control, reset operation
    • Discuss two applications e.g. astable, monostable multivibrator
12. 7 Marks
    bExplain the need for interfacing between TTL and MOS logic. Discuss TTL-to-CMOS interfacing techniques.
    How to answer

    • Mismatch in voltage levels, current drive, noise margins
    • TTL-to-CMOS issues: VOH, supply differences
    • Solutions: pull-up resistor, level shifter, HCT series
13. 7 Marks
    aExplain Time Division Multiplexing (TDM) with block diagram. Differentiate between synchronous and asynchronous TDM.
    How to answer

    • Principle of sharing channel in time slots with MUX/DEMUX
    • Block diagram of TDM transmitter-receiver with sync
    • Synchronous vs asynchronous: clocking, bit stuffing, framing
14. 7 Marks
    bExplain quantization process and quantization error in PCM. How can quantization noise be reduced.
    How to answer

    • Sampling, quantization levels, step size, encoding in PCM
    • Quantization error = original minus quantized value
    • Noise power relation to steps; methods: more bits, non-uniform/companding
15. 14 Marks
    Write a short note on any **two**:

    1. a)Logic Gates
    2. b)look-ahead carry generator
    3. c)S-R Flip-Flop
    4. d)Shannon's Channel Capacity Theorem
    How to answer

    • Definition and truth table/symbol for chosen topics
    • Working principle and key expressions/diagram
    • Applications and advantages/limitations