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CS-304 · Digital Systems/Quick Revision Short Notes

Digital Systems (CS-304) - Unit 3 Short Notes

How unit 3 is examined

Flip-flops (SR, JK, D, T, master-slave), race-around, shift registers and counters carry most marks (design questions on counters and T flip-flops repeat); memories (SRAM, DRAM, Flash, ROM) and PLA come next.

Sequential logic: flip-flops, D, T, S-R, J-K Master-Slave

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Definition. <mark>A flip-flop is a 1-bit bistable memory element with two stable states, 0 and 1, that stays in its state until a clocked input changes it.</mark> A sequential circuit is one whose output depends on the present inputs and on past inputs (stored state), so it needs memory and feedback.

Comparison.

Basis Combinational Sequential
Output depends on Present inputs only Present inputs and present state
Memory None Flip-flops store state
Feedback None Output fed back to input
Clock Not needed Usually clocked
Speed Faster Slower
Examples Adder, MUX, decoder Counter, register, FSM

Key points.

  1. SR flip-flop (NOR latch): S=1,R=0 sets Q=1; S=0,R=1 resets Q=0; S=R=0 holds the state; S=R=1 is forbidden because both outputs go 0 and the final state is unpredictable.
  2. Characteristic equation of SR is $Q_{n+1}=S+\bar{R}Q_n$ with $SR=0$.
  3. JK removes the forbidden state: J=K=0 holds, J=0,K=1 resets, J=1,K=0 sets, J=K=1 toggles; $Q_{n+1}=J\bar{Q}_n+\bar{K}Q_n$.
  4. D flip-flop copies the input at the clock edge, $Q_{n+1}=D$; it is a JK with $K=\bar J$ and is used in registers.
  5. T flip-flop toggles when T=1 and holds when T=0, $Q_{n+1}=T\oplus Q_n$; it is a JK with J=K=T and is used in counters.
  6. Edge-triggered means the flip-flop changes only at a clock transition (positive edge 0 to 1, or negative edge 1 to 0), so it samples inputs for an instant.
  7. Excitation table (Q to Q+): SR: 00 -> S0 R-; 01 -> S1 R0; 10 -> S0 R1; 11 -> S- R0. JK: 00 -> J0 K-; 01 -> J1 K-; 10 -> J- K1; 11 -> J- K0. T: T = Q xor Q+.
J K $Q_{n+1}$
0 0 $Q_n$
0 1 0
1 0 1
1 1 $\bar{Q}_n$

Master-slave JK. Two JK latches in series: master enabled by CLK=1, slave enabled by inverted clock (CLK=0).

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  1. While CLK=1 the master follows J,K and the slave is isolated, so Q does not move.
  2. When CLK falls to 0 the master is isolated and the slave copies the master, so Q changes once, at the falling edge.
  3. Output cannot re-enter the master during the same pulse, so J=K=1 toggles exactly once (race-around avoided).

Example (Nov 2022 design, T flip-flops). Assign S1=00, S2=01, S3=10, S4=11 (state AB, $T=Q\oplus Q^+$). Excitation over (A B X): $T_A=1$ for 001, 011, 100, 101, 111; $T_B=1$ for 001, 100. Z=1 for 000, 010, 011, 100.

$$T_A = X + A\bar{B},\quad T_B=\bar{B}(A\oplus X),\quad Z=\bar{B}\bar{X}+\bar{A}B$$

Answer frame. Flip-flop / master-slave: define flip-flop, draw the NAND master-slave figure with inverted clock, give the truth table, explain the CLK=1 and CLK=0 phases, close with race-around removal. RS: define, draw NOR latch, truth table with forbidden row. Design: assignment, transition table, T excitation, K-maps, two T flip-flops with gates for $T_A,T_B,Z$.

Pitfall: In the design, T=1 when the bit changes ($Q\oplus Q^+$), not when the next bit is 1.

Asked: [7 marks] (Jun 2020, Dec 2023, Dec 2025) What is Flip-Flop? Explain Master Slave J-K flip-flop (with timing diagram). Asked: [7 marks] (Nov 2018) What is a flip flop? Explain the principle of operation of RS flip flop with truth table. Asked: [7 marks] (Nov 2018, Nov 2019) What are sequential circuits? Differentiate combinational and sequential circuits. Asked: [7 marks] (Nov 2019) Draw logic diagram of JK Flip-Flop and give its characteristics table and equation. Asked: [7 marks] (May 2019) What is Shift Register? Explain J-K flip flop. Asked: [7 marks] (Nov 2022) Design a sequential circuit using T flip-flop for the given state table (S1..S4, X=0/1, output Z). Asked: [7 marks] (Jun 2023) What is meant by 'edge triggered'? Differentiate SR-FF and JK-FF with functional operation and excitation tables.

Racing condition

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Definition. ==Race-around is the uncontrolled repeated toggling of a level-triggered JK flip-flop when J=K=1 and the clock pulse width $t_p$ is longer than the propagation delay $\Delta t$.== In general a race means the result depends on which of two signals with unequal delays arrives first.

Key points.

  1. In an SR flip-flop, S=R=1 drives both outputs to the same value, and when both inputs go to 0 together the flip-flop races to an unpredictable state, hence S=R=1 is forbidden.
  2. JK feeds Q and $\bar Q$ back to the input gates, so J=K=1 gives a valid toggle instead of an invalid state.
  3. With a level-triggered JK and J=K=1, the output toggles after $\Delta t$, the new value feeds back while the clock is still high, and it toggles again.
  4. The output therefore oscillates many times in one pulse and ends in an unpredictable state, which is the race-around condition.
  5. Condition to avoid: $t_p<\Delta t<T$, which is hard to guarantee, so the fix is structural.
  6. Master-slave: the master works at CLK=1 and the slave at CLK=0, and the two are never open together, so there is no path from output back to master during a pulse.
  7. Other fixes: edge-triggered flip-flops (very narrow sampling window) or a pulse narrower than the delay.
CLK : _|‾‾‾‾‾‾‾|____
Q   : _|‾‾|_|‾‾|____   J=K=1, level JK: toggles every delay, ends unpredictable
Q   : ______|‾‾‾‾‾‾‾   Master-slave: one toggle at falling edge

For the master-slave circuit see the diagram in the previous topic.

Answer frame. Open with the definition and the J=K=1 condition; draw the timing waveform above; explain points 3-5; draw the master-slave figure; explain CLK=1 and CLK=0 phases; close with "the output changes only once, at the falling edge". For SR question, state S=R=1 invalid and then JK toggle.

Asked: [7 marks] (May 2019) What is sequential circuit? Explain racing condition. Asked: [7 marks] (Dec 2020) Explain the race condition in S-R flip flop. Also explain how it is removed in J-K flip flop. Asked: [7 marks] (Dec 2024) Explain race-around condition in J-K flip-flops using timing relationships; draw the clocked Master-Slave J-K and explain how it removes race-around.

Edge and level triggered circuits

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Definition. <mark>A level-triggered circuit responds to inputs during the whole time the clock is at a given level, while an edge-triggered circuit responds only at the clock transition.</mark>

Key points.

  1. Level-triggered devices (latches, gated SR, plain JK) are transparent while the clock is high, so input changes pass to the output and can cause race-around.
  2. Positive-edge triggering acts on the 0 to 1 transition, negative-edge on 1 to 0 (shown by a bubble at the clock input).
  3. Edge-triggered flip-flops sample the input for an instant, so they are race-free and need input stable only near the edge (setup and hold time).
  4. Master-slave behaves as edge-triggered at the output because Q changes once, at the falling edge.

Shift registers

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Definition. <mark>A shift register is a group of cascaded flip-flops sharing one clock in which the stored bits move one place per clock pulse.</mark> An n-bit register stores n bits.

Key points.

  1. SISO: serial in, serial out; a delay line taking n clocks to output a bit.
  2. SIPO: serial in, parallel out; converts serial data to parallel.
  3. PISO: parallel in, serial out (a load/shift control); converts parallel to serial.
  4. PIPO: parallel in, parallel out; a plain storage register.
  5. Bidirectional (shift left-right): a MUX in front of each D input picks the left or right neighbour using a control line (1 = right, 0 = left).
  6. Universal shift register: four D flip-flops with a 4:1 MUX before each D input; select lines $S_1S_0$ choose the mode.
  7. Modes: 00 no change (Q fed back), 01 shift right (from left neighbour, serial input at MSB side), 10 shift left (from right neighbour), 11 parallel load ($I_0..I_3$).
$S_1$ $S_0$ Operation MUX input used
0 0 No change $Q_i$
0 1 Shift right $Q_{i-1}$
1 0 Shift left $Q_{i+1}$
1 1 Parallel load $I_i$

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text-anchor="middle">F0</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">4-bit universal shift register. Mi = 4:1 MUX i, Fi = D flip-flop i (output Qi). All MUXes share S1,S0; all flip-flops share the clock. Each MUX also takes its own Qi (hold) and parallel input Ii.</figcaption></figure>

  1. Example: right shift of 1011 with serial input 0 gives 0101, then 0010 on the next clock.

Answer frame. Open with the definition; draw the universal register (four D flip-flops, four 4:1 MUXes, $S_1S_0$); write the mode table; explain each mode in one sentence; close with the four uses (delay, serial-parallel conversion, storage, counters). For left-right: draw a 2:1 MUX per stage and explain direction control.

Asked: [7 marks] (Dec 2020) What is a Shift Register? Draw and explain shift Left-Right shift register. Asked: [7 marks] (Jun 2023, Dec 2024) Describe (draw and explain) the 4-bit universal shift register with a neat diagram.

Asynchronous and synchronous counters, types and state diagrams

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Definition. <mark>A counter is a sequential circuit that goes through a prescribed sequence of states on clock pulses; in an asynchronous (ripple) counter the clock drives only the first flip-flop and each later stage is clocked by the previous output, while in a synchronous counter all flip-flops share the same clock.</mark>

Basis Asynchronous (ripple) Synchronous
Clock Cascaded, from previous stage Common to all
Delay Adds up, $n\cdot t_{pd}$ One $t_{pd}$
Speed Slow, low max frequency Fast
Logic Very simple, no gates Extra gates
Glitches Yes in decoding No

Key points.

  1. A mod-N counter uses n flip-flops with $2^n\ge N$ (mod-10 needs 4).
  2. Ripple binary counter: JK/T flip-flops with J=K=1, each toggling on the falling edge of the previous Q.
  3. Ripple decade counter (Dec 2024): 4 JK flip-flops, J=K=1, counting 0000 to 1001; at count 10 (1010) Q3 and Q1 are both 1, a NAND of Q3 and Q1 drives the active-low CLEAR of all flip-flops, so it resets to 0000.

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  1. Synchronous up/down counter with M (M=1 up, M=0 down), T flip-flops: $T_0=1$; $T_1=MQ_0+\bar M\bar Q_0$; $T_2=MQ_0Q_1+\bar M\bar Q_0\bar Q_1$; $T_3=MQ_0Q_1Q_2+\bar M\bar Q_0\bar Q_1\bar Q_2$. For 3 bits use $T_0..T_2$ only. Each stage toggles when all lower bits are 1 (up) or all 0 (down).
  2. Timing: all outputs change together at the clock edge; $Q_0$ toggles every clock, $Q_1$ every 2, $Q_2$ every 4, $Q_3$ every 8. With M switched, the count reverses direction.
  3. Random sequence 0,2,4,5,7,0 with D flip-flops: 3 flip-flops, states 1,3,6 unused (don't cares), $D=Q^+$.
Present $Q_2Q_1Q_0$ Next $D_2D_1D_0$
000 (0) 010 (2) 010
010 (2) 100 (4) 100
100 (4) 101 (5) 101
101 (5) 111 (7) 111
111 (7) 000 (0) 000

From the K-maps: $D_2=Q_2\oplus Q_1$, $D_1=\bar Q_1(\bar Q_2+Q_0)$, $D_0=Q_2\bar Q_1$.

  1. State diagram (Nov 2022): "even" means 0. The next state is Even only when $xy=00$, else Odd; $z=1$ only for $xy=00$. The next state does not depend on the present state.
State 00 01 10 11
Even Even/1 Odd/0 Odd/0 Odd/0
Odd Even/1 Odd/0 Odd/0 Odd/0

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Answer frame. Compare: define counter, explain each type with a 3-bit timing figure, table of five differences, one application each (ripple: frequency dividers; synchronous: CPUs). Decade: sequence, NAND reset, figure. Up/down: state table, excitation, K-map equations, circuit, timing. Random: step 6 in order (flip-flop count, table, D equations, circuit).

Pitfall: Forgetting that count 10 appears briefly in a ripple decade counter before the reset acts.

Asked: [7 marks] (Jun 2020, Dec 2025) Explain synchronous and Asynchronous counter (compare on speed and hardware complexity). Asked: [7 marks] (Nov 2022) Draw the state diagram for the Even/Odd sequential system with inputs x(t), y(t) and output z(t). Asked: [7 marks] (Nov 2022) Design a synchronous counter to count 0, 2, 4, 5, 7, 0, ... using D flip-flop. Asked: [7 marks] (Dec 2023, Jun 2023) Design a 4-bit up/down synchronous binary counter with a neat timing diagram (also 3-bit with direction control M using T flip-flop). Asked: [7 marks] (Dec 2024) Design a ripple decade counter using JK flip-flop.

Semiconductor memories

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>Semiconductor memory stores binary data in an integrated circuit as an array of cells, organised as words and read or written by address.</mark>

Key points.

  1. Classification: RAM (read/write, volatile: SRAM and DRAM) and ROM (read mostly, non-volatile: mask ROM, PROM, EPROM, EEPROM, Flash).
  2. SRAM stores a bit in a flip-flop of 4-6 transistors, so it is fast and needs no refresh but is bulky and costly; used for cache.
  3. DRAM stores a bit as charge on a capacitor with one transistor, so it is dense and cheap but the charge leaks and must be refreshed every few milliseconds; used as main memory.
  4. ROM keeps its contents with power off; it is programmed by mask, by fuse (PROM), by UV erase (EPROM) or electrically (EEPROM); used for BIOS and firmware.
  5. Capacity is (number of words) x (bits per word); n address lines select $2^n$ words.
  6. ROM structure: a decoder selects a word line, and diodes or transistors at crossings give the stored 1s and 0s on the bit lines.

Answer frame. Open with the definition; draw the classification tree; give SRAM cell versus DRAM cell in two lines; write DRAM (capacitor, refresh) in full since it is part of the question; close with applications.

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Asked: [7 marks] (Jun 2020, Nov 2022) Write short notes on i) Semiconductor memories ii) DRAM.

Introduction to digital ICs 2716, 2732 and their address decoding

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. <mark>IC 2716 is a 2K x 8 (16 Kbit) UV-erasable EPROM and IC 2732 is a 4K x 8 (32 Kbit) EPROM.</mark>

Key points.

  1. 2716 has 11 address lines (A0-A10) and 8 data lines (D0-D7), and 2732 has 12 address lines (A0-A11) and 8 data lines.
  2. Both work from 5 V, are erased by ultraviolet light through a quartz window, and are read using chip enable and output enable.
  3. Address decoding: the high address lines of the CPU go to a decoder (or NAND gates) whose output drives chip select, so each chip occupies its own range of addresses.
  4. Example: a 2716 needs A0-A10 directly, and A11-A15 decode to chip select, giving a 2 KB block such as 0000H-07FFH.

Modern trends in semiconductor memories: DRAM, Flash RAM

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>DRAM stores bits as charge in capacitors and needs refresh, while Flash is non-volatile memory that stores charge on a floating gate and is erased in blocks.</mark>

Basis SRAM DRAM
Cell Flip-flop (6 transistors) 1 transistor + 1 capacitor
Refresh Not needed Needed every few ms
Speed Faster Slower
Density Low High
Cost per bit High Low
Power Low when idle Higher (refresh)
Use Cache Main memory

Key points.

  1. DRAM write puts charge on the capacitor (1) or discharges it (0), read senses the charge and destroys it, so it is rewritten after every read.
  2. Refresh reads and rewrites each row periodically; DRAM is volatile.
  3. Flash uses a floating-gate MOSFET, where trapped charge changes the threshold voltage and represents the bit.
  4. Flash is non-volatile, is written by tunnelling or hot electrons, and is erased in blocks (not per byte), which is why it is fast.
  5. NOR flash allows random read and suits code storage; NAND flash is denser and cheaper and suits data storage.
  6. Applications: DRAM in main memory; Flash in USB drives, SSDs, memory cards and smartphones.
  7. ROM: non-volatile, holds firmware/BIOS. Flash is electrically erasable ROM with wear limit on erase cycles.

Answer frame. Differentiate: define both, table of seven rows, applications. DRAM and Flash: draw 1T-1C cell and floating-gate cell, then working, volatility, refresh versus block erase, close with uses. For ROM/PLA/DRAM/Flash question give four short paragraphs, each with principle and application.

Asked: [7 marks] (Nov 2019) Differentiate static and dynamic RAM. Asked: [7 marks] (Dec 2023) Explain: DRAM and FLASH RAM. Asked: [7 marks] (Nov 2022) Explain the working and applications of ROM, PLA, DRAM and FLASH RAM.

Designing with ROM and PLA

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>A PLA (Programmable Logic Array) is a programmable logic device with a programmable AND array followed by a programmable OR array, which implements sum-of-products functions.</mark>

Key points.

  1. Inputs pass through buffers giving true and complement lines, the AND plane forms product terms, and the OR plane sums selected products into each output.
  2. Programming is done by blowing fuses (or anti-fuses) at crosspoints; an intact fuse means the input is used.
  3. A ROM has a fixed AND array (a full decoder giving all $2^n$ minterms) and a programmable OR array, so any truth table can be stored, but it wastes terms.
  4. A PLA has only the product terms needed, so it is smaller, and it can share terms between outputs; PAL programs only the AND array.
  5. Designing with ROM: n inputs and m outputs need a $2^n\times m$ ROM whose contents are the truth table.
  6. Applications: combinational logic, code converters and state machines.

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Example (Dec 2025). $F_1=\bar AB+AC$, $F_2=AB+B\bar C$. Product terms: P1 = $\bar AB$, P2 = $AC$, P3 = $AB$, P4 = $B\bar C$ (four terms, no sharing).

Term A B C F1 F2
P1 $\bar AB$ 0 1 - 1 -
P2 $AC$ 1 - 1 1 -
P3 $AB$ 1 1 - - 1
P4 $B\bar C$ - 1 0 - 1

(0 = complement fuse kept, 1 = true fuse kept, - = both blown.)

Answer frame. PLA note: define, draw the block diagram above with fuses, explain programming, compare with PAL and ROM in three lines. Implementation: list product terms, programming table, draw AND-OR fuse map, close with outputs.

Asked: [7 marks] (Dec 2024) Write a short note on PLA. Asked: [7 marks] (Dec 2025) Implement F1 = A'B + AC, F2 = AB + BC' using PLA; draw the PLA programming table. Asked: [7 marks] (May 2019) Write short notes on i) PLA ii) FLASH RAM.

Last-minute revision

  • Flip-flop = 1-bit bistable memory; sequential output depends on past inputs, combinational does not.
  • SR: S=R=1 forbidden; $Q_{n+1}=S+\bar RQ_n$.
  • JK: $Q_{n+1}=J\bar Q+\bar KQ$; J=K=1 toggles; T: $Q_{n+1}=T\oplus Q$; D: $Q_{n+1}=D$.
  • Race-around when J=K=1 and $t_p>\Delta t$ in a level-triggered JK; cured by master-slave or edge triggering.
  • Master works at CLK=1, slave at CLK=0.
  • Universal shift register: 4 D flip-flops + 4 4:1 MUX; $S_1S_0$: 00 hold, 01 right, 10 left, 11 load.
  • Ripple decade counter: NAND of Q3 and Q1 clears at 1010.
  • Ripple delay is $n\cdot t_{pd}$; synchronous delay is one $t_{pd}$.
  • Random counter 0,2,4,5,7: $D_2=Q_2\oplus Q_1$, $D_1=\bar Q_1(\bar Q_2+Q_0)$, $D_0=Q_2\bar Q_1$.
  • DRAM = 1T + 1C, refresh needed; SRAM = flip-flop; Flash = floating gate, block erase.
  • PLA: programmable AND and OR; ROM: fixed AND, programmable OR.
  • 2716 = 2K x 8, 2732 = 4K x 8.

Memory hooks

  • "SR forbids 11; JK toggles 11; T toggles on 1; D copies."
  • Master-slave: "master when CLK high, slave when low", like a lock with two doors.
  • Ripple = domino, synchronous = orchestra with one conductor.
  • Universal register modes 00, 01, 10, 11 = hold, right, left, load.
  • DRAM leaks like a bucket with a hole (refresh), Flash traps charge in a sealed gate.

Coverage checklist

  • Sequential logic: flip flops, D,T, S-R, J-K Master- Slave: flip-flop, master-slave, RS, JK, edge-triggered, sequential vs combinational, T design.
  • racing condition: race-around, SR race, master-slave fix.
  • Edge & Level triggered circuits: definition and comparison.
  • Shift registers: left-right and universal shift register.
  • Asynchronous and synchronous counters, their types and state diagrams: comparison, Even/Odd diagram, random counter, up/down counter, ripple decade counter.
  • Semiconductor memories: classification, SRAM/DRAM, ROM.
  • Introduction to digital ICs 2716, 2732 etc. & their address decoding: 2716, 2732 and decoding.
  • Modern trends in semiconductor memories such as DRAM, FLASH RAM etc.: SRAM vs DRAM, DRAM and Flash, ROM/PLA/DRAM/Flash.
  • Designing with ROM and PLA: PLA note, PLA implementation, PLA and Flash notes.
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