CS-304 Digital Systems - Dec 2024 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aConvert the following decimal numbers to the indicated bases: i) $(516)_7 = ()_{10} = ()_{16}$ ii) $(250.5)_{10} = ()_8 = ()_4$ iii) $(2\text{ED})_{16} = ()_8 = ()_2$ iv) Obtain the 9's and 10's complement of $(864)_{10}$.
   How to answer

   • Convert $(516)_7$ to decimal by positional expansion: $5\times7^2 + 1\times7^1 + 6\times7^0 = 258_{10}$, then convert 258 to hexadecimal: $102_{16}$.
   • Convert integer and fractional parts of $250.5_{10}$ separately to base 8: $372.4_8$ and base 4: $3322.2_4$.
   • Convert $(2\text{ED})_{16}$ to binary: $0010\,1110\,1101_2$, then group in 3s for octal: $1355_8$.
   • Calculate 9's complement of 864 as $999 - 864 = 135$.
   • Calculate 10's complement as $135 + 1 = 136$.
2. 7 Marks
   bRepresent the decimal number 6 in i) Excess-3 code ii) BCD code iii) Gray code iv) 84-2-1 code v) 2421 codes
   How to answer

   • Excess-3: $6 + 3 = 9 \Rightarrow 1001_2$.
   • BCD: 8421 representation of $6 \Rightarrow 0110_2$.
   • Gray code: Binary is 0110, converting to Gray gives $0101_2$.
   • 84-2-1 code: Weight $8(1) + 4(0) - 2(1) - 1(0) = 6 \Rightarrow 1010_2$.
   • 2421 code: $2(1) + 4(1) + 2(0) + 1(0) = 6 \Rightarrow 1100_2$.
3. 7 Marks
   aSimplify the following expression as much as possible: $$F(w, x, y, z) = y'z' + w'x'z' + w'xyz' + wyz'$$ and implement your result using universal gates only.
   How to answer

   • Factor out common terms or plot onto a 4-variable K-map for variables $w, x, y, z$.
   • Group adjacent minterms in the K-map to determine the minimal SOP expression.
   • Obtain simplified expression: $F = z'(y' + w'x' + w'x + w) = z'$.
   • Convert the simplified expression into NAND-only (or NOR-only) gate logic.
   • Draw the circuit diagram using universal gates (NAND/NOR).
4. 7 Marks
   bExpress the following Boolean function $F$ in a sum of min terms and a product of max terms. $$F(x, y, z) = (xy + z)(y + xz)$$
   How to answer

   • Expand the given expression algebraically: $F = xy\cdot y + xy\cdot xz + zy + zxz = xy + xyz + yz + xz = xy + yz + xz$.
   • Find canonical SOP by expanding missing literals: $xy(z+z') + yz(x+x') + xz(y+y')$.
   • Write as sum of minterms: $F(x, y, z) = \sum m(3, 5, 6, 7)$.
   • Write as product of maxterms by taking the complement minterms: $F(x, y, z) = \prod M(0, 1, 2, 4)$.
5. 7 Marks
   aWhat is the role of multiplexer in the digital electronics? Explain the logic how it selects a one input among several inputs?
   How to answer

   • Define multiplexer (MUX) as a digital data selector routing one of $2^n$ data inputs to a single output.
   • Discuss its key roles: data routing, parallel-to-serial conversion, implementing Boolean functions.
   • Explain the selection mechanism via $n$ select lines, using an enable signal and decoding logic.
   • Give example of 4-to-1 or 2-to-1 MUX with truth table, Boolean equation, and gate-level schematic.
6. 7 Marks
   bWrite a short note on decoder.
   How to answer

   • Define decoder: combinational circuit converting $n$ coded inputs into a maximum of $2^n$ unique outputs.
   • Describe working principle and role of enable line (active high/low).
   • Illustrate with 2-to-4 or 3-to-8 decoder truth table and logic circuit.
   • Mention applications: memory address decoding, data demultiplexing, seven-segment display drivers.
7. 7 Marks
   aDraw a full subtractor circuit using NAND gate.
   How to answer

   • State truth table and output equations for full subtractor: $\text{Difference} = A \oplus B \oplus B_{in}$, $\text{Borrow}_{out} = A'B + A'B_{in} + BB_{in}$.
   • Express Difference and Borrow using only NAND operations.
   • Show implementation using two half-subtractors and an OR/NAND gate combination.
   • Neatly draw the 9-NAND gate circuit diagram implementing the full subtractor.
8. 7 Marks
   bExplain race-around condition in relation to the J-K flip-flops using timing relationships. Draw the clocked Master-Slave J-K flip-flop configuration and explain how it removes race-around condition in J-K flip-flops?
   How to answer

   • Define race-around condition: occurs when $J = K = 1$, clock pulse duration $t_p > \Delta t$ (propagation delay), causing the output to oscillate between 0 and 1 uncontrollably.
   • Sketch timing diagrams showing clock pulses, propagation delays, and unstable toggling output.
   • Draw circuit diagram of Master-Slave J-K flip-flop (master clocked on clock high, slave clocked on clock low/inverted).
   • Explain elimination mechanism: master responds when $CLK=1$ while slave is isolated; slave responds when $CLK=0$ while master is isolated, preventing feedback loop oscillation during a single clock pulse.
9. 7 Marks
   aDesign a ripple decade counter using JK flip-flop.
   How to answer

   • State requirements for decade (mod-10) counter: 4 JK flip-flops counting from 0000 to 1001 (0 to 9).
   • Construct count sequence state table and identify reset condition at count 10 (1010, where $Q_3=1$ and $Q_1=1$).
   • Show reset logic: inputs $Q_3$ and $Q_1$ connected to a 2-input NAND gate whose output drives asynchronous clear (CLR) pins.
   • Draw the complete circuit schematic with flip-flops, clock cascading, $J=K=1$, and NAND feedback to reset.
10. 7 Marks
    bDraw and explain 4-bit universal shift register.
    How to answer

    • Define universal shift register as a bidirectional register capable of parallel load, serial/parallel input, and serial/parallel output.
    • Describe mode selection table with mode inputs $S_1, S_0$ (00: No change, 01: Shift-right, 10: Shift-left, 11: Parallel load).
    • Draw circuit diagram containing 4 D flip-flops and four 4:1 multiplexers.
    • Explain internal operation for each mode configuration.
11. 7 Marks
    aWith a neat diagram explain the operation of R-2R DAC.
    How to answer

    • Draw circuit diagram of 4-bit R-2R ladder DAC with operational amplifier.
    • Explain the advantage of R-2R ladder over weighted-resistor DAC (uses only two resistor values).
    • Derive equivalent resistance and current distribution using node equations or Thevenin's theorem.
    • State the output voltage formula: $V_{out} = -V_{ref} \left(\frac{b_3}{2^1} + \frac{b_2}{2^2} + \frac{b_1}{2^3} + \frac{b_0}{2^4}\right)$.
12. 7 Marks
    bWrite a short note on PLA.
    How to answer

    • Define PLA (Programmable Logic Array) as a PLD with both programmable AND and programmable OR arrays.
    • Draw the basic architecture block diagram showing inputs, input buffers/inverters, AND plane, OR plane, and output buffers.
    • Explain programming methodology using fuse links/anti-fuses.
    • Compare briefly with PAL and ROM regarding flexibility and implementation complexity.
13. 7 Marks
    aDescribe the circuit and performance of CMOS inverter and state the characteristics of CMOS.
    How to answer

    • Draw the circuit diagram of a CMOS inverter showing PMOS pull-up and NMOS pull-down network.
    • Explain operation for $V_{in} = 0$ (PMOS ON, NMOS OFF, $V_{out}=V_{DD}$) and $V_{in} = V_{DD}$ (PMOS OFF, NMOS ON, $V_{out}=0$).
    • Sketch Voltage Transfer Characteristics (VTC) showing operating regions.
    • List key characteristics of CMOS: negligible static power dissipation, high noise immunity, wide supply voltage range, high input impedance.
14. 7 Marks
    bDraw the circuit diagram of Schmitt trigger and explain its working.
    How to answer

    • Draw circuit diagram of an op-amp based inverting or non-inverting Schmitt trigger with positive feedback.
    • Explain the concept of hysteresis and calculate threshold voltages: $V_{UTP} = +V_{sat} \frac{R_1}{R_1+R_2}$ and $V_{LTP} = -V_{sat} \frac{R_1}{R_1+R_2}$.
    • Draw the hysteresis loop / transfer characteristics ($V_{out}$ vs $V_{in}$).
    • Discuss its use in wave shaping and eliminating noise in digital signals.
15. 7 Marks
    aWrite a short note on PCM.
    How to answer

    • Define Pulse Code Modulation (PCM) as a method used to digitally represent analog signals.
    • Describe the three main stages: Sampling (Nyquist rate $f_s \ge 2f_m$), Quantization (discretizing amplitudes), and Encoding (converting to binary words).
    • Draw the basic PCM transmitter and receiver block diagram.
    • Mention advantages: high noise immunity, easy multiplexing, and uniform transmission quality.
16. 7 Marks
    bExplain the geometrical representation of Non-orthogonal BFSK.
    How to answer

    • Define Binary Frequency Shift Keying (BFSK) and distinguish between orthogonal and non-orthogonal frequency separation.
    • Define the two signals: $s_1(t) = \sqrt{\frac{2E_b}{T_b}}\cos(2\pi f_1 t)$ and $s_2(t) = \sqrt{\frac{2E_b}{T_b}}\cos(2\pi f_2 t)$ where frequency separation does not satisfy orthogonality condition.
    • Apply Gram-Schmidt procedure to find orthonormal basis functions $\phi_1(t)$ and $\phi_2(t)$.
    • Draw the constellation/signal space diagram showing non-perpendicular signal vectors separated by correlation coefficient $\rho$.
    • Discuss error probability implications due to non-zero correlation.