CS-304 Digital Circuits and System - Jun 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aConvert the following:

   1. i)$(B2F8)_{16} = (?)_{8}$
   2. ii)$(113.2)_{8} = (?)_{2}$
   3. iii)$(01000111)_{2} = (\dots)_{Gray}$
   4. iv)$(249)_{10} = (\dots)_{BCD}$
   5. v)$(A2B.1A)_{16} = (?)_{10}$
   How to answer

   • Convert hex B2F8 to binary and regroup in sets of 3 to get octal
   • Convert each octal digit of 113.2 to 3-bit binary equivalent
   • Apply binary to Gray code conversion logic (MSB same, XOR successive bits)
   • Convert each decimal digit of 249 into 4-bit BCD code
   • Multiply hex digits by corresponding positional powers of 16 and sum
2. 7 Marks
   bConvert the following expression into sum of product and product of sums. $$X' + X(X + Y')(Y + Z')$$
   How to answer

   • Expand $X(X + Y')(Y + Z') = (X + XY')(Y + Z') = X(Y + Z') = XY + XZ'$
   • Substitute back: $X' + XY + XZ' = (X' + X)(X' + Y) + XZ' = X' + Y + XZ' = X' + Y + Z'$
   • Express in canonical or standard Sum of Products (SOP) form
   • Express in standard/canonical Product of Sums (POS) form using Boolean duality/complementation
3. 7 Marks
   aWhat do you mean by logic gates? Describe the various types of gates.
   How to answer

   • Definition of logic gate as fundamental building block of digital systems
   • Classification: Basic gates (AND, OR, NOT), Universal gates (NAND, NOR), Special purpose gates (EX-OR, EX-NOR)
   • Logic symbols and Boolean expressions for each type
   • Truth tables for 2-input implementations
4. 7 Marks
   bWhat do you understand by Adder Circuit? Design and Implement Full Adder using Two half adder and OR Gate.
   How to answer

   • Definition of an adder circuit
   • Full adder truth table with inputs A, B, Cin and outputs Sum, Cout
   • Expressions: Sum = A ⊕ B ⊕ Cin, Cout = AB + Cin(A ⊕ B)
   • Circuit schematic showing two Half Adders connected to an OR gate generating the final Sum and Carry
5. 7 Marks
   aDraw and explain the BCD adder circuit.
   How to answer

   • Principle of BCD addition and detection of invalid BCD codes (sum > 9 or carry = 1)
   • Correction logic by adding binary 0110 (decimal 6)
   • Block/logic diagram using two 4-bit parallel binary adders (e.g., 7483) and a correction detection circuit (C + S3·S2 + S3·S1)
   • Working explanation with an example
6. 7 Marks
   bRealize the function $f(A, B, C, D) = \pi(1, 4, 6, 10, 14) + d(0, 8, 11, 15)$ using: i) 16:1 MUX ii) 8:1 MUX
   How to answer

   • Convert maxterms POS form to minterms SOP form: $f(A, B, C, D) = \sum(2, 3, 5, 7, 9, 12, 13) + d(0, 8, 11, 15)$
   • Implementation using 16:1 MUX: connect select lines to A, B, C, D; connect data inputs to 1, 0, or don't care accordingly
   • Implementation using 8:1 MUX: use A, B, C as select lines and derive D-expressions (0, 1, D, D') for data inputs I0 to I7 using implementation table
   • Draw circuit diagrams for both implementations
7. 7 Marks
   aWhat is meant by 'edge triggered'? Differentiate SR-FF and JK-FF with their functional operation and excitation tables.
   How to answer

   • Definition of edge-triggered flip-flops (positive and negative edge triggering)
   • Comparison of SR-FF vs JK-FF (indeterminate state in SR vs toggle state in JK)
   • Functional truth tables of both flip-flops
   • Excitation tables of SR-FF and JK-FF
8. 7 Marks
   bDescribe the 4-bit universal shift register with a neat diagram.
   How to answer

   • Definition and operations of Universal Shift Register (Parallel load, shift left, shift right, no change)
   • Logic diagram showing four D flip-flops and four 4:1 multiplexers
   • Mode control truth table ($S_1 S_0$ control lines)
   • Working explanation of each operational mode
9. 7 Marks
   aDesign a 4-bit up/down Synchronous binary counter. Explain with a neat timing diagram.
   How to answer

   • State table and excitation table for 4-bit synchronous up/down counter using control input M (M=1 for UP, M=0 for DOWN)
   • Derivation of flip-flop input equations using K-maps
   • Logic circuit diagram using T or JK flip-flops and steering logic gates
   • Timing diagram showing clock cycles, control input, and Q0-Q3 waveform transitions
10. 7 Marks
    bExplain the principle working of sample and hold circuit.
    How to answer

    • Purpose and basic block/schematic diagram of Sample and Hold (S/H) circuit with switch, holding capacitor, and buffer op-amps
    • Sampling mode vs Hold mode operation
    • Waveforms showing input analog signal, sampling control pulse, and S/H output
    • Performance parameters: acquisition time, aperture time, droop rate
11. 7 Marks
    aAn n-bit Analog to Digital converter (ADC) is required to convert an analog input in the range 0-5 V dc to an accuracy of 5mv. Find the value of n.
    How to answer

    • State relation: Resolution / Step size $\le 5\text{ mV} = 0.005\text{ V}$
    • Formula: $\frac{V_{FS}}{2^n} \le 0.005$ or $\frac{5}{2^n} \le 0.005$
    • Calculate $2^n \ge \frac{5}{0.005} = 1000$
    • Since $2^9 = 512$ and $2^{10} = 1024$, select $n = 10$ bits
12. 7 Marks
    bWith the help of circuit diagram explain the working of V-F converters.
    How to answer

    • Definition and basic concept of Voltage-to-Frequency (V-F) conversion
    • Circuit schematic featuring integrator, comparator, reference current/charge dispenser (or monostable multivibrator), and reset switch
    • Working explanation: relationship between input voltage and charging/discharging rates determining output frequency
    • Output frequency formula proportional to input voltage: $f_{out} \propto V_{in}$
13. 7 Marks
    aWith the help of Block diagram explain the working of BPSK modulation scheme.
    How to answer

    • Definition of Binary Phase Shift Keying (BPSK)
    • Block diagram of BPSK transmitter (NRZ level encoder, carrier oscillator, balanced modulator / product modulator)
    • Mathematical representation of BPSK signal: $s(t) = A \cos(2\pi f_c t)$ for bit 1 and $A \cos(2\pi f_c t + \pi)$ for bit 0
    • Waveform / constellation diagram showing $180^\circ$ phase shift
14. 7 Marks
    bWhat do you understand by Multiplexing? Explain the working principle of Time Division Multiplexing with suitable diagram.
    How to answer

    • Definition of multiplexing and why it is used
    • Definition and concept of Time Division Multiplexing (TDM) allocating distinct time slots to channels
    • Block diagram showing commutator (rotary switch), transmission link, and decommutator
    • Frame structure and synchronization explanation
15. 14 Marks
    Write a short notes on any two :

    1. i)Schmitt trigger
    2. ii)PLA
    3. iii)Look ahead carry generator
    4. iv)Karnaugh Map
    How to answer

    • Schmitt trigger: circuit operation, upper and lower threshold voltages (UTP, LTP), hysteresis loop, noise immunity
    • PLA: Programmable Logic Array structure, programmable AND array and programmable OR array, realization of Boolean functions
    • Look ahead carry generator: Carry propagation and carry generation terms ($P_i$ and $G_i$), circuit delay reduction compared to ripple carry adder
    • Karnaugh Map (K-map): graphical method for simplifying Boolean expressions, grouping rules (pairs, quads, octets), Gray coding on map borders