CS-304 Digital Systems / Digital Circuits and System - Nov 2022 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aGiven the following Boolean function: $F(W,X,Y,Z) = WX'(Y' + Z') + X'.Z'.(W' \odot Y)$ where $\odot$ represents the XNOR operation, determine the simplified(minimal) SOP expression for F using boolean algebra and Implement the given function using NOR-NOR logic.
   How to answer

   • Expand the XNOR term $(W' \odot Y) = W'Y + WY'$ or standard XNOR equivalence
   • Distribute and simplify the expression using Boolean algebra identities to minimal SOP form
   • Convert SOP to NOR-NOR logic by taking double complement and applying De Morgan's laws
   • Draw the NOR-NOR logic gate circuit diagram
2. 7 Marks
   bComputer the prime implicants (PI) and essential prime implicants (EPI) in the following Boolean function $F(W, X, Y, Z) = \Pi M(1, 3, 5, 7, 8, 9, 11, 12) + d(2, 10)$ Computer a minimal SOP expression for $F$ and determine whether it is unique.
   How to answer

   • Identify minterms as complementary to given maxterms: $\Sigma m(0, 4, 6, 13, 14, 15)$ with don't-cares $d(2, 10)$
   • Plot 4-variable K-map with minterms and don't cares
   • Group adjacent 1s (and don't cares where helpful) to find all Prime Implicants (PI)
   • Determine Essential Prime Implicants (EPI) covering unique 1s
   • Form minimal SOP expression and analyze if alternative groupings exist to determine uniqueness
3. 7 Marks
   aEach of the following functions actually represents a set of four functions, corresponding to the possible assignments of the don't-care terms. $f_1(w,x,y,z) = \Sigma(1,3,5,6,9,10) + \sum_{\phi}(11,12)$ $f_2(w,x,y,z) = \Sigma(0,3,4,5,8,9) + \sum_{\phi}(6,7)$ i) Find $f_3 = f_1 . f_2$. How many functions does $f_3$ represent? ii) Find $f_4 = f_1 + f_2$. How many functions does $f_4$ represent?
   How to answer

   • List minterms and don't-care sets for both $f_1$ and $f_2$
   • Determine intersection ($f_3 = f_1 \cdot f_2$): minterms where both are 1, and evaluate don't-care interactions
   • Count number of distinct functions $f_3$ represents based on remaining don't-care degrees of freedom ($2^k$)
   • Determine union ($f_4 = f_1 + f_2$): minterms where either is 1, evaluate don't-cares
   • Count number of distinct functions $f_4$ represents based on don't-cares ($2^m$)
4. 7 Marks
   bGiven the network of Fig., determine the functions $f_2$ and $f_3$ if $f_1 = xz + x'z'$ and the overall transmission function is to be $$f(w, x, y, z) = \sum(0, 3, 6, 10, 11, 12)$$

   How to answer

   • Express the circuit equation from the diagram: $f = (f_1 \cdot f_2) + f_3$
   • Express $f_1$ in terms of minterms of 4 variables $(w, x, y, z)$
   • Compare with target minterms of $f(w,x,y,z) = \{0, 3, 6, 10, 11, 12\}$
   • Select $f_2$ and $f_3$ minterm sets such that $(f_1 \cap f_2) \cup f_3 = f$
   • Write minimal SOP expressions for $f_2$ and $f_3$
5. 7 Marks
   aDesign a $8 \times 1$ multiplexer using one $4 \times 1$ multiplexer and four $2 \times 1$ multiplexers.
   How to answer

   • Identify input lines $I_0$ to $I_7$ and select lines $S_2, S_1, S_0$
   • Use four $2 \times 1$ MUXs in the first stage, each taking two inputs ($I_0-I_1, I_2-I_3, I_4-I_5, I_6-I_7$) controlled by $S_0$
   • Connect the 4 outputs of the $2 \times 1$ MUXs to the inputs of the $4 \times 1$ MUX in the second stage
   • Control the $4 \times 1$ MUX with select lines $S_2, S_1$
   • Draw the complete circuit schematic with labeled inputs, outputs, and select lines
6. 7 Marks
   bDesign a combinational logic circuit to convert the BCD to excess-3 code.
   How to answer

   • Construct truth table with 4 BCD inputs (0-9) and 4 Excess-3 outputs, with 10-15 treated as don't-care conditions
   • Draw K-maps for each output variable ($E_3, E_2, E_1, E_0$)
   • Derive minimized Boolean expressions for each output
   • Draw the combinational logic circuit using basic logic gates
7. 7 Marks
   aDesign a $3 \times 8$ decoder using one $1 \times 2$ decoder and two $2 \times 4$ decoder with Enable input.
   How to answer

   • Identify inputs $A, B, C$ and outputs $Y_0$ through $Y_7$
   • Use most significant input $A$ to drive the $1 \times 2$ decoder
   • Connect the two outputs of the $1 \times 2$ decoder to the Enable inputs of the two $2 \times 4$ decoders
   • Feed remaining inputs $B, C$ in parallel to both $2 \times 4$ decoders
   • Draw the circuit diagram and provide the truth table
8. 7 Marks
   bDraw a schematic for a minimal circuit that uses only NOR gates that performs the two's complement operation on a four bit input value. Let the input be $A_{3:0}$ and the output be $B_{3:0}$.
   How to answer

   • Derive two's complement logic equations: $B = A' + 1$ for a 4-bit number $A_3 A_2 A_1 A_0$
   • Express bit-by-bit equations: $B_0 = A_0$, $B_1 = A_1 \oplus A_0$, $B_2 = A_2 \oplus (A_1 + A_0)$, $B_3 = A_3 \oplus (A_2 + A_1 + A_0)$
   • Convert equations into NOR-only implementations using Boolean algebra and De Morgan's theorem
   • Draw the minimal schematic using strictly NOR gates
9. 7 Marks
   aCovert Decimal to Binary i) $(1024)_{10}$ ii) $(23.25)_{10}$
   How to answer

   • For $(1024)_{10}$: recognise $1024 = 2^{10}$, so binary is $10000000000_2$ (or show successive division by 2)
   • For $(23.25)_{10}$: integer part $23_{10} = 10111_2$ via successive division by 2
   • Fractional part $0.25_{10}$: $0.25 \times 2 = 0.5$ (carry 0), $0.5 \times 2 = 1.0$ (carry 1) $\rightarrow .01_2$
   • Combine to obtain $(23.25)_{10} = (10111.01)_2$
10. 7 Marks
    bDraw the state diagram for the following specification sequential systems: Input: $x(t), y(t) \in \{0,1\}$ Output: $z(t) \in \{0,1\}$ State: $s(t) \in \{\text{Even, odd}\}$ Initial state: $s(0) = \text{Even}$ Functions: The transition and output functions are $s(t+1) = \text{even if } x(t) \text{ and } y(t) \text{ both are even}$ $s(t+1) = \text{odd otherwise}$ $z(t) = 1 \text{ if } x(t) \text{ and } y(t) \text{ both are even}$ $z(t) = 0 \text{ otherwise}$
    How to answer

    • Interpret 'even' for binary inputs: $x(t)=0, y(t)=0$ are even; $1$ is odd
    • Construct state transition and output table for states {Even, Odd} with all four input pairs (00, 01, 10, 11)
    • Determine next states: next state is Even only when $xy = 00$, else Odd
    • Determine output: $z = 1$ when $xy = 00$, else $z = 0$
    • Draw state diagram showing two states (Even, Odd) with directed arrows labeled with inputs/output $x y / z$
11. 7 Marks
    aDesign a synchronous counter to count in the random sequence $0, 2, 4, 5, 7, 0, 2, 4, 5, 7 \dots$ using D flip-flop.
    How to answer

    • Determine number of flip-flops required ($N=3$ since max state is 7)
    • Write state transition table for sequence: $000 \rightarrow 010 \rightarrow 100 \rightarrow 101 \rightarrow 111 \rightarrow 000$; unused states ($1, 3, 6$) are don't cares
    • Use D flip-flop excitation property ($D = Q_{next}$)
    • Plot K-maps for $D_2, D_1, D_0$ to find minimal Boolean expressions
    • Draw synchronous logic circuit diagram using 3 D flip-flops and logic gates
12. 7 Marks
    b

    Design a sequential circuit using T flip-flop for the following state table.

    Present State $S(t)$	Next State $S(t+1)$ / Output (Z) for Input $X = 0$	Next State $S(t+1)$ / Output (Z) for Input $X = 1$
    $S_1$	$S_1 / 1$	$S_4 / 0$
    $S_2$	$S_2 / 1$	$S_4 / 1$
    $S_3$	$S_2 / 1$	$S_1 / 0$
    $S_4$	$S_4 / 0$	$S_2 / 0$

    Assume any suitable assumptions for state assignment.

    How to answer

    • Assign binary values to states: e.g., $S_1 = 00, S_2 = 01, S_3 = 10, S_4 = 11$ (two flip-flops $Q_A, Q_B$)
    • Construct transition and excitation table using T flip-flop excitation condition ($T = Q \oplus Q_{next}$)
    • Determine T flip-flop inputs $T_A, T_B$ and output $Z$ for all input combinations ($X=0, X=1$)
    • Derive minimized equations for $T_A, T_B$, and $Z$ using K-maps
    • Draw circuit diagram using T flip-flops and logic gates
13. 7 Marks
    aExplain Interfacing between TTL and MOS with example.
    How to answer

    • Discuss logic level voltage compatibility issues ($V_{OH}, V_{OL}, V_{IH}, V_{IL}$) between TTL and MOS/CMOS
    • Explain TTL driving CMOS: necessity of a pull-up resistor to reach required $V_{IH}$ for CMOS
    • Explain CMOS driving TTL: current sinking ($I_{OL}$) and sourcing capability considerations
    • Provide schematic diagrams of interfacing circuits with typical resistance/voltage values
14. 7 Marks
    bExplain the concept of working and applications of following memories.. i) ROM ii) PLA iii) DRAM iv) FLASH RAM
    How to answer

    • ROM: Principle of non-volatile storage, diode/transistor array structure, applications in firmware/BIOS
    • PLA: Programmable AND and programmable OR arrays, implementation of combinational functions
    • DRAM: Capacitive charge storage, single transistor cell, need for refresh cycles, primary computer memory application
    • FLASH RAM: Floating gate MOSFET, block-level erasure, applications in USB drives, SSDs, mobile storage
15. 14 Marks
    Write notes on the following i) A/D and D/A convertors ii) CMOS Logic iii) Shannon's theorem for channel capacity iv) Nyquist sampling theorem
    How to answer

    • A/D and D/A converters: Operating principles, flash ADC/counter ADC, R-2R ladder/weighted resistor DAC, parameters like resolution and conversion time
    • CMOS Logic: Complementary PMOS and NMOS configuration, operation of CMOS inverter, low power dissipation and high noise immunity
    • Shannon's channel capacity theorem: Formula $C = B \log_2(1 + S/N)$, definition of variables, significance in maximum error-free data rate
    • Nyquist sampling theorem: Statement $f_s \ge 2f_{max}$, aliasing phenomenon, guard bands, and reconstruction low-pass filter