Computer System Organization (EC-504 (B)) - Important Questions

Explain the Von Neumann model of a computer system, its components with diagram, and how it handles instruction and data processing.

Explain the instruction cycle and its fetch, decode and execute phases, with flowchart/steps and significance.

Explain the different addressing modes of a basic computer with examples.

Explain CPU registers including Program Counter (PC), Accumulator and Instruction Register, and memory registers, their roles and working.

Numerical on instruction format: calculate number of distinct instructions and addressable memory locations from opcode bits, address format, and instruction length.

Explain common / shared bus system architecture with the help of diagram.

Determine the task performed by the given machine code with registers initialized to $R1=x, R2=y, R3=0, R4=0$.

Numerical on basic computer bus and instruction format: address bus bits and number of memory-reference vs register-reference instructions from memory size and format.

Differentiate / compare hardwired control unit vs microprogrammed control unit

What is the microinstruction format and what are its different fields / role in control memory?

Describe the process of multiplication in the arithmetic unit. What are the challenges in designing a multiplication circuit?

Describe the micro-instruction format and the function of a microprogram sequencer.

Discuss the concept of floating-point and decimal arithmetic and how these are handled by the arithmetic unit.

Explain hardwired control unit / what is meant by hardwired control

Explain the working principle of a microprogram sequencer with block diagram.

Explain the microprogrammed control organization/unit, including micro and nano programmed control, with a neat sketch.

Draw and explain the flowchart of the floating-point addition process.

Design a minimum-bit encoding for given microinstructions that preserves all inherent parallelism among micro-operations.

Derive Boolean expressions for hardwired control signals $S5, S6, S10$ from instruction $I1$-$I4$ and timing $T1$-$T5$ table

Explain and compare the three data transfer modes: program-controlled (programmed I/O), interrupt-driven I/O, and direct memory access (DMA).

Explain the role and operation of an I/O interface in data transfer.

Explain and compare simplex, half-duplex, and full-duplex data transfer modes and their use cases.

Explain programmed I/O / program-controlled data transfer between CPU and I/O device, including flowchart.

Explain interfacing of a typical DMA controller to CPU/microprocessor with block diagram and example.

Describe the working of I/O processor and its role in asynchronous data transfer.

Differentiate between synchronous and asynchronous data transfer modes.

Calculate I/O bus bandwidth and determine if it can support given device bandwidth requirements.

Numerical problem on DMA transfer: calculate fraction of CPU time spent handling data transfer given transfer rate, page size, clock and overhead cycles.

Describe the organization of cache memory and explain the different mapping techniques (direct, associative, set-associative) with diagrams, and how cache improves processing speed.

Explain the different types of memory and the concept of memory hierarchy and its significance in improving computer performance.

Explain memory mapping in computers, its significance, and how it affects program execution.

What is Associative Memory? How is it different from cache memory?

Given cache size and block size, calculate the number of cache blocks and explain the direct mapping process.

Explain what virtual memory is and discuss the benefits of the virtual memory technique.

Given cache access time, main memory access time and hit ratio, find the average memory access time and define hit ratio.

Explain the difference between internal and external fragmentation.

Explain what virtual memory is and how paging helps implement virtual memory.

Given a memory access sequence and number of cache blocks, find the total number of misses for direct-mapped, set-associative with LRU, and fully associative with FIFO caches.

Given hit/miss cycles and separate read/write access percentages and miss rates, calculate the average memory access time (AMAT).

Explain the principles and basic structure of a pipeline processor, including its advantages and limitations.

Explain the concept of instruction pipelining, including the operations in each segment of a four-segment pipeline, and how it improves processor performance.

Explain vector and array processors, their working and application areas.

Explain vector processing and how it differs from scalar processing.

Write about Multiple Instruction Multiple Data (MIMD) method with its architecture.

Write a short note on any Two:

Write short notes on : (Any four)

Design the half adder with the help of its truth table.