EC-504-B Computer System Organization - Nov 2022 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aWhat task performs by following machine code? Assume initially: $R1 = x, R2 = y, R3 = 0, R4 = 0$ INC R1 # RESULT = x + 1 COPY R3 # R3 = x+1 INC R3 COPY R3 MULT R1, R3 # RESULT = x * (x+2) COPY R3 ADD R2, R2 # RESULT = 2*Y COPY R4
   How to answer

   • Trace register values step by step for INC, COPY, MULT, ADD operations
   • Show intermediate results x+1, x*(x+2), 2*Y
   • State final task / arithmetic expression computed
   • Mention role of R3, R4 as result registers
2. 7 Marks
   bWhat do you mean by virtual memory? Discuss how paging helps in implementing virtual memory.
   How to answer

   • Define virtual memory and need for large logical address space
   • Explain paging concept: pages, frames, page table
   • Discuss how paging supports demand paging and address translation
   • Mention benefits: protection, sharing, reduced fragmentation
3. 7 Marks
   aConsider the basic computer registers connected to a common bus system, if the memory size is 256 k word each of length 32 bits, and the instruction format has three parts: an Indirect address bit (I), the op-code part and the address part for this system perform the following:

   1. i)What is the number of bits of the address bus?
   2. ii)What is the number of memory reference instructions; register reference instructions?
   How to answer

   • Compute address bits from 256k words: 18 bits address bus
   • Compute opcode bits from 32-bit word minus I-bit and address bits
   • Derive number of memory-reference and register-reference instructions
   • State formulas for address space and instruction encoding
4. 7 Marks
   bDraw and explain the flowchart of floating point addition process.
   How to answer

   • Show flowchart blocks: compare exponents, align mantissa, add/subtract, normalize
   • Explain each step with conditions and shifts
   • Mention handling of overflow/underflow and rounding
   • Provide neat flowchart diagram
5. 7 Marks
   aExplain the differences between hardwired control and micro programmed control? Is it possible to have a hardwired control associated with a control memory?
   How to answer

   • Define hardwired control and microprogrammed control
   • Compare on speed, flexibility, design cost, modification
   • Discuss control memory concept and possibility of combination
   • Conclude with applications
6. 7 Marks
   b

   Find a method of encoding the micro instructions described by the following table so that the minimum number of control bits is used and all inherent parallelism among the micro-operations is preserved.

   Micro instruction	Control Signals activated
   $I_1$	$a, b, c, d, e$
   $I_2$	$a, d, f, g$
   $I_3$	$b, h$
   $I_4$	$c$
   $I_5$	$c, e, g, i$
   $I_6$	$a, h, j$

   How to answer

   • List micro-instructions I1 to I6 with activated signals a-j
   • Identify mutually exclusive vs compatible micro-operations
   • Propose grouping/encoding to minimize control bits preserving parallelism
   • Calculate number of bits required
7. 7 Marks
   aWith a neat sketch explain the micro programmed control organization.
   How to answer

   • Draw block diagram: control memory, CAR, CDR, sequencer
   • Explain fetch and execution of microinstructions
   • Describe horizontal vs vertical microprogramming
   • Mention advantages and applications
8. 7 Marks
   bA hardwired CPU uses 10 control signals S1 to S10 in various time steps T1 to T5 to implement 4 instructions I1 to I4 as shown below. Find out the Boolean Expressions represent the circuit for generating control signals S5, S6 and S10 respectively? [$(Ij + Ik) T_n$ indicates that the control signal should be generated in time step $T_n$ if the instruction being executed is Ij or Ik]

   How to answer

   • Interpret table of S1-S10 across T1-T5 for I1-I4
   • Collect minterms for S5, S6, S10 as (Ij+Ik)Tn form
   • Write simplified Boolean expressions for each signal
   • Explain hardwired generation logic
9. 7 Marks
   aDraw flow chart and Explain Program Controlled I/O technique of data transfer between the CPU and I/O device
   How to answer

   • Draw flowchart: test device flag, transfer data, loop
   • Explain CPU polling and role of control/status registers
   • Discuss advantages and drawbacks vs interrupt/DMA
   • Mention example of programmed I/O sequence
10. 7 Marks
    bThe original I/O bus operated at 33 MHz and transferred 32 bits of data at a time. If the hard disks attached to the I/O bus could deliver a maximum of 40 MB per sec, is it possible to use a video card that needed 128 MB/sec of bandwidth to meet the demands of an application? Justify your answer.
    How to answer

    • Compute I/O bus bandwidth: 33 MHz * 32 bits = 132 MB/s
    • Compare with disk 40 MB/s + video 128 MB/s demand
    • Show total demand exceeds bus capacity
    • Justify impossibility of adding video card
11. 7 Marks
    aExplain how a typical DMA controller can be interfaced to CPU or microprocessor with suitable example
    How to answer

    • Draw block diagram of DMA controller interfaced to CPU and memory
    • Explain DMA request, acknowledge, address and control lines
    • Give example of block transfer sequence
    • Mention cycle stealing / burst modes
12. 7 Marks
    bAn I/O device transfers 10 MB/s of data into the memory of a processor over the I/O bus, which has a total bandwidth of 100 MB/s. The 10MB of data is transferred as 2500 independent pages, each of which is 4kB in length. If the processor operates at 200 MHz, it takes 1000 cycles to initiate a DMA transaction and 1500 cycles to respond to the device's interrupt when the DMA transfer completes, what fraction of the CPU's time is spent handling the data transfer with DMA?
    How to answer

    • Compute total CPU cycles for initiation and interrupt per page
    • Compute total overhead time for 2500 pages at 200 MHz
    • Compute transfer time for 10 MB data and fraction of CPU time
    • State formula for DMA overhead fraction
13. 7 Marks
    aExplain the different types of mapping procedures in the organization of cache memory with diagram.
    How to answer

    • Define direct, associative and set-associative mapping
    • Draw diagrams showing tag, index, block offset fields
    • Explain hit/miss logic and replacement
    • Compare advantages and complexity
14. 7 Marks
    bSuppose a 32-bit byte-addressable CPU accesses memory in the following order: 433, 435, 536, 535, 443, 444, 551, 538, 539, 553. Assume that we have 4 cache blocks. Initially the cache is empty. (1 word = 4 bytes) and 12 bits memory addresses are in hex decimal.

    1. i)If the cache is direct-mapped, what is the total number of misses? Assume 1 block is 1 word. (Ignore the tag field and other bits.)
    2. ii)If the cache is 2-way set associative with LRU replacement policy, what is the total number of misses? Assume 1 block is 1 words. (Ignore the tag field and other bits.)
    3. iii)If the cache is fully associative with FIFO replacement policy, what is the total number of misses? Assume 1 block is 1 word. (Ignore the tag field and other bits)
    How to answer

    • Convert hex addresses to block/index for 4 blocks
    • Simulate direct-mapped accesses counting misses
    • Simulate 2-way set associative with LRU
    • Simulate fully associative with FIFO and compare misses
15. 7 Marks
    aCache memory 16KB instruction cache and 16KB data cache. Hit cycle: 1, Miss cycle: 50 75% read access and 25% write access Read miss rate=0.64%, Write miss rate=6.47% What is the Average memory access time (AMAT)?
    How to answer

    • State AMAT formula: Hit time + miss rate * miss penalty
    • Compute weighted miss rate from 75% read and 25% write
    • Substitute hit=1, miss=50 to get AMAT value
    • Interpret result in cycles
16. 7 Marks
    bFormulate a four segment instruction pipeline for a computer. Specify the operation to be performed in each segment.
    How to answer

    • Draw four segments: Fetch, Decode, Execute, Write-back
    • Specify operation in each segment with registers
    • Explain overlapping and timing diagram
    • Mention hazards and speedup