EC-504-B Computer System Organization - Nov 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aWhat do you understand by instruction cycle? Explain with the help of flowchart.
   How to answer

   • Define instruction cycle as fetch-decode-execute sequence
   • Describe phases: fetch, decode, operand fetch, execute, store/interrupt
   • Present flowchart of instruction cycle
   • Explain PC, IR, control signals role in cycle
2. 7 Marks
   bExplain common bus system architecture with the help of diagram.
   How to answer

   • Define common bus system connecting CPU registers, memory and I/O
   • Explain need for multiplexing and control/selection lines
   • Sketch labelled diagram with bus, registers, memory
   • Explain data transfer via bus and bus control
3. 7 Marks
   aWhat is micro instruction format? Explain different field of micro instruction.
   How to answer

   • Define microinstruction and microinstruction format
   • List fields: micro-operation, condition/branch, address fields
   • Explain function of each field
   • Give example format layout
4. 7 Marks
   bWhat is meant by Hard wired control? Explain.
   How to answer

   • Define hardwired control as fixed logic circuit control
   • Explain use of flip-flops, decoders, encoder and logic gates
   • Describe generation of control signals from opcode and timing
   • Mention advantages: speed and disadvantages: inflexibility
5. 7 Marks
   aDesign the half adder with the help of its truth table.
   How to answer

   • Present truth table of half adder for inputs A, B to Sum and Carry
   • Derive Boolean expressions: Sum = A XOR B, Carry = A AND B
   • Show logic diagram using XOR and AND gates
   • Explain working for all input combinations
6. 7 Marks
   bWhat do you mean by programmed I/O? Explain in brief.
   How to answer

   • Define programmed I/O as CPU-controlled data transfer
   • Explain polling / busy-wait and instruction sequence
   • Mention role of I/O addresses and status check
   • Mention drawback: CPU time wastage
7. 7 Marks
   aWhat is a Virtual Memory? Discuss the benefits of virtual memory technique.
   How to answer

   • Define virtual memory as illusion of large main memory using disk
   • Explain paging / address translation and demand paging
   • List benefits: large programs, multiprogramming, protection
   • Mention reduced I/O and efficient memory use
8. 7 Marks
   bIf cache access time is 100 ns, main memory access time is 1000 ns and the hit ratio is 0.9. Find the average access time and also define hit ratio.
   How to answer

   • Define hit ratio as hits divided by total accesses
   • State formula for average access time: $T_{avg} = h \cdot T_c + (1-h) \cdot T_m$
   • Substitute $T_c=100\,ns$, $T_m=1000\,ns$, $h=0.9$ to get $190\,ns$
   • Interpret result and effect of hit ratio
9. 7 Marks
   aExplain the basic structure of pipeline processor.
   How to answer

   • Define pipelining and overlapping of instruction stages
   • Describe stages: fetch, decode, execute, memory, writeback
   • Sketch basic pipeline structure with segments and registers
   • Explain speedup and hazards in brief
10. 7 Marks
    bWrite about Multiple Instruction Multiple Data (MIMD) method with its architecture.
    How to answer

    • Define MIMD as multiple instruction streams on multiple data streams
    • Describe architecture: multiple processors with own control and memory
    • Sketch shared-memory / message-passing MIMD model
    • Give examples: multiprocessors, multicomputers
11. 7 Marks
    aWith neat block diagram, explain the working principle of microprogram sequencer.
    How to answer

    • Define microprogram sequencer role in control unit
    • Present neat block diagram with control memory, CAR, multiplexers
    • Explain next-address generation and branching
    • Describe working sequence for microinstruction fetch
12. 7 Marks
    bExplain the difference between internal and external fragmentation.
    How to answer

    • Define internal fragmentation as wasted space inside allocated block
    • Define external fragmentation as scattered free holes outside allocation
    • Compare on cause, location, occurrence in paging vs segmentation
    • Mention remedies: compaction, paging, best-fit
13. 7 Marks
    aDraw and explain typical block diagram of DMA.
    How to answer

    • Define DMA for direct memory-I/O transfer without CPU
    • Draw typical block diagram with DMA controller, address and data bus
    • Explain DMA request, acknowledge and transfer modes
    • Mention advantages and steal/burst modes
14. 7 Marks
    bWrite in brief about shared bus architecture.
    How to answer

    • Define shared bus architecture for interconnecting modules
    • Explain arbitration, bus protocols and control lines
    • Mention advantages: simplicity, expandability
    • Mention limitation: bottleneck and contention
15. 14 Marks
    Write short notes on any two:

    1. i)Von-Neumann Model
    2. ii)RISC
    3. iii)Cache Memory
    4. iv)Asynchronous Data Transfer
    How to answer

    • Select any two topics from the four options
    • Give definition, diagram/architecture and key features for each
    • Mention advantages, applications and limitations
    • Conclude with comparison or use-case