Computer Org. & Architecture (CS-404) - Unit 4 Short Notes

How unit 4 is examined

This unit covers how the CPU talks to peripherals: the I/O interface and the PCI, SCSI and USB buses, the modes of data transfer, DMA and the I/O processor. All four topics are asked often; the 14-mark PCI, SCSI and USB question and DMA carry the most marks.

I/O Interface – PCI Bus, SCSI Bus, USB

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. An I/O interface is the hardware between the CPU buses and a peripheral that resolves the differences in speed, data format and timing between them. <mark>PCI is a 32/64-bit, plug-and-play local bus joining processor and fast peripherals through a bridge; SCSI is a parallel bus for daisy-chained storage devices; USB is a serial, hot-pluggable, host-controlled bus for external devices.</mark>

Diagram. I/O interface (need and connection).

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-01" viewBox="0 0 510 80" width="510" height="80" role="img" aria-label="CPU to interface (address decode, data, control, status registers) to I/O device"><style>#dsfig-u4-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-01 .t{fill:#16181D;font-weight:500}#dsfig-u4-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-01 .dot{fill:#16181D}#dsfig-u4-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-01 .ah{fill:#454C5A}#dsfig-u4-01 .ah.hi{fill:#2340B8}#dsfig-u4-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-01 .e{stroke:#B1B7C3}html.dark #dsfig-u4-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-01 .t{fill:#E6E8ED}html.dark #dsfig-u4-01 .t.inv{fill:#0F1115}html.dark #dsfig-u4-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-01 .dot{fill:#E6E8ED}html.dark #dsfig-u4-01 .ann{fill:#8FA3FF}html.dark #dsfig-u4-01 .lbl{fill:#858D9C}html.dark #dsfig-u4-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-01 .ah{fill:#B1B7C3}html.dark #dsfig-u4-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58.2,45.4 Q147.5,72 234.9,46" marker-end="url(#ah15)"/><path class="e" d="M236.8,34.6 Q147.5,8 60.1,34" marker-end="url(#ah15)"/><path class="e" d="M61,40 L234,40" marker-end="url(#ah15)" marker-start="url(#ah15)"/><path class="e" d="M276,40 L449,40" marker-end="url(#ah15)" marker-start="url(#ah15)"/><g class="wl"><rect x="112.7" y="49.9" width="68.7" height="18" rx="9"/><text class="t" x="147" y="58.9" dy=".35em" text-anchor="middle">addr+ctl</text></g><g class="wl"><rect x="120.8" y="12.1" width="54.3" height="18" rx="9"/><text class="t" x="148" y="21.1" dy=".35em" text-anchor="middle">status</text></g><g class="wl"><rect x="127.1" y="31" width="40.8" height="18" rx="9"/><text class="t" x="147.5" y="40" dy=".35em" text-anchor="middle">data</text></g><g class="wl"><rect x="342.1" y="31" width="40.8" height="18" rx="9"/><text class="t" x="362.5" y="40" dy=".35em" text-anchor="middle">data</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="255" cy="40" r="18"/><text class="t" x="255" y="40" dy=".35em" text-anchor="middle">Int</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">Dev</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">CPU to interface (address decode, data, control, status registers) to I/O device</figcaption></figure>

Key points.

1. An interface is needed because peripherals are slower than the CPU, use different word formats, and need their own timing and signal levels.
2. The interface decodes the address to select its device, and holds data, control and status registers; the CPU writes commands to control, reads status (ready, busy, error), and moves data through the data register.
3. PCI (Peripheral Component Interconnect) is a 32- or 64-bit multiplexed address/data bus at 33 or 66 MHz, giving 133 MB/s (32-bit, 33 MHz) up to 528 MB/s (64-bit, 66 MHz).
4. A host bridge links the CPU and memory to PCI, and PCI-to-PCI bridges extend it; this isolates fast devices from the processor speed, so it replaced ISA/EISA.
5. PCI signals include AD[31:0], C/BE#, FRAME#, IRDY#, TRDY#, DEVSEL# and REQ#/GNT#; a central arbiter grants the bus and transfers run in bursts (one address, many data words).
6. PCI is plug-and-play: each device has a configuration space that the BIOS reads to assign addresses and interrupts automatically.
7. SCSI (Small Computer System Interface) is a parallel bus of 8 or 16 data lines connecting up to 8 or 16 devices in a daisy chain, with terminators at both ends and a unique ID per device.
8. SCSI devices are initiators (host adapter) or targets (disk, tape); control signals are BSY, SEL, REQ, ACK, ATN, RST, MSG, C/D, I/O; phases are bus free, arbitration, selection, command, data, status, message.
9. USB is a 4-wire serial bus (VBUS, D+, D-, GND) in a tiered-star tree of hubs with one host controller, up to 127 devices, hot-plugging, power supply and automatic enumeration.
10. USB speeds are low 1.5 Mbps, full 12 Mbps, high 480 Mbps and super 5 Gbps; endpoints on each device carry four transfer types: control, bulk, interrupt and isochronous.

Diagram. SCSI bus.

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-02" viewBox="0 0 510 252" width="510" height="252" role="img" aria-label="SCSI: host adapter (initiator) and target devices daisy-chained; T = terminator at each end"><style>#dsfig-u4-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-02 .t{fill:#16181D;font-weight:500}#dsfig-u4-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-02 .dot{fill:#16181D}#dsfig-u4-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-02 .ah{fill:#454C5A}#dsfig-u4-02 .ah.hi{fill:#2340B8}#dsfig-u4-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-02 .e{stroke:#B1B7C3}html.dark #dsfig-u4-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-02 .t{fill:#E6E8ED}html.dark #dsfig-u4-02 .t.inv{fill:#0F1115}html.dark #dsfig-u4-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-02 .dot{fill:#E6E8ED}html.dark #dsfig-u4-02 .ann{fill:#8FA3FF}html.dark #dsfig-u4-02 .lbl{fill:#858D9C}html.dark #dsfig-u4-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-02 .ah{fill:#B1B7C3}html.dark #dsfig-u4-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L193,40"/><path class="e" d="M231,40 L322,40"/><path class="e" d="M360,40 L451,40"/><path class="e" d="M40,59 L40,193"/><path class="e" d="M470,59 L470,193"/><g class="wl"><rect x="109.2" y="31" width="33.6" height="18" rx="9"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">bus</text></g><g class="wl"><rect x="259.7" y="31" width="33.6" height="18" rx="9"/><text class="t" x="276.5" y="40" dy=".35em" text-anchor="middle">bus</text></g><g class="wl"><rect x="388.7" y="31" width="33.6" height="18" rx="9"/><text class="t" x="405.5" y="40" dy=".35em" text-anchor="middle">bus</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Hst</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">D1</text><circle class="n" cx="341" cy="40" r="18"/><text class="t" x="341" y="40" dy=".35em" text-anchor="middle">D2</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">D3</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">T1</text><circle class="n" cx="470" cy="212" r="18"/><text class="t" x="470" y="212" dy=".35em" text-anchor="middle">T2</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">SCSI: host adapter (initiator) and target devices daisy-chained; T = terminator at each end</figcaption></figure>

Answer frame. Open with the definition of the interface; draw the block diagram and the SCSI chain for the 14-mark version; for each bus write architecture, signals, features in that order; close with the comparison table. For "USB vs SCSI" use only the table rows with speed, cost and application.

Pitfall: Do not say SCSI needs no terminators; an unterminated chain reflects signals and fails.

Asked: [14 marks] (May 2019, Jun 2020, Jun 2022, Jun 2025) Explain PCI bus, SCSI bus and USB in detail (also short notes on the same) Asked: [7 marks] (Jun 2022, Jun 2025, Jun 2026) Working of PCI bus and how it improves I/O performance Asked: [7 marks] (Nov 2023) Short notes on the USB interface Asked: [7 marks] (Nov 2023) Explain PCI, BUS and LRU algorithm briefly (LRU: replace the page unused for the longest time, e.g. refs 1,2,3,1,4 with 3 frames evicts 2) Asked: [7 marks] (Jun 2024) Why an interface is needed for I/O devices; how it is connected, with sketch Asked: [7 marks] (Jun 2025) How USB differs from SCSI in speed, cost and application Asked: [7 marks] (Jun 2025) Comparative note on different types of I/O interfaces Asked: [7 marks] (Jun 2026) Architecture and working of the SCSI bus with a diagram

Data Transfer: Serial, Parallel, Synchronous, Asynchronous

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Definition. Serial transfer sends bits one at a time over one line; parallel transfer sends all bits of a word together over many lines. Synchronous transfer is timed by a common clock; asynchronous transfer has no shared clock and uses strobe or handshake signals. <mark>Asynchronous transfer needs control signals because source and destination have independent clocks and speeds.</mark>

Key points.

1. Serial transfer needs few wires, is cheap and reliable over long distances, but is slower per clock; examples are UART/RS-232 and USB.
2. Parallel transfer moves a whole word per clock so it is fast over short distances, but needs many wires and suffers skew and crosstalk; examples are the system bus and the printer port.
3. Synchronous transfer uses one clock for both units, so it is fast and simple but every device must run at the clock speed.
4. Asynchronous transfer suits devices of different speeds, at the cost of extra control lines and handshake delay.
5. Strobe control uses one line: the source places data and pulses STROBE, and the destination latches it, but the source cannot know if the data was received.
6. In destination-initiated strobe, the destination sends the strobe first, then the source supplies data.
7. Handshaking adds a reply line: the source puts data and raises DATA VALID, the destination latches it and raises ACCEPT, then both signals drop in order.
8. Handshaking is reliable since each side confirms the other; strobe alone is not.
9. The modes of I/O transfer are programmed I/O (CPU polls the status flag and is busy), interrupt-driven I/O (device interrupts when ready) and DMA (controller moves the block).

Diagram. Handshake sequence, source-initiated.

Data valid : ____/‾‾‾‾‾‾‾‾‾‾‾‾\____   source: data on bus, valid=1
Data accept: _______/‾‾‾‾‾‾‾‾\_____   destination: latched, accept=1
Order: data placed -> valid=1 -> accept=1 -> valid=0 -> accept=0

Answer frame. Open by defining the mode; draw the strobe and handshake timing lines; develop the mechanism then the table; close by stating the handshake is the reliable method. For I/O modes, compare CPU involvement of the three.

Pitfall: Strobe gives no acknowledgement; only handshaking confirms receipt.

Asked: [7 marks] (Jun 2020, Jun 2023) Different modes of data transfer between processor/memory and I/O devices Asked: [? marks] (Jun 2023) What is multiprocessing? Discuss types of data transfer (serial/parallel, synchronous/asynchronous) Asked: [7 marks] (Dec 2024, Jun 2026) Differences between serial and parallel transfer Asked: [7 marks] (Dec 2024) Differentiate synchronous and asynchronous data transfer Asked: [7 marks] (Jun 2024) Strobe control and handshaking in asynchronous transfer Asked: [7 marks] (Jun 2024, Jun 2026) Asynchronous data transfer with methods

Direct Memory Access (DMA)

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Definition. DMA is a method in which a DMA controller transfers a block of data directly between an I/O device and main memory without passing it through the CPU. <mark>DMA frees the CPU from moving every word, so the CPU only starts the transfer and is interrupted when it ends.</mark>

Diagram. DMA block diagram.

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-03" viewBox="0 0 510 381" width="510" height="381" role="img" aria-label="DMA controller holds address register, word-count register and control logic; BR bus request, BG bus grant"><style>#dsfig-u4-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-03 .t{fill:#16181D;font-weight:500}#dsfig-u4-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-03 .dot{fill:#16181D}#dsfig-u4-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-03 .ah{fill:#454C5A}#dsfig-u4-03 .ah.hi{fill:#2340B8}#dsfig-u4-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-03 .e{stroke:#B1B7C3}html.dark #dsfig-u4-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-03 .t{fill:#E6E8ED}html.dark #dsfig-u4-03 .t.inv{fill:#0F1115}html.dark #dsfig-u4-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-03 .dot{fill:#E6E8ED}html.dark #dsfig-u4-03 .ann{fill:#8FA3FF}html.dark #dsfig-u4-03 .lbl{fill:#858D9C}html.dark #dsfig-u4-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-03 .ah{fill:#B1B7C3}html.dark #dsfig-u4-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58,50.8 L237,158.2" marker-end="url(#ah17)" marker-start="url(#ah17)"/><path class="e" d="M61,40 L449,40" marker-end="url(#ah17)" marker-start="url(#ah17)"/><path class="e" d="M273,158.2 L452,50.8" marker-end="url(#ah17)" marker-start="url(#ah17)"/><path class="e" d="M255,190 L255,320" marker-end="url(#ah17)" marker-start="url(#ah17)"/><g class="wl"><rect x="124" y="95.5" width="47.1" height="18" rx="9"/><text class="t" x="147.5" y="104.5" dy=".35em" text-anchor="middle">BR/BG</text></g><g class="wl"><rect x="238.2" y="31" width="33.6" height="18" rx="9"/><text class="t" x="255" y="40" dy=".35em" text-anchor="middle">bus</text></g><g class="wl"><rect x="324.6" y="95.5" width="75.9" height="18" rx="9"/><text class="t" x="362.5" y="104.5" dy=".35em" text-anchor="middle">addr/data</text></g><g class="wl"><rect x="224.3" y="246" width="61.5" height="18" rx="9"/><text class="t" x="255" y="255" dy=".35em" text-anchor="middle">req/ack</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="255" cy="169" r="18"/><text class="t" x="255" y="169" dy=".35em" text-anchor="middle">DMA</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="255" cy="341" r="18"/><text class="t" x="255" y="341" dy=".35em" text-anchor="middle">IO</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">DMA controller holds address register, word-count register and control logic; BR bus request, BG bus grant</figcaption></figure>

Key points.

1. Programmed I/O wastes CPU time in polling and interrupt I/O still costs a context switch per word; DMA is needed for fast, bulk transfers such as disk.
2. The controller has an address register (memory location), a word-count register (words left) and control logic with the mode bits.
3. The CPU programs the controller with the memory address, the count and the direction, then continues its own work.
4. The device raises a DMA request; the controller sends Bus Request (BR) to the CPU; the CPU finishes its cycle and replies Bus Grant (BG) with its buses floated.
5. The controller then puts the address on the bus, transfers a word, increments the address and decrements the count, repeating until the count is zero.
6. At the end it releases the bus and interrupts the CPU to signal completion.
7. Burst mode holds the bus for the whole block; cycle stealing takes the bus for one word at a time, slowing the CPU slightly.
8. DMA versus interrupts: interrupt I/O needs the CPU to run a service routine for each word, DMA needs it only at start and end, so DMA is faster for blocks.
9. Interrupt handling in brief: finish the instruction, save the PC and status, identify the source, run the service routine, restore and return.

Answer frame. Open with the definition and why it is needed; draw the block diagram with BR and BG; give the steps 3-6 as numbered steps; then modes; close with the benefit that CPU overhead falls to two interrupts per block.

Pitfall: Cycle stealing is one word per bus grant; burst is the whole block.

Asked: [7 marks] (May 2019, Nov 2023, Dec 2024, Jun 2026) Explain the DMA method in detail; significance and working of the controller Asked: [7 marks] (Nov 2023, Dec 2024) Explain DMA with a block diagram of how the operation is carried out Asked: [7 marks] (Jun 2020) Explain DMA and interrupt handling Asked: [? marks] (Jun 2023) Notes on DMA and on PCI and SCSI bus Asked: [14 marks] (Jun 2025) Short note on any two: DMA, virtual memory, ROM

I/O Processor

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. An I/O processor (IOP), or channel, is a separate processor with its own instruction set that manages I/O transfers, so the CPU only issues a high-level command. <mark>The IOP takes over complete I/O tasks, unlike a DMA controller that only moves data.</mark>

Diagram.

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-04" viewBox="0 0 510 338" width="510" height="338" role="img" aria-label="CPU, memory, I/O processor (IOP) and devices D1, D2"><style>#dsfig-u4-04 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-04 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-04 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-04 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-04 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-04 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-04 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-04 .t{fill:#16181D;font-weight:500}#dsfig-u4-04 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-04 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-04 .dot{fill:#16181D}#dsfig-u4-04 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-04 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-04 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-04 .ah{fill:#454C5A}#dsfig-u4-04 .ah.hi{fill:#2340B8}#dsfig-u4-04 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-04 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-04 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-04 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-04 .e{stroke:#B1B7C3}html.dark #dsfig-u4-04 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-04 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-04 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-04 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-04 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-04 .t{fill:#E6E8ED}html.dark #dsfig-u4-04 .t.inv{fill:#0F1115}html.dark #dsfig-u4-04 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-04 .dot{fill:#E6E8ED}html.dark #dsfig-u4-04 .ann{fill:#8FA3FF}html.dark #dsfig-u4-04 .lbl{fill:#858D9C}html.dark #dsfig-u4-04 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-04 .ah{fill:#B1B7C3}html.dark #dsfig-u4-04 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-04 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-04 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-04 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59.5,118.2 L235.5,47.8" marker-end="url(#ah18)" marker-start="url(#ah18)"/><path class="e" d="M59.5,133.8 L235.5,204.2" marker-end="url(#ah18)" marker-start="url(#ah18)"/><path class="e" d="M255,61 L255,191" marker-end="url(#ah18)" marker-start="url(#ah18)"/><path class="e" d="M274.5,204.2 L450.5,133.8" marker-end="url(#ah18)" marker-start="url(#ah18)"/><path class="e" d="M274.5,219.8 L450.5,290.2" marker-end="url(#ah18)" marker-start="url(#ah18)"/><g class="wl"><rect x="130.7" y="160" width="33.6" height="18" rx="9"/><text class="t" x="147.5" y="169" dy=".35em" text-anchor="middle">cmd</text></g><g class="wl"><rect x="238.2" y="117" width="33.6" height="18" rx="9"/><text class="t" x="255" y="126" dy=".35em" text-anchor="middle">DMA</text></g><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="255" cy="40" r="18"/><text class="t" x="255" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="255" cy="212" r="18"/><text class="t" x="255" y="212" dy=".35em" text-anchor="middle">IOP</text><circle class="n" cx="470" cy="126" r="18"/><text class="t" x="470" y="126" dy=".35em" text-anchor="middle">D1</text><circle class="n" cx="470" cy="298" r="18"/><text class="t" x="470" y="298" dy=".35em" text-anchor="middle">D2</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">CPU, memory, I/O processor (IOP) and devices D1, D2</figcaption></figure>

Key points.

1. The IOP is needed to offload I/O from the CPU, which can then compute while many devices are served.
2. The CPU tests the IOP status, then starts it with a command giving the I/O program address in memory.
3. The IOP fetches and runs the channel program (its own instructions) from memory, doing format conversion and error checking.
4. It moves data to memory by DMA and interrupts the CPU when the whole program is finished.
5. The CPU then reads the status word to see success or failure.
6. Computers with several devices gain most, since one IOP controls many controllers.

Answer frame. For need and working: define, draw the CPU-IOP-memory figure, list steps 2-5, close on offloading. For comparison: give one line each for DMA and IOP, then the table.

Asked: [7 marks] (Dec 2020) Compare and contrast DMA and I/O processors Asked: [7 marks] (Jun 2024) Need of the I/O processor and its working

Last-minute revision

• An interface reconciles speed, format and timing differences between CPU and device.
• PCI: 32/64-bit, 33/66 MHz, 133 MB/s to 528 MB/s, bridges, burst, plug-and-play.
• SCSI: 8 or 16 devices in a daisy chain with terminators at both ends.
• SCSI phases: arbitration, selection, command, data, status, message.
• USB: tree of hubs, 127 devices, 4 wires, hot-plug, 1.5 Mbps, 12 Mbps, 480 Mbps, 5 Gbps.
• USB transfer types: control, bulk, interrupt, isochronous.
• Serial uses one line and is cheap; parallel uses many lines and is faster over short range.
• Strobe has no acknowledgement; handshake has a reply signal.
• DMA steps: program, request, BR/BG, transfer, interrupt.
• Burst holds the bus for the block; cycle stealing takes one word.
• IOP runs its own program; DMA only moves data.

Memory hooks

• PCI = Plug-and-play, Common bridge, Inside the box.
• SCSI = "Skuzzy" chain: devices in a line, terminated at the ends.
• USB transfers: "CBII", control, bulk, interrupt, isochronous.
• DMA: "Request, Grant, Steal, Tell": BR, BG, transfer, interrupt.
• Strobe = shout, handshake = shout and hear "OK".

Coverage checklist

• I/O Interface –PCI Bus, SCSI Bus, USB: Q2, Q3, Q12, Q13, Q14, Q15, Q16, Q17, Q18.
• Data Transfer: Serial, Parallel, Synchronous, Asynchronous Modes of Data Transfer: Q4, Q5, Q6, Q7, Q8, Q21.
• Direct Memory Access(DMA): Q1, Q9, Q10, Q11, Q22.
• I/O Processor: Q19, Q20.