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CS-404 · Computer Org. & Architecture/Quick Revision Short Notes

Computer Org. & Architecture (CS-404) - Unit 3 Short Notes

How unit 3 is examined

This unit covers how the ALU adds, subtracts, multiplies and divides binary numbers; Booth's algorithm, signed 2's complement addition and the arithmetic-unit design carry the most marks.

Addition and Subtraction

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Definition. Binary addition adds two bits at a time with a carry, and binary subtraction subtracts bit by bit with a borrow; hardware does both with one adder by using complements.

Key points.

  1. Addition rules are $0+0=0$, $0+1=1$, $1+1=0$ with carry 1, and $1+1+1=1$ with carry 1.
  2. Subtraction rules are $0-0=0$, $1-0=1$, $1-1=0$ and $0-1=1$ with a borrow of 1 from the next higher bit.
  3. A full adder has $S = A \oplus B \oplus C_{in}$ and $C_{out} = AB + C_{in}(A \oplus B)$; a half adder has $S = A \oplus B$ and $C = AB$.
  4. Subtraction is done as $A - B = A + \bar{B} + 1$, so the same adder serves both operations.

<mark>A parallel adder is a chain of full adders in which each carry-out feeds the next carry-in, and subtraction is performed by adding the 2's complement.</mark>

2's Complement Representation

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Definition. The 1's complement of a binary number is obtained by inverting every bit, and the 2's complement is the 1's complement plus 1; both represent negative numbers with the leftmost bit as the sign (0 positive, 1 negative).

Key points.

  1. To form the 2's complement, invert all bits and add 1 (equivalently $2^n - N$); for $+6$ = 0110 the 1's complement is 1001 and the 2's complement 1010, which is $-6$.
  2. The range of $n$-bit 2's complement is $-2^{n-1}$ to $+2^{n-1}-1$, and of 1's complement $-(2^{n-1}-1)$ to $+(2^{n-1}-1)$.
  3. 1's complement has two zeros (0000 and 1111) whereas 2's complement has a single zero, which is why it is preferred.
  4. Subtraction becomes addition: $A - B = A + (2\text{'s complement of } B)$.
  5. In 2's complement the carry out of the sign bit is discarded; in 1's complement it is added back at the least significant bit (end-around carry).
  6. Example, $9 - 5$ in 5 bits: $5 = 00101 \to 11011$; $01001 + 11011 = 1\,00100$; discard the carry to get $00100 = 4$.

==Subtraction is performed as $A - B = A + \bar{B} + 1$, so no separate subtractor circuit is needed.==

Answer frame. Open by defining 1's and 2's complement; give the formation steps with one example each; then range, single zero, subtraction as addition with the 9 - 5 example; close by stating the end-carry rule and that one adder serves both operations.

Asked: [7 marks] (Jun 2024) Discuss how two's complement is used for representing negative numbers and performing subtraction as addition with complement.

Asked: [7 marks] (Jun 2025) Explain 1's and 2's complement representation for negative numbers with examples.

Signed Addition and Subtraction

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Definition. In signed 2's complement arithmetic, numbers including their sign bit are added directly; subtraction adds the 2's complement of the subtrahend, and the result is checked for overflow.

Key points.

  1. Convert each operand to $n$-bit 2's complement, with negatives as the complement of the magnitude.
  2. Add all bits including the sign bit and discard any carry out of the sign position.
  3. To subtract, change the sign of the subtrahend by taking its 2's complement and then add.
  4. Overflow can occur only when both operands have the same sign and the result has the opposite sign.
  5. The hardware test is overflow $= C_{in} \oplus C_{out}$ of the sign bit: overflow if the carry into the sign bit differs from the carry out.
  6. The range of a 7-bit number is $-64$ to $+63$ and of a 5-bit number $-16$ to $+15$; a result outside it is overflow.

Example (7-bit). $+35 = 0100011$, $-35 = 1011101$, $+40 = 0101000$, $-40 = 1011000$.

Case Addition Carry in / out of sign Result
i) $35 + 40$ 0100011 + 0101000 = 1001011 1 / 0 overflow (true 75 > 63)
ii) $-35 + -40$ 1011101 + 1011000 = 1 0110101 0 / 1 overflow (true $-75$)
iii) $-35 - 40$ 1011101 + 1011000 (2's comp of +40) = 0110101 0 / 1 overflow (true $-75$)

Example (5-bit).

Pair Binary sum Carry in / out Result
$-5 + 7$ 11011 + 00111 = 1 00010 1 / 1 $+2$, no overflow
$-10 + -13$ 10110 + 10011 = 1 01001 0 / 1 overflow (true $-23 < -16$)
$-14 + 11$ 10010 + 01011 = 11101 0 / 0 $-3$, no overflow

<mark>Overflow occurs exactly when the carry into the sign bit differs from the carry out of it.</mark>

Answer frame. Open with the 2's complement rule for signed numbers; write each operand in binary first; add row by row and mark both sign-bit carries; close each case with the words overflow or no overflow. For the adder/subtractor circuit see the design section.

Pitfall: Discarding the carry out is not an overflow test; compare carry in and carry out of the sign bit.

Asked: [14 marks] (May 2019, Jun 2020) Perform (+35) + (+40), (-35) + (-40), (-35) - (+40) in signed 2's complement using seven bits and check overflow; also convert -5 and 7, -10 and -13, -14 and 11 to 5-bit signed 2's complement, add them and state whether overflow occurred.

Asked: [7 marks] (Jun 2023, Jun 2024) Describe signal addition and subtraction in detail; design a 4-bit adder/subtractor circuit and explain how addition and subtraction are performed (circuit in the design section below).

Multiplication and Division

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Definition. Multiplication $M \times Q = P$ forms partial products (M or 0 for each multiplier bit, shifted) and sums them; a carry-save adder array adds them without propagating carries row to row.

Key points.

  1. Each row of full adders passes its sum and carry to the next row instead of rippling the carry, and only one final carry-propagate adder resolves the product.
  2. This makes the delay grow with the number of rows, not with rows times carry length.
  3. Example: $M = 1011$ (11), $Q = 1101$ (13): partial products 00001011, 00101100, 01011000 give sum bits 01111111 and carries 00010000, and the final add gives $10001111 = 143$.

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Asked: [7 marks] (Jun 2020) Explain the concept of carry-save addition for the multiplication operation $M \times Q = P$ for 4-bit operands, with diagram and suitable example.

Booth's Algorithm

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Definition. Booth's algorithm multiplies signed 2's complement numbers directly by scanning the multiplier bit pair $Q_0 Q_{-1}$ and adding or subtracting the multiplicand, followed by an arithmetic shift right.

Key points.

  1. It is needed because plain shift-and-add fails for a negative multiplier in 2's complement; Booth handles both signs without correction.
  2. It recodes a run of 1s as $+2^{k+1} - 2^{j}$, so a block of 1s costs one subtraction and one addition.
  3. Registers: $M$ (multiplicand), $A = 0$, $Q$ (multiplier), $Q_{-1} = 0$ and count $= n$.
  4. Rules: 00 or 11 only shift; 10 gives $A = A - M$; 01 gives $A = A + M$.
  5. After each step do an arithmetic shift right of $A, Q, Q_{-1}$, keeping the sign bit of A, and decrement the count.
  6. After $n$ cycles the $2n$-bit product is in $A Q$.
  7. Best case is a multiplier with few 0-1 and 1-0 transitions; worst case is alternating bits.

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Ini: A=0, Q-1=0, count=n. Chk: test Q0 Q-1. Sub: A=A-M. Add: A=A+M. Shr: arithmetic shift right A,Q,Q-1 and count-1. Cnt: count=0? End: product in A,Q.</figcaption></figure>

Example 1. $(+15) \times (-13)$, 5 bits: $M = 01111$, $Q = 10011$.

Cycle $Q_0Q_{-1}$ Operation A Q $Q_{-1}$
1 10 A-M, shift 11000 11001 1
2 11 shift 11100 01100 1
3 01 A+M, shift 00101 10110 0
4 00 shift 00010 11011 0
5 10 A-M, shift 11001 11101 1

$AQ = 1100111101 = -195$.

Example 2. $(-13) \times 8$: $M = 10011$ ($-13$), $Q = 01000$.

Cycle $Q_0Q_{-1}$ Operation A Q $Q_{-1}$
1-3 00 shift 00000 00001 0
4 10 A-M, shift 00110 10000 1
5 01 A+M, shift 11100 11000 0

$AQ = 1110011000 = -104$. Likewise $(+15) \times (-6)$: $Q = 11010$ gives operations shift, A-M, A+M, A-M, shift and $AQ = 1110100110 = -90$.

Best case. Appending $Q_{-1} = 0$, the transitions are: 011111 has 2, 0110110 has 4, 00000111 has 2, 01010101 has 8. The best cases are 011111 and 00000111 (one block of 1s, two operations); 011111 has the longest block and saves most; 01010101 is the worst.

<mark>Booth's algorithm examines $Q_0 Q_{-1}$: 10 subtracts M, 01 adds M, 00 and 11 only shift.</mark>

Answer frame. Open with the definition and why signed multiplication needs it; draw the flowchart; state the four rules and the shift; work one example in the A, Q, $Q_{-1}$ table and box the product with its sign; close by noting the $2n$-bit product. For best case, count transitions of each multiplier.

Asked: [8 marks] (Jun 2022, Nov 2023) Discuss Booth's algorithm in detail / for multiplication of signed numbers.

Asked: [7 marks] (May 2019, Jun 2020) Multiply (+15) x (-13) using Booth's method; explain Booth's algorithm and multiply +15 and -6.

Asked: [7 marks] (Dec 2020) Find which is the best case for implementing Booth's algorithm for a multiplier: 011111, 0110110, 00000111, 01010101.

Asked: [7 marks] (Dec 2024) Draw the flowchart for Booth's algorithm for multiplication of signed 2's complement numbers and explain with an example.

Asked: [7 marks] (Jun 2025) Describe Booth's algorithm for multiplication. Illustrate with a 4-bit example.

Asked: [7 marks] (Dec 2024, Jun 2026) Evaluate (-13) x (8) using Booth's multiplication algorithm and draw the flow diagram of this process.

Asked: [? marks] (Jun 2023) Write Booth's algorithm. Also explain floating point arithmetic operation.

Division Operation

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. Binary division is long division: the dividend is shifted left one bit at a time into a partial remainder, the divisor is subtracted, and each step produces one quotient bit.

Key points.

  1. Registers: $A = 0$ (remainder), $Q$ = dividend, $M$ = divisor, count $= n$.
  2. Restoring: shift $AQ$ left, do $A = A - M$; if $A < 0$ set $q_0 = 0$ and restore $A = A + M$, otherwise $q_0 = 1$.
  3. Non-restoring: shift $AQ$ left; if $A \ge 0$ subtract $M$, else add $M$; set $q_0 = 1$ if the new $A \ge 0$, else 0.
  4. Non-restoring needs no restore step, so it is faster; a final correction adds $M$ if the last remainder is negative.
  5. After $n$ steps $Q$ holds the quotient and $A$ the remainder.

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Ini: A=0, Q=dividend, M=divisor, count=n. Shl: shift AQ left. Sub: A=A-M. Tst: A<0? Res: A=A+M, q0=0. Set: q0=1. Cnt: count-1, zero?</figcaption></figure>

Example. $10100 \div 101$ (20 / 5), non-restoring, $M = 101$:

Step After shift $A \pm M$ $q_0$
1 1 $1 - 5 = -4$ 0
2 $-8$ $-8 + 5 = -3$ 0
3 $-5$ $-5 + 5 = 0$ 1
4 0 $0 - 5 = -5$ 0
5 $-10$ $-10 + 5 = -5$ 0

Final $A = -5 < 0$, so add $M$: remainder $0$. Quotient $00100 = 4$, remainder $0$.

<mark>Division repeats shift, subtract and test for $n$ cycles, giving one quotient bit per cycle.</mark>

Answer frame. Open with the long-division principle; draw the restoring flowchart; explain restoring, then the non-restoring difference; close with the 20 / 5 example ending in quotient 4, remainder 0.

Asked: [7 marks] (Jun 2024) Discuss how binary division is performed and the steps involved in dividing one binary number by another with flowchart.

Asked: [7 marks] (Jun 2026) Draw the flow chart of restoring division operation and perform the division process of 10100 by 101 using non-restoring Booth's division method.

Floating Point Arithmetic Operation

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. A floating-point number is stored as sign, exponent and mantissa, value $= (-1)^S \times M \times 2^E$; IEEE 754 single precision uses 1 sign bit, 8 exponent bits (bias 127) and 23 mantissa bits.

Key points.

  1. Addition and subtraction: compare exponents, shift the smaller mantissa right to align, add or subtract mantissas, then normalise.
  2. Example: $1.5 \times 2^3 + 1.0 \times 2^1$: align to $0.25 \times 2^3$, sum $1.75 \times 2^3 = 14$.
  3. Multiplication: add the exponents (subtract the bias), multiply the mantissas, normalise, and set the sign by XOR.
  4. Division: subtract the exponents (add the bias), divide the mantissas, normalise.
  5. Results are rounded to fit the mantissa; exponent too large is overflow and too small is underflow.
Feature Fixed point Floating point
Format Fixed binary point, e.g. $0101.10 = 5.5$ Mantissa and exponent, e.g. $1.011 \times 2^3$
Range Small Very large
Precision Uniform, absolute Relative, varies with size
Hardware Simple, fast Complex, needs aligning and normalising
Use Embedded, DSP, integers Scientific and graphics

<mark>Floating-point addition aligns exponents, adds mantissas and normalises; multiplication adds exponents and multiplies mantissas.</mark>

Answer frame. Open with the sign, exponent, mantissa format; give addition steps with the example, then multiplication and division, then rounding and overflow; for the comparison, draw the table and give one example each.

Asked: [7 marks] (Dec 2024, Jun 2026) Describe the basic arithmetic operations supported by floating-point arithmetic, including addition, subtraction, multiplication and division.

Asked: [7 marks] (Jun 2025) Compare fixed point and floating point arithmetic operations with examples.

Asked: [? marks] (Jun 2023) Write Booth's algorithm. Also explain floating point arithmetic operation.

Design of Arithmetic Unit

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. The arithmetic unit is the ALU section of the CPU that performs addition, subtraction, multiplication, division and shifts on operands held in registers.

Key points.

  1. The ALU contains the parallel adder and logic that carry out the operation chosen by the control signals.
  2. Input registers (and an accumulator) hold the operands and receive the result.
  3. A shifter supports shift-and-add multiplication, division and normalisation.
  4. The control unit selects the operation and sequences the steps.
  5. Status flags (carry, zero, sign, overflow) report the result to the control unit.
  6. Adder/subtractor: XOR gates on the B inputs with mode M let one 4-bit adder do both operations.
  7. With $M = 0$ the XOR passes $B$ and $C_{in} = 0$, giving $A + B$; with $M = 1$ it inverts $B$ and $C_{in} = 1$, giving $A + \bar{B} + 1 = A - B$.
  8. Carry ripples from $FA_0$ to $FA_3$; the final carry is the carry-out (borrow indicator for subtraction), and $V = C_3 \oplus C_4$ gives overflow.

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cx="143.2" cy="169" r="18"/><text class="t" x="143.2" y="169" dy=".35em" text-anchor="middle">F3</text><circle class="n" cx="237.8" cy="169" r="18"/><text class="t" x="237.8" y="169" dy=".35em" text-anchor="middle">F2</text><circle class="n" cx="332.4" cy="169" r="18"/><text class="t" x="332.4" y="169" dy=".35em" text-anchor="middle">F1</text><circle class="n" cx="427" cy="169" r="18"/><text class="t" x="427" y="169" dy=".35em" text-anchor="middle">F0</text><circle class="n" cx="280.8" cy="306.6" r="18"/><text class="t" x="280.8" y="306.6" dy=".35em" text-anchor="middle">A</text><circle class="n" cx="40" cy="298" r="18"/><text class="t" x="40" y="298" dy=".35em" text-anchor="middle">Co</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">4-bit adder/subtractor. X four XOR gates on B, M mode, F0-F3 full adders giving S0-S3, A0-A3 the A inputs, Co final carry.</figcaption></figure>

Example. $M = 1$: $A = 0111$, $B = 0101$, XOR gives 1010, $C_{in} = 1$, sum $= 1\,0010$; drop the carry to get $0010 = 2 = 7 - 5$.

==One row of full adders with XOR gates on the B inputs and $C_{in} = M$ performs both addition and subtraction.==

Answer frame. For the short note, open by defining the arithmetic unit; draw the block diagram; explain each component in order (ALU, registers, shifter, control, flags). For the adder/subtractor, draw the circuit, explain $M = 0$ and $M = 1$, give the example, close with overflow.

Asked: [6 marks] (Jun 2022, Dec 2024) Write a short note on design of arithmetic unit; what components are required to design the arithmetic unit, explain with neat sketch.

Asked: [7 marks] (Jun 2023, Jun 2024) Design a 4-bit adder/subtractor circuit and explain how addition and subtraction are performed.

Last-minute revision

  • 2's complement: invert and add 1; range $-2^{n-1}$ to $2^{n-1}-1$; single zero.
  • $A - B = A + \bar{B} + 1$; discard the end carry in 2's complement.
  • Overflow $= C_{in} \oplus C_{out}$ of the sign bit; same-sign operands only.
  • 7-bit range $-64$ to $+63$; $35 + 40$, $-35 + -40$ and $-35 - 40$ all overflow.
  • 5-bit range $-16$ to $+15$; $-10 + -13$ overflows, the other two do not.
  • Booth: 10 gives A-M, 01 gives A+M, 00 and 11 shift; product in AQ, $2n$ bits.
  • $15 \times -13 = -195$; $-13 \times 8 = -104$; $15 \times -6 = -90$.
  • Booth best case 011111 and 00000111 (two transitions); worst 01010101.
  • Non-restoring: subtract if $A \ge 0$, add if $A < 0$; $10100 \div 101$ gives quotient 4, remainder 0.
  • Floating add: align exponents, add, normalise; multiply: add exponents, multiply mantissas.
  • Adder/subtractor: XOR on B with mode M, $C_{in} = M$.

Memory hooks

  • Booth pairs: "10 Subtract, 01 Add, same-same shift".
  • Overflow: "Carries into and out of the sign must agree."
  • Two's complement: "Flip and add one."
  • Floating add: "Align, Add, Normalise" (AAN).
  • Non-restoring: "Positive subtract, negative add."

Coverage checklist

  • Addition and Subtraction: no past question; definition, adder equations.
  • Tools Compliment Representation: Jun 2024 and Jun 2025 two's complement questions.
  • Signed Addition and Subtraction: 14-mark 7-bit and 5-bit overflow numericals, signal addition and adder/subtractor question.
  • Multiplication and division: Jun 2020 carry-save multiplication.
  • Booths Algorithm: all seven Booth questions including best case and the Jun 2023 combined question.
  • Division Operation: Jun 2024 binary division, Jun 2026 restoring and non-restoring 10100 by 101.
  • Floating Point Arithmetic Operation: Dec 2024 / Jun 2026 operations, Jun 2025 fixed versus floating comparison.
  • design of Arithmetic unit: Jun 2022 / Dec 2024 short note, Jun 2023 / Jun 2024 4-bit adder/subtractor.
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