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CS-404 · Computer Org. & Architecture/Quick Revision Short Notes

Computer Org. & Architecture (CS-404) - Unit 2 Short Notes

How unit 2 is examined

This unit covers instructions and their types, the fetch-execute cycle, and the two ways of building a control unit (hardwired and microprogrammed); the marks sit in hardwired vs microprogrammed, the instruction cycle, instruction types and control memory.

Basic Concept of Instruction

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Definition. <mark>An instruction is a binary-coded command that tells the CPU which operation to perform (the opcode) and on which data (the operands).</mark>

Key points.

  1. An instruction has an opcode field, which names the operation, and one or more operand fields, which give registers, memory addresses or immediate values.
  2. A program is a sequence of instructions stored in memory and executed one after another under control of the program counter.
  3. Each instruction is broken into micro-operations, the elementary register-transfer steps that the control unit sequences.
  4. The set of all instructions a CPU understands is its instruction set, and it fixes what the programmer can ask the machine to do.

Instruction Types

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Definition. <mark>Computer instructions are classified by the kind of operation they perform into data transfer, arithmetic, logical, shift and rotate, program control, and input-output instructions.</mark>

Key points.

  1. Data transfer instructions move data between registers, memory and I/O without changing it, for example MOV R1,R2, LOAD R1,X, STORE X, PUSH, POP.
  2. Arithmetic instructions perform calculations on numbers, for example ADD, SUB, MUL, DIV, INC, DEC, NEG.
  3. Logical and bit-manipulation instructions work bit by bit, for example AND, OR, XOR, NOT, CLEAR, COMPLEMENT.
  4. Shift and rotate instructions move the bits of a word left or right, for example SHL, SHR, ROL, ROR, and are used for fast multiply or divide by 2.
  5. Program control (branch) instructions change the sequence of execution by loading the PC with a new address, for example JMP, JZ, CALL, RET, CMP.
  6. Input-output instructions transfer data between the CPU and peripherals, for example IN port, OUT port.
  7. By number of address fields, instructions are also zero-address (stack: ADD), one-address (accumulator: ADD X), two-address (ADD R1,R2) and three-address (ADD R1,R2,R3).

Answer frame. Open with the definition and the classification basis (operation performed); draw a table Class | Purpose | Example instruction; develop points 1-6 in that order with one example each; add point 7 as the format view; close with one line that the instruction set is the interface between hardware and programmer.

Asked: [7 marks] (May 2019) Give a suitable classification for computer instructions and give an example for each class. Asked: [14 marks] (Dec 2024) Write a short note on any two of: a) Instruction types, b) PCI Bus, c) Read Only Memory, d) Inter-processor communication and synchronization (write a) plus one more; PCI, ROM and IPC belong to Units 4 and 5).

Micro Instruction Formats

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Definition. <mark>A microinstruction is one word in control memory whose bits specify the control signals to be issued in one clock period and how to find the next microinstruction; a set of microinstructions is a microprogram.</mark>

Diagram.

F1 F2 F3 CD BR AD
micro-operation field 1 micro-operation field 2 micro-operation field 3 condition select branch type next address

Key points.

  1. The micro-operation fields (F1, F2, F3) encode the control signals, such as register load, ALU function or memory read, to be activated in this step.
  2. The condition field (CD) selects the status bit (zero, carry, sign) that is tested for a branch.
  3. The branch field (BR) tells the sequencer how to get the next address: next in sequence, jump, call subroutine or return.
  4. The address field (AD) holds the branch target address in control memory.
  5. In horizontal format each control signal has its own bit, so the word is wide and fast but memory is large; in vertical format the signals are encoded into few bits and need decoders, so the word is short and memory is small but decoding makes it slower.

Asked: [8 marks] (Jun 2022) What is the format of Micro Instruction in Computer Architecture explain?

Fetch and Execution cycle

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Definition. <mark>The instruction cycle is the repeated sequence of fetching an instruction from memory, decoding it, fetching its operands, executing it and storing the result, which the CPU performs for every instruction.</mark>

Diagram.

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Steps (fetch, in register transfers).

Step 1: T0: MAR <- PC                  (address of instruction goes to memory)
Step 2: T1: MDR <- M[MAR], PC <- PC+1  (memory read; PC points to next instruction)
Step 3: T2: IR <- MDR                  (instruction loaded into IR)
Step 4: T3: decode opcode in IR, control unit selects the operation
Step 5: T4...: fetch operands (MAR <- address, MDR <- M[MAR]); if indirect, read once more
Step 6: Tn: execute (ALU or transfer) and store the result in register or memory

Key points.

  1. The program counter (PC) always holds the address of the next instruction, and it is incremented during fetch so that execution continues in sequence.
  2. The memory address register (MAR) carries the address on the address bus, and the memory data register (MDR) receives the word over the data bus.
  3. The instruction register (IR) holds the fetched instruction while the control unit decodes it, so the opcode is not lost when the buses are reused.
  4. Decode means the control unit reads the opcode and works out which micro-operations and which addressing mode are needed.
  5. Operand fetch may need one more memory access when the address is indirect; register and immediate operands need none.
  6. Execution is done by the ALU or by a register transfer, and the result is written to a register or to memory (write-back).
  7. After each instruction the control unit checks for a pending interrupt; if there is none, the cycle repeats from fetch, and a branch simply loads a new value into the PC.
  8. The control unit generates every control signal, timed by the clock, that opens the right register to the bus at each step.

Answer frame. Open by defining an instruction (opcode plus operands) and the instruction cycle; draw the cycle diagram above with the interrupt check; then write the register-transfer steps T0-T3 for fetch, followed by points 4-7 for decode and execute; close with one line that the cycle repeats until the program halts.

Asked: [7 marks] (Jun 2020, Dec 2024) Explain the concepts of instruction and describe instruction cycle with neat diagram. Asked: [7 marks] (Dec 2024, Jun 2025) Discuss the sequence of steps involved in fetching an instruction from memory and executing it.

Hardwired control unit

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Definition. <mark>A hardwired control unit generates control signals with fixed combinational logic (gates, decoders, encoders and counters), so its behaviour is set by the wiring and can be changed only by redesigning the circuit.</mark>

Diagram.

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Key points.

  1. The instruction register (IR) holds the current instruction, and its opcode bits are the input of the decoder.
  2. The instruction decoder converts the opcode into one active line per instruction, such as ADD or LOAD.
  3. The clock drives a step counter and timing decoder, which produce timing signals T1, T2, T3 to say which step of the instruction is running.
  4. The control signal encoder (control logic gates) combines the instruction lines, timing signals and flag inputs with AND-OR logic to produce each control signal.
  5. Each control signal is a Boolean function, for example $\text{PCout} = T_1 + T_4\cdot \text{BRANCH}$, so signals appear exactly at the right step of the right instruction.
  6. It is fast because signals pass only through gate delays, but the design is complex and any change to the instruction set needs redesign of the logic.
  7. It is used in RISC processors and fast, simple machines.

Comparison.

Basis Hardwired Microprogrammed
Method Fixed logic gates, decoders, counters Microprogram stored in control memory
Speed Faster, only gate delay Slower, control memory access each step
Flexibility Rigid, hard to change Easy to modify by changing the microprogram
Cost Costly and complex for large instruction sets Cheaper for complex instruction sets
Design Complex, irregular, error-prone Systematic and simple
Structure Combinational logic plus timing Control memory plus sequencer
Used in RISC, simple fast CPUs CISC, complex CPUs

Answer frame. Open by defining both control units in one line each; draw the hardwired block diagram and explain IR, decoder, timing counter, encoder and how signals are generated (points 1-5); then give the comparison table row by row; close with the trade-off: speed for hardwired, flexibility for microprogrammed.

Asked: [7 marks] (May 2019, Jun 2024) Differentiate hardwired and microprogrammed control units. Asked: [7 marks] (Jun 2024, Jun 2026) Differentiate between Hardwired control unit and Micro-programmed control unit. Asked: [7 marks] (Jun 2026) What is the Difference between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.

Micro-programmed Control unit

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Definition. <mark>A microprogrammed control unit stores the control signals of every instruction as a microprogram in a control memory and generates them by reading microinstructions one after another.</mark>

Key points.

  1. Each machine instruction is executed by a small routine of microinstructions, found by mapping the opcode to a starting address in control memory.
  2. A control address register (CAR) holds the address of the current microinstruction, and a sequencer decides the next address.
  3. Changing or adding an instruction only means rewriting the microprogram, so the design is flexible and regular.
  4. It is slower than hardwired control because each step needs a control memory read, and it suits CISC machines.

microprogram sequencer

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Definition. <mark>A microprogram sequencer is the circuit that generates the address of the next microinstruction in control memory, choosing between the next address in sequence, a branch, a subroutine call or return, and a mapped address from the opcode.</mark>

Diagram.

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Key points.

  1. The sequencer sits between the instruction register and control memory, and its job is only to supply the correct address of the next microinstruction.
  2. The multiplexer selects one of the sources: CAR plus 1, the branch address in the microinstruction, the mapped address from the opcode, or the return address from the subroutine register.
  3. Status bits and the branch field decide the selection, so conditional branches are possible inside a microprogram.
  4. Working: CAR addresses control memory, the word is read into the control buffer register, its control fields go out as signals, and its next-address bits and branch field drive the multiplexer for the following address.

Asked: [7 marks] (Nov 2023) Micro-program sequencer

Control Memory

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>Control memory is the read-only memory inside the control unit that stores the microprograms; each word is a microinstruction, and the control unit reads and interprets these words to generate control signals.</mark>

Key points.

  1. A microinstruction is one control memory word specifying the micro-operations for one clock period, and a routine of them forms the microprogram for one machine instruction.
  2. Control memory is usually ROM (or writable control store), because the microprogram is fixed and must not be lost when power is off.
  3. Microinstructions of one routine are stored in consecutive addresses so that the CAR can simply increment, and branch or subroutine fields handle jumps.
  4. The arrangement may be horizontal, with one bit per control signal, giving a wide word and high parallelism, or vertical, with encoded fields, giving a short word and needing decoders.
  5. Interpretation: the opcode is mapped to the routine's start address and loaded into the CAR; the addressed word is read into the control buffer register; its fields are decoded into control signals which run the micro-operations.
  6. Next-address logic then chooses CAR plus 1, a branch address, or a return address, and the process repeats until the routine ends and control returns to the instruction fetch routine.

Answer frame. Open by defining microinstruction and control memory; draw control memory with CAR, decoder and control buffer register (same block as the sequencer figure); develop points 3-4 for arrangement and 5-6 for interpretation; close that the fetch routine is always the first microprogram executed.

Asked: [7 marks] (Dec 2024, Jun 2026) Describe how micro instructions are arranged in control memory and how they are interpreted?

Sequencing and Execution of Micro Instruction

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Low weight</span>

Definition. <mark>Microinstruction sequencing is the process of generating the address of each successive microinstruction, and execution is the issuing of its control signals to perform its micro-operations.</mark>

Key points.

  1. A micro-operation is the elementary action, such as register transfer or ALU operation, that a microinstruction triggers.
  2. The sequencer starts every instruction by loading the mapped opcode address into the CAR; the fetch routine's address is loaded first.
  3. Next-address generation gives sequential execution (CAR plus 1), unconditional branch, conditional branch on a status bit, subroutine call and return.
  4. Execution steps: read the microinstruction from control memory, place it in the control buffer register, decode its fields into control signals, perform the micro-operations, then form the next address.
  5. At the end of the routine, an end-of-routine branch loads the address of the instruction fetch routine.

Asked: [7 marks] (Jun 2020) Explain sequencing and execution of micro instruction.

Last-minute revision

  • Instruction = opcode + operand(s); the CPU classes are data transfer, arithmetic, logical, shift, program control, I/O.
  • Instruction cycle = fetch, decode, operand fetch, execute, store, with an interrupt check.
  • Fetch: MAR <- PC; MDR <- M[MAR], PC <- PC+1; IR <- MDR.
  • Hardwired control = decoder + step counter + encoder gates; fast, rigid, used in RISC.
  • Microprogrammed control = control memory + sequencer; slower, flexible, used in CISC.
  • Microinstruction = control field + condition + branch + address field.
  • Horizontal format: wide word, one bit per signal, fast; vertical: encoded, short, slower.
  • CAR holds the address of the current microinstruction; control buffer register holds the word read.
  • Sequencer chooses next address: CAR+1, branch, mapped opcode address, or return.
  • Control memory is ROM (or writable control store) and stores the microprograms.

Memory hooks

  • Fetch order P-M-I: PC to MAR, Memory read, IR load.
  • Hardwired = Hard, Hasty, Hard to change; microprogrammed = Memory, Modifiable, Mildly slow.
  • Sequencer chooses among N-B-M-R: Next, Branch, Map, Return.
  • Horizontal = wide and quick; Vertical = tall (encoded) and thrifty.
  • Instruction classes D-A-L-S-C-I: Data, Arithmetic, Logic, Shift, Control, I/O.

Coverage checklist

  • Basic Concept of Instruction: definition of opcode and operand (also covered inside Q4).
  • Instruction Types: Q9 (May 2019), Q1 (Dec 2024).
  • Micro Instruction Formats: Q2 (Jun 2022).
  • Fetch and Execution cycle: Q4 (Jun 2020, Dec 2024), Q5 (Dec 2024, Jun 2025).
  • Hardwired control unit: Q6 (May 2019, Jun 2024), Q7 (Jun 2024, Jun 2026), Q8 (Jun 2026).
  • Micro-programmed Control unit: definition and comparison (Q6, Q7, Q8).
  • microprogram sequencer: Q11 (Nov 2023).
  • Control Memory: Q3 (Dec 2024, Jun 2026).
  • Sequencing and Execution of Micro Instruction: Q10 (Jun 2020).
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