Computer Org. & Architecture (CS-404) Unit 1 Notes

How unit 1 is examined

Covers the block structure of a computer, CPU registers, stack organisation, instruction formats, buses, register transfer and addressing modes; the desktop structure, general register organisation and bus structure carry the most marks.

Structure of Desktop Computers

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. <mark>A desktop computer is a stored-program machine whose CPU, main memory and I/O modules are joined by a bus interconnection on a motherboard; computer architecture is the set of attributes visible to the programmer, while organisation is how they are realised in hardware.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-01" viewBox="0 0 424 252" width="424" height="252" role="img" aria-label="Structural view: CPU (ALU, CU, registers), Memory, Input and Output units joined by the system bus"><style>#dsfig-u1-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-01 .t{fill:#16181D;font-weight:500}#dsfig-u1-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-01 .dot{fill:#16181D}#dsfig-u1-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-01 .ah{fill:#454C5A}#dsfig-u1-01 .ah.hi{fill:#2340B8}#dsfig-u1-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-01 .e{stroke:#B1B7C3}html.dark #dsfig-u1-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-01 .t{fill:#E6E8ED}html.dark #dsfig-u1-01 .t.inv{fill:#0F1115}html.dark #dsfig-u1-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-01 .dot{fill:#E6E8ED}html.dark #dsfig-u1-01 .ann{fill:#8FA3FF}html.dark #dsfig-u1-01 .lbl{fill:#858D9C}html.dark #dsfig-u1-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-01 .ah{fill:#B1B7C3}html.dark #dsfig-u1-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah1" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh1" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L191,40" marker-end="url(#ah1)"/><path class="e" d="M231,40 L363,40" marker-end="url(#ah1)"/><path class="e" d="M212,61 L212,105" marker-end="url(#ah1)" marker-start="url(#ah1)"/><path class="e" d="M212,191 L212,147" marker-end="url(#ah1)" marker-start="url(#ah1)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">In</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Out</text><circle class="n" cx="212" cy="126" r="18"/><text class="t" x="212" y="126" dy=".35em" text-anchor="middle">Bus</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Structural view: CPU (ALU, CU, registers), Memory, Input and Output units joined by the system bus</figcaption></figure>

Key points.

The functional view has four functions: data processing, data storage, data movement between the computer and outside, and control of all three.
The structural view has four parts: CPU, main memory, I/O modules and the system interconnection (bus).
The CPU has the ALU for arithmetic and logic, the control unit (CU) that issues timing and control signals, and registers for fast temporary storage.
Main memory (RAM) holds the running program and its data; each word is reached by an address.
The I/O subsystem connects keyboard, mouse, display, disk and network through interface controllers.
On the motherboard the chipset (north and south bridge) links CPU, RAM, expansion slots and peripheral interfaces such as SATA and USB.
Data flows Input to memory or CPU, is processed in the ALU, is stored in memory and leaves through Output, all under the CU's control signals.
Architecture covers the instruction set (ISA), datapath and control design, memory hierarchy and I/O organisation, seen as levels from gates up to high-level programs.

Answer frame. Open with the definition; draw the functional view (four functions) then the structural block diagram with the bus; develop points 3-7 in order; close with the data-flow line. For "basic principles of architecture" lead with point 8.

Pitfall: Do not draw only one view when the question says "functional and structural views".

Asked: [7 marks] (Dec 2020, Jun 2020, Jun 2022, Nov 2023) Draw the functional and structural views of a computer system and explain in detail; with a block diagram, explain the basic organization of a computer system. Asked: [8 marks] (Jun 2022, Nov 2023, Jun 2026) Explain the structure of desktop system in detail; draw and explain the architecture of a computer system. Asked: [? marks] (Jun 2023) Explain basic principles of computer architecture.

CPU: General Register Organization

Definition. <mark>In general register organization the CPU holds several general-purpose registers whose outputs pass through two multiplexers to the ALU, and the ALU result is loaded back into a register chosen by a decoder, all set by a control word.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-02" viewBox="0 0 338 338" width="338" height="338" role="img" aria-label="Registers R1-R7, multiplexers MuxA and MuxB (select operands), ALU, decoder (selects destination), control word"><style>#dsfig-u1-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-02 .t{fill:#16181D;font-weight:500}#dsfig-u1-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-02 .dot{fill:#16181D}#dsfig-u1-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-02 .ah{fill:#454C5A}#dsfig-u1-02 .ah.hi{fill:#2340B8}#dsfig-u1-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-02 .e{stroke:#B1B7C3}html.dark #dsfig-u1-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-02 .t{fill:#E6E8ED}html.dark #dsfig-u1-02 .t.inv{fill:#0F1115}html.dark #dsfig-u1-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-02 .dot{fill:#E6E8ED}html.dark #dsfig-u1-02 .ann{fill:#8FA3FF}html.dark #dsfig-u1-02 .lbl{fill:#858D9C}html.dark #dsfig-u1-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-02 .ah{fill:#B1B7C3}html.dark #dsfig-u1-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah2" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh2" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58,46 L149.1,76.4" marker-end="url(#ah2)"/><path class="e" d="M58,120 L149.1,89.6" marker-end="url(#ah2)"/><path class="e" d="M53.4,198.6 L154.2,97.8" marker-end="url(#ah2)"/><path class="e" d="M53.4,53.4 L154.2,154.2" marker-end="url(#ah2)"/><path class="e" d="M58,132 L149.1,162.4" marker-end="url(#ah2)"/><path class="e" d="M58,206 L149.1,175.6" marker-end="url(#ah2)"/><path class="e" d="M187,89 L278.1,119.4" marker-end="url(#ah2)"/><path class="e" d="M187,163 L278.1,132.6" marker-end="url(#ah2)"/><path class="e" d="M298,145 L298,277" marker-end="url(#ah2)"/><path class="e" d="M284.6,284.6 L54.8,54.8" marker-end="url(#ah2)"/><path class="e" d="M188,298 L277,298" marker-end="url(#ah2)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">R1</text><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">R2</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">R7</text><circle class="n" cx="169" cy="83" r="18"/><text class="t" x="169" y="83" dy=".35em" text-anchor="middle">MA</text><circle class="n" cx="169" cy="169" r="18"/><text class="t" x="169" y="169" dy=".35em" text-anchor="middle">MB</text><circle class="n" cx="298" cy="126" r="18"/><text class="t" x="298" y="126" dy=".35em" text-anchor="middle">ALU</text><circle class="n" cx="298" cy="298" r="18"/><text class="t" x="298" y="298" dy=".35em" text-anchor="middle">Dec</text><circle class="n" cx="169" cy="298" r="18"/><text class="t" x="169" y="298" dy=".35em" text-anchor="middle">CW</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Registers R1-R7, multiplexers MuxA and MuxB (select operands), ALU, decoder (selects destination), control word</figcaption></figure>

Key points.

Registers are the fastest storage in the CPU, so keeping operands in them avoids slow memory access and speeds up execution.
MuxA and MuxB each select one register as an ALU input using the select fields SELA and SELB.
The ALU performs the operation chosen by the OPR field and its result goes to the bus.
A 3-to-8 decoder driven by SELD enables the load of one destination register.
One clock pulse performs the whole micro-operation, for example $R1 \leftarrow R2 + R3$.
Accumulator (AC) is the implicit register for arithmetic results, MAR holds the memory address, MDR holds the data read or written, IR holds the current instruction and PC holds the next instruction address.
MAR is connected to the address bus and MDR to the data bus, so all memory traffic passes through them.
Example: for the fetch, PC goes to MAR, memory data goes to MDR, MDR goes to IR and PC increments; IR then supplies opcode and operand address for execute.

Register	Function	Typical use
Accumulator	Holds one ALU operand and the result	ADD X gives AC = AC + M[X]
Index	Holds an offset added to an address	Array access, EA = base + XR
Stack pointer	Holds address of the stack top	PUSH, POP, subroutine calls
General purpose	Holds any operand, address or result	R1 = R2 + R3, flexible

Answer frame. For "explain general register organization" define it, draw the diagram, explain MuxA, MuxB, ALU, decoder, then give the R1 = R2 + R3 example and close on speed. For the register list, one line each on MAR, MDR, AC, IR, PC then the fetch example (point 8). For the comparison, give the table above with a one-line definition each.

Asked: [7 marks] (May 2019, Jun 2020) Explain the working of MAR, MDR, AC, IR, PC; purpose of general register, memory register and instruction register with example. Asked: [7 marks] (Dec 2020, Jun 2024) Explain general register organization. Asked: [7 marks] (Dec 2024) Differentiate between accumulator, index, stack and general-purpose registers. Asked: [7 marks] (Jun 2024) Explain the role and significance of registers in a CPU's general register organization.

Memory Register

Definition. <mark>Memory registers are the Memory Address Register (MAR) and Memory Data Register (MDR), which buffer the address and the data of every memory access.</mark>

Key points.

MAR holds the address of the location to be read or written and drives the address bus.
MDR holds the word just read from, or about to be written to, memory and sits on the data bus.
For a read, the address goes to MAR, a Read signal is given and the word arrives in MDR; for a write, data is placed in MDR and a Write signal stores it.
MAR is as wide as the address and MDR as wide as the memory word.

Instruction Register

Definition. <mark>The Instruction Register (IR) holds the instruction currently being executed.</mark>

Key points.

After the fetch, the instruction word is copied from memory into IR through MDR.
The opcode field goes to the control unit's decoder, which generates the control signals.
The address or operand field goes to MAR or the ALU path as needed.
IR keeps the instruction stable for the whole execute phase, and is overwritten by the next fetch.

Control Word

Definition. <mark>A control word is a string of bits whose fields select the registers, ALU operation and destination, so that one micro-operation executes in one clock pulse.</mark>

Key points.

In the general register organisation it has four fields, SELA (3 bits), SELB (3 bits), SELD (3 bits) and OPR (5 bits), 14 bits in all.
SELA and SELB choose the source registers, SELD the destination and OPR the ALU function.
Code 000 selects external Input, 001 to 111 select R1 to R7; OPR 00101 is subtract and 00010 is add.
Example: $R1 \leftarrow R2 - R3$ needs SELA=010, SELB=011, SELD=001, OPR=00101, so the control word is 010 011 001 00101.
Loading the word into the control unit performs the operation at the next clock; a new word gives the next micro-operation.

Asked: [7 marks] (Jun 2025) How does the control word help in micro-operation execution? Illustrate with an example.

Stack Organization

Definition. <mark>A stack is a last-in first-out (LIFO) memory area addressed by a stack pointer (SP) that always points to the top item.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-03" viewBox="0 0 424 252" width="424" height="252" role="img" aria-label="Stack CPU: SP = stack pointer, Stk = memory stack (top two items feed ALU), DR = data register, CU = control unit"><style>#dsfig-u1-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-03 .t{fill:#16181D;font-weight:500}#dsfig-u1-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-03 .dot{fill:#16181D}#dsfig-u1-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-03 .ah{fill:#454C5A}#dsfig-u1-03 .ah.hi{fill:#2340B8}#dsfig-u1-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-03 .e{stroke:#B1B7C3}html.dark #dsfig-u1-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-03 .t{fill:#E6E8ED}html.dark #dsfig-u1-03 .t.inv{fill:#0F1115}html.dark #dsfig-u1-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-03 .dot{fill:#E6E8ED}html.dark #dsfig-u1-03 .ann{fill:#8FA3FF}html.dark #dsfig-u1-03 .lbl{fill:#858D9C}html.dark #dsfig-u1-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-03 .ah{fill:#B1B7C3}html.dark #dsfig-u1-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah3" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh3" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L191,40" marker-end="url(#ah3)"/><path class="e" d="M230.8,49.4 L365.2,116.6" marker-end="url(#ah3)" marker-start="url(#ah3)"/><path class="e" d="M212,191 L212,61" marker-end="url(#ah3)" marker-start="url(#ah3)"/><path class="e" d="M58.4,207.4 L363.6,131.1" marker-end="url(#ah3)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">SP</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">Stk</text><circle class="n" cx="384" cy="126" r="18"/><text class="t" x="384" y="126" dy=".35em" text-anchor="middle">ALU</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">DR</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">CU</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Stack CPU: SP = stack pointer, Stk = memory stack (top two items feed ALU), DR = data register, CU = control unit</figcaption></figure>

Key points.

PUSH decrements or increments SP and writes the item at the new top; POP reads the top and moves SP back.
A register stack is small and fast; a memory stack uses a portion of RAM and lets SP address it.
Stack instructions are zero-address: ADD, SUB, MUL take both operands from the top two items and push the result, so no operand field is needed.
Arithmetic expressions are evaluated in postfix (reverse Polish) form, which needs no brackets.
Stacks also support subroutine calls, recursion and interrupts by saving return addresses.
Overflow (push on full) and underflow (pop on empty) must be checked.

Example. $X=(A-B)*(((C-D*E)/F)/G)$ in postfix is A B - C D E * - F / G / *. Program:

Step 1: PUSH A; PUSH B; SUB          -> (A-B)
Step 2: PUSH C; PUSH D; PUSH E; MUL  -> (A-B), C, D*E
Step 3: SUB                          -> (A-B), C-D*E
Step 4: PUSH F; DIV                  -> (A-B), (C-D*E)/F
Step 5: PUSH G; DIV                  -> (A-B), ((C-D*E)/F)/G
Step 6: MUL                          -> (A-B)*(((C-D*E)/F)/G)
Step 7: POP X

Answer frame. Open with the LIFO definition; draw the stack CPU diagram; explain SP, PUSH, POP, ALU on the top two items; close with 0-address advantage. For the program, write postfix first, then the PUSH sequence with the stack after each step.

Asked: [7 marks] (Jun 2026) Explain Stack based central processing unit organization with block diagram. Asked: [7 marks] (Jun 2026) WAP to evaluate $X=(A-B)*(((C-D*E)/F)/G)$ using stack organized computer with 0-address instruction.

Instruction Format

Definition. <mark>An instruction format is the layout of an instruction word as an opcode field followed by zero to three address (operand) fields.</mark>

Key points.

The opcode says which operation to perform and the address fields say where the operands are (and often the result).
Three-address: ADD R1, R2, R3 ($R1 \leftarrow R2+R3$) gives short programs but long instructions.
Two-address: ADD R1, R2 ($R1 \leftarrow R1+R2$) overwrites one operand, and is the most common format.
One-address: ADD X ($AC \leftarrow AC + M[X]$) uses the accumulator implicitly.
Zero-address: ADD takes both operands from the stack top; instructions are shortest but need more of them.
Fewer addresses mean shorter instructions but longer programs; more addresses mean the reverse.

Asked: [7 marks] (Nov 2023) Explain the instruction formats for computer system. Asked: [6 marks] (Jun 2022) Define the instruction format? (first half; see I/O System)

ALU

Definition. <mark>The Arithmetic Logic Unit is the CPU circuit that performs arithmetic (add, subtract) and logic (AND, OR, NOT, shift) operations on operands.</mark>

Key points.

It is combinational logic; operands come from registers (or the accumulator) and the result returns to a register.
The control unit selects the operation through the function-select lines (OPR).
It also sets status flags such as carry, zero, sign and overflow.
Its width (8, 32, 64 bits) fixes the word size the CPU processes at once.

I/O System

Definition. <mark>The I/O system is the set of interfaces and controllers that let the CPU and memory exchange data with peripherals whose speed and format differ from the processor's.</mark>

Key points.

An interface is needed to match speed, data format and voltage between slow devices and the fast CPU.
Programmed I/O: the CPU polls the device status and moves each word itself, so the CPU is kept busy.
Interrupt-driven I/O: the device signals when ready, the CPU runs an interrupt routine, and no time is lost polling.
DMA: a DMA controller moves blocks directly between device and memory, and interrupts the CPU only at the end.
Instruction format is the opcode plus operand fields, as defined above.

Asked: [6 marks] (Jun 2022) Define the instruction format? Explain I/O System in detail.

bus

Definition. <mark>A bus is a set of parallel wires shared by several units to carry data, addresses or control signals.</mark>

Key points.

The data bus carries data both ways; its width sets how many bits move at once.
The address bus carries the memory or I/O address one way, from CPU; its width fixes the addressable memory ($2^n$ locations for $n$ lines).
The control bus carries Read, Write, clock, interrupt and bus-grant signals.
Only one device may drive a bus at a time, so tri-state buffers or multiplexers are used.

CPU and Memory Program Counter

Definition. <mark>The Program Counter (PC) holds the address of the next instruction; together with the memory register (MAR) and instruction register (IR) it drives the fetch-execute cycle.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-04" viewBox="0 0 338 209" width="338" height="209" role="img" aria-label="Fetch path: PC to MAR, memory read to MDR, MDR to IR, IR decoded by CU"><style>#dsfig-u1-04 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-04 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-04 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-04 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-04 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-04 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-04 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-04 .t{fill:#16181D;font-weight:500}#dsfig-u1-04 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-04 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-04 .dot{fill:#16181D}#dsfig-u1-04 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-04 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-04 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-04 .ah{fill:#454C5A}#dsfig-u1-04 .ah.hi{fill:#2340B8}#dsfig-u1-04 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-04 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-04 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-04 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-04 .e{stroke:#B1B7C3}html.dark #dsfig-u1-04 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-04 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-04 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-04 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-04 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-04 .t{fill:#E6E8ED}html.dark #dsfig-u1-04 .t.inv{fill:#0F1115}html.dark #dsfig-u1-04 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-04 .dot{fill:#E6E8ED}html.dark #dsfig-u1-04 .ann{fill:#8FA3FF}html.dark #dsfig-u1-04 .lbl{fill:#858D9C}html.dark #dsfig-u1-04 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-04 .ah{fill:#B1B7C3}html.dark #dsfig-u1-04 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-04 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-04 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-04 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah4" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh4" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L148,40" marker-end="url(#ah4)"/><path class="e" d="M188,40 L277,40" marker-end="url(#ah4)"/><path class="e" d="M298,59 L298,148" marker-end="url(#ah4)"/><path class="e" d="M279,169 L190,169" marker-end="url(#ah4)"/><path class="e" d="M150,169 L61,169" marker-end="url(#ah4)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">PC</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">MAR</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="298" cy="169" r="18"/><text class="t" x="298" y="169" dy=".35em" text-anchor="middle">MDR</text><circle class="n" cx="169" cy="169" r="18"/><text class="t" x="169" y="169" dy=".35em" text-anchor="middle">IR</text><circle class="n" cx="40" cy="169" r="18"/><text class="t" x="40" y="169" dy=".35em" text-anchor="middle">CU</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Fetch path: PC to MAR, memory read to MDR, MDR to IR, IR decoded by CU</figcaption></figure>

Key points.

PC is as wide as the address bus and is incremented after each fetch (or loaded with a new address by a jump or branch).
MAR receives the PC value and places it on the address bus; MDR receives the word from the data bus.
IR holds the fetched instruction; its opcode is decoded by the control unit.
Fetch steps: $T0: MAR \leftarrow PC$; $T1: MDR \leftarrow M[MAR], PC \leftarrow PC+1$; $T2: IR \leftarrow MDR$.
Decode: the CU decodes the opcode in IR at $T3$.
Execute: the operand address in IR is sent to MAR, the operand is read into MDR and the ALU operation is done; for a jump, IR's address is loaded into PC.
The cycle then repeats with the incremented PC.

Answer frame. Open by defining PC, MAR, IR; draw the fetch path; give the T0-T2 steps, then the execute role of IR and MAR; close by saying the cycle repeats.

Asked: [7 marks] (Dec 2024, Jun 2025) Discuss the structure and role of the program counter, instruction register and memory register during a fetch-execute cycle. Asked: [? marks] (Jun 2023) Explain: i) Stack organization ii) Bus structure and addressing modes iii) Fetch and execution cycle (see the topics above, below and this one).

Bus Structure

Definition. <mark>A bus structure is the arrangement of shared address, data and control lines that interconnects the CPU, memory and I/O devices.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-05" viewBox="0 0 424 286.4" width="424" height="286.4" role="img" aria-label="System bus: Add = address bus, Dat = data bus, Ctl = control bus, connecting CPU, memory and I/O"><style>#dsfig-u1-05 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-05 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-05 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-05 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-05 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-05 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-05 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-05 .t{fill:#16181D;font-weight:500}#dsfig-u1-05 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-05 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-05 .dot{fill:#16181D}#dsfig-u1-05 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-05 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-05 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-05 .ah{fill:#454C5A}#dsfig-u1-05 .ah.hi{fill:#2340B8}#dsfig-u1-05 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-05 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-05 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-05 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-05 .e{stroke:#B1B7C3}html.dark #dsfig-u1-05 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-05 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-05 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-05 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-05 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-05 .t{fill:#E6E8ED}html.dark #dsfig-u1-05 .t.inv{fill:#0F1115}html.dark #dsfig-u1-05 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-05 .dot{fill:#E6E8ED}html.dark #dsfig-u1-05 .ann{fill:#8FA3FF}html.dark #dsfig-u1-05 .lbl{fill:#858D9C}html.dark #dsfig-u1-05 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-05 .ah{fill:#B1B7C3}html.dark #dsfig-u1-05 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-05 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-05 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-05 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah5" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh5" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58.8,49.4 L193.2,116.6" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M56,53.6 L196,172.6" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M53.4,56.1 L198.6,230.3" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M212,61 L212,165.2" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M368,53.6 L228,172.6" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M212,61 L212,105" marker-end="url(#ah5)" marker-start="url(#ah5)"/><path class="e" d="M370.6,56.1 L225.4,230.3" marker-end="url(#ah5)" marker-start="url(#ah5)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">IO</text><circle class="n" cx="212" cy="126" r="18"/><text class="t" x="212" y="126" dy=".35em" text-anchor="middle">Add</text><circle class="n" cx="212" cy="186.2" r="18"/><text class="t" x="212" y="186.2" dy=".35em" text-anchor="middle">Dat</text><circle class="n" cx="212" cy="246.4" r="18"/><text class="t" x="212" y="246.4" dy=".35em" text-anchor="middle">Ctl</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">System bus: Add = address bus, Dat = data bus, Ctl = control bus, connecting CPU, memory and I/O</figcaption></figure>

Key points.

The address bus is unidirectional (CPU to memory or I/O), the data bus is bidirectional, and the control bus carries Read, Write, clock and interrupt signals.
A single-bus structure is cheap and simple but only one transfer can occur at a time, so it can become a bottleneck.
Multiple-bus structures (separate memory bus and I/O bus) allow parallel transfers at higher cost.
Read: CPU puts the address on the address bus, asserts Read, memory puts data on the data bus, CPU latches it.
Write: CPU puts address and data on the buses and asserts Write, and memory stores the word.
Bus arbitration decides which master (CPU or DMA) controls the bus when two want it.
Bus width and clock speed together set the bandwidth.
SCSI is a parallel peripheral bus that connects up to 8 or 16 devices (disks, tapes) on one daisy chain with arbitration; RAM is the volatile read-write main memory.

Answer frame. Open with the definition; draw the three-bus diagram with arrows; explain the read and write steps; then arbitration and bandwidth; close with the applications (CPU-memory-I/O communication). For a "any two" question, choose Bus structure plus RAM or SCSI, each with definition, diagram and features.

Asked: [14 marks] (Jun 2024, Jun 2025) Write a short note on any two: a) Bus structure b) SCSI Bus c) Random Access Memory d) Inter processor arbitration.

Register Transfer Language-Bus and Memory Transfer

Definition. <mark>Register Transfer Language (RTL) is a symbolic notation that describes micro-operations, the elementary operations on data stored in registers, and the control conditions under which they occur.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-06" viewBox="0 0 338 166" width="338" height="166" role="img" aria-label="P: R2 <- R1; control P enables the load input of R2 so R1 copies into R2 at the clock edge"><style>#dsfig-u1-06 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-06 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-06 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-06 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-06 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-06 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-06 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-06 .t{fill:#16181D;font-weight:500}#dsfig-u1-06 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-06 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-06 .dot{fill:#16181D}#dsfig-u1-06 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-06 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-06 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-06 .ah{fill:#454C5A}#dsfig-u1-06 .ah.hi{fill:#2340B8}#dsfig-u1-06 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-06 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-06 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-06 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-06 .e{stroke:#B1B7C3}html.dark #dsfig-u1-06 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-06 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-06 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-06 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-06 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-06 .t{fill:#E6E8ED}html.dark #dsfig-u1-06 .t.inv{fill:#0F1115}html.dark #dsfig-u1-06 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-06 .dot{fill:#E6E8ED}html.dark #dsfig-u1-06 .ann{fill:#8FA3FF}html.dark #dsfig-u1-06 .lbl{fill:#858D9C}html.dark #dsfig-u1-06 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-06 .ah{fill:#B1B7C3}html.dark #dsfig-u1-06 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-06 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-06 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-06 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah6" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh6" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,126 L277,126" marker-end="url(#ah6)"/><path class="e" d="M184.8,50.5 L280.5,114.4" marker-end="url(#ah6)"/><g class="wl"><rect x="213.1" y="74" width="40.8" height="18" rx="9"/><text class="t" x="233.5" y="83" dy=".35em" text-anchor="middle">load</text></g><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">R1</text><circle class="n" cx="298" cy="126" r="18"/><text class="t" x="298" y="126" dy=".35em" text-anchor="middle">R2</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">P</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">P: R2 <- R1; control P enables the load input of R2 so R1 copies into R2 at the clock edge</figcaption></figure>

Key points.

A register is named by capital letters (MAR, R1); the arrow $\leftarrow$ means transfer, so $R2 \leftarrow R1$ copies R1 into R2 and R1 is unchanged.
A control condition is written before a colon, so $P: R2 \leftarrow R1$ means transfer only when P = 1.
Several transfers at the same time are separated by commas, e.g. $T: R2 \leftarrow R1, R1 \leftarrow R2$.
Memory transfer: read is $R1 \leftarrow M[MAR]$ and write is $M[MAR] \leftarrow R1$.
Bus transfer: $BUS \leftarrow R1$ then $R2 \leftarrow BUS$; a mux or tri-state buffers choose the source register.
Instructions are written in RTL, e.g. LOAD: $AC \leftarrow M[X]$; ADD: $AC \leftarrow AC + M[X]$; STORE: $M[X] \leftarrow AC$.

Answer frame. Define RTL and micro-operation; draw R1, R2 with control P; explain the meaning of P: R2 <- R1; then give memory and bus transfers and the LOAD or ADD examples.

Asked: [7 marks] (May 2019) What is RTL? Explain $P: R2 \leftarrow R1$ and draw suitable block diagram. Asked: [7 marks] (Jun 2024) What is register transfer language? Explain the representation of instructions in RTL with suitable examples.

addressing modes

Definition. <mark>An addressing mode is the rule by which the operand address field of an instruction is interpreted to find the effective address (EA) of the operand.</mark>

Key points.

Implied: the operand is implicit, so no address field is used (e.g. CMA complements AC).
Immediate: the operand itself is in the instruction, so no memory access is needed for it (e.g. ADD #5).
Register: the operand is in a CPU register named in the instruction, so EA is the register (e.g. ADD R1).
Register indirect: the register holds the memory address, so $EA = (R)$.
Direct: the address field is the address of the operand, so $EA = A$.
Indirect: the address field points to a word that holds the operand's address, so $EA = M[A]$.
Indexed: $EA = A + XR$, used for arrays; relative: $EA = PC + A$, used for branches; base register: $EA = BR + A$, used for relocation.
Auto-increment or decrement: register indirect where the register is then stepped, used for tables.

Mode	EA	Example (A=500, M[500]=800, R1=400, XR=100, PC=201)
Direct	A	500
Indirect	M[A]	800
Register indirect	R1	400
Indexed	A + XR	600
Relative	PC + A	701

Answer frame. Define the mode; list the modes in the order above; give the EA formula and an example instruction for each, using the table; close with which gives flexibility (indexed) and which is fastest (register, immediate).

Asked: [7 marks] (Dec 2020, Nov 2023) What are different addressing modes? Explain each of them. Asked: [7 marks] (Nov 2023) Explain the addressing modes with suitable examples.

Last-minute revision

Functional view: data processing, storage, movement, control; structural view: CPU, memory, I/O, bus.
General register organisation control word is 14 bits: SELA 3, SELB 3, SELD 3, OPR 5.
Fetch: $MAR \leftarrow PC$; $MDR \leftarrow M[MAR]$, $PC \leftarrow PC+1$; $IR \leftarrow MDR$.
MAR sits on the address bus, MDR on the data bus, IR holds the current instruction, PC the next.
Stack is LIFO; ALU uses the top two items; zero-address instructions have no operand field.
Postfix of the paper expression: A B - C D E * - F / G / *.
Instruction formats: three, two, one and zero address.
Address bus is one-way, data bus is two-way, control bus carries Read, Write and clock.
$n$ address lines give $2^n$ locations.
$EA$: direct A, indirect M[A], indexed A+XR, relative PC+A, register indirect (R).
I/O techniques: programmed, interrupt-driven, DMA.

Memory hooks

"MAR Addresses, MDR Data": the A and D tell the bus each register uses.
"Fetch = PC, MAR, MDR, IR": follow the letters in order.
Stack "LIFO, top two into ALU, zero address".
Addressing modes "I-I-R-D-I-I-R": Implied, Immediate, Register, Direct, Indirect, Indexed, Relative.
Bus lines "A one way, D two way, C control".

Coverage checklist

Structure of Desktop Computers: Q2, Q14, Q18 (functional and structural views, desktop structure, principles of architecture)
CPU: General Register Organization: Q4, Q5, Q6, Q7
Memory Register: covered via Q3 and Q4 (MAR, MDR)
Instruction Register: covered via Q3 and Q4 (IR)
Control Word: Q8
Stack Organization: Q12, Q13, Q19 (i)
Instruction Format: Q9, Q17 (first half)
ALU: no past question
I/O System: Q17
bus: no past question
CPU and Memory Program Counter: Q3, Q19 (iii)
Bus Structure: Q1, Q19 (ii)
Register Transfer Language-Bus and Memory Transfer: Q10, Q11
addressing modes: Q15, Q16, Q19 (ii)

Account

Computer Org. & Architecture (CS-404) - Unit 1 Short Notes

How unit 1 is examined

Structure of Desktop Computers

CPU: General Register Organization

Memory Register

Instruction Register

Control Word

Stack Organization

Instruction Format

ALU

I/O System

bus

CPU and Memory Program Counter

Bus Structure

Register Transfer Language-Bus and Memory Transfer

addressing modes

Last-minute revision

Memory hooks

Coverage checklist