Industrial Electronics (EX-504 (A)) - Unit 5 Short Notes

1.0 Power Electronic Converters & Power Supplies

1.1 Single-Phase Rectifiers

Half-Wave Rectifier (R Load):

• Conducts only during positive half-cycle.

• Average output voltage:

$$V_{avg} = \frac{V_m}{\pi}$$

• RMS output voltage:

$$V_{rms} = \frac{V_m}{2}$$

• Ripple Factor (RF) = 1.21 (high).

Half-Wave Rectifier (RL Load):

• Inductance causes current continuity; diode conducts beyond 180° until current drops to zero.

• Average voltage:

$$V_{avg} = \frac{V_m}{\pi} (1 + \cos\alpha)$$

, where \(\alpha\) = firing angle (for controlled rectifier) or extinction angle (for uncontrolled with inductance).

Full-Wave Rectifiers:

Full-Wave (Bridge, R Load):

$$V_{avg} = \frac{2V_m}{\pi}$$

RF = 0.48 (much lower than half-wave).

Advantages of Full-Wave: Higher efficiency, lower ripple, better transformer utilization (bridge).
Disadvantages: More diodes (bridge), higher PIV (center-tapped), complexity.

[!TIP]

Exam Focus: Derive \(V_{avg}\) for half-wave RL—show integration over conduction angle. Compare PIV and transformer requirements for center-tapped vs. bridge.

1.2 Switch Mode Power Supplies (SMPS) & Switched Regulators

Block Diagram:

Switched-Mode Voltage Regulators:

Full-Bridge Regulator from Buck:

• Isolated version: Replace buck switch with full-bridge of 4 switches driving a transformer primary.

• Secondary rectified and filtered gives isolated output. Duty cycle \(D\) controls \(V_{out}\).

Design Calculation (Buck Converter Inductor):

For continuous conduction mode (CCM):

$$\Delta I_L = \frac{(V_{in} - V_{out}) \cdot D}{f_s \cdot L}$$

where \(D = V_{out}/V_{in}\), \(f_s\) = switching frequency.

\boxed{L = \frac{(V_{in} - V_{out}) \cdot D}{f_s \cdot \Delta I_L}}

SMPS vs. Linear Regulator:

[!TIP]

Common Pitfall: In buck design, ensure CCM: \(I_{out} > \frac{\Delta I_L}{2}\). Use worst-case \(V_{in}\) for L calculation.

1.3 Uninterruptible Power Supply (UPS) & Power Conditioning

On-Line UPS Block Diagram:

1. Rectifier/Charger: AC → DC (charges battery, feeds inverter).

2. Battery: Backup storage.

3. Inverter: DC → AC (always active).

4. Static Transfer Switch: Bypass for maintenance/failure.

5. Output Filter: Smooths inverter AC.
   Operation: Normal: Rectifier → Inverter → Load. Mains fail: Battery → Inverter → Load.

Active Power Line Conditioner (APLC):

• Shunt active filter: Injects compensating currents to cancel harmonics/reactive power.

• Series active filter: Inserted in line to cancel voltage sags/swells.

• Principle: Detect disturbance via sensors → DSP/controller → PWM inverter → inject corrective waveform.

2.0 Power Semiconductor Switching Devices

2.1 Silicon Controlled Rectifier (SCR)

Construction & Two-Transistor Model:

• pnp-npn (Q1, Q2) coupled: \(I_A = I_{C1} + I_{C2} = \alpha_1 I_A + I_{CBO1} + \alpha_2 I_K + I_{CBO2}\).

• Assuming \(I_{CBO} \approx 0\): \(I_A = \frac{I_{CBO1} + I_{CBO2}}{1 - (\alpha_1 + \alpha_2)}\).

• Latch-up when \(\alpha_1 + \alpha_2 \geq 1\).

Static V-I Characteristics:

• Forward Blocking: \(V_{AK} < V_{BO}\), \(I_A\) small (leakage).

• Forward Conduction: \(V_{AK} \approx 1–2V\) (on-state).

• Reverse Blocking: \(V_{AK} < -V_{RBO}\), \(I_A\) small until breakdown.

• Latching Current (\(I_L\)): Minimum \(I_A\) to maintain conduction after gate pulse removed.

• Holding Current (\(I_H\)): Minimum \(I_A\) to keep SCR on; \(I_H < I_L\).

Turn-On Methods:

1. Forward Voltage Triggering: \(V_{AK} > V_{BO}\) (avalanche).

2. Gate Triggering: Positive gate current (most common).

3. dv/dt Triggering: High \(\frac{dV}{dt}\) causes charge flow (undesired).

4. Thermal Triggering: High temperature increases leakage → latch-up.

Turn-Off (Commutation):

• Natural (Line Commutation): AC source forces current to zero (e.g., in phase-controlled rectifiers).

• Forced Commutation:

  • Self-Commutated: Auxiliary SCR (e.g., in bridge circuits).

  • External: RC, LC, resonant circuits (e.g., Class-D commutation).

Causes of Damage & Protection:

[!TIP]

Exam Focus: Mark \(I_L\) and \(I_H\) on V-I curve. Explain forced commutation with LC circuit diagram. Crowbar: SCR triggered across supply to short and blow fuse.

2.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)

Construction & Operation:

• Enhancement Mode: \(V_{GS} > V_{th}\) creates channel (N-channel: positive).

• Depletion Mode: Channel exists at \(V_{GS}=0\); \(V_{GS}\) depletes it.

• N-channel vs. P-channel: N-channel has lower \(R_{DS(on)}\), faster.

Characteristics:

• Output (\(I_D\) vs \(V_{DS}\)): Triode region (\(V_{GS} > V_{th}, V_{DS} < V_{GS}-V_{th}\)), saturation (\(V_{DS} \geq V_{GS}-V_{th}\)).

• Transfer (\(I_D\) vs \(V_{GS}\)): \(I_D = k(V_{GS} - V_{th})^2\) (saturation).

Key Parameters:

• Threshold Voltage (\(V_{th}\)): Minimum \(V_{GS}\) to conduct.

• Transconductance (\(g_m\)): \(g_m = \frac{\partial I_D}{\partial V_{GS}}\) (measure of gate control).

Power MOSFET:

• Structure: Vertical, with source/body shorted (to avoid parasitic thyristor latch-up).

• Ratings: \(V_{DS}\) up to 1000V, \(I_D\) up to 100A, \(R_{DS(on)}\) mΩ.

• Advantages over BJT: Voltage-controlled (high input impedance), fast switching (no minority carrier storage), no secondary breakdown.

• Applications: Switch-mode power supplies, motor drives, DC-DC converters.

[!TIP]

Short Note Focus: Emphasize lateral vs. vertical structure, \(R_{DS(on)}\) temperature dependence, safe operating area (SOA).

2.3 Insulated Gate Bipolar Transistor (IGBT)

Construction & Operation:

• MOSFET gate controls BJT collector current.

• On-state: Gate voltage > \(V_{GE(th)}\) → MOSFET conducts → injects electrons into p-base → BJT turns on.

• Off-state: MOSFET off → no electron injection → BJT off.

Equivalent Circuit: MOSFET + BJT (pnp).

Characteristics:

• Output (\(V_{CE}\) vs \(I_C\)): Similar to BJT but with MOSFET input.

• Transfer (\(V_{GE}\) vs \(I_C\)): Threshold \(V_{GE(th)}\), then linear/saturation.

Features & Comparison:

Applications: Motor drives (AC/DC), inverters, UPS, traction.

[!TIP]

Exam Focus: IGBT is “MOSFET input, BJT output.” Explain why it combines high input impedance with low saturation voltage. Note tail current in turn-off.

2.4 Comparative Analysis & Power Losses

Applications Summary:

Power Losses:

1. Conduction Losses: \(P_{cond} = I_{rms}^2 \cdot R_{on}\) (MOSFET/IGBT) or \(V_{TM} \cdot I_{avg}\) (SCR).

2. Switching Losses: \(P_{sw} = \frac{1}{2} V \cdot I \cdot (t_{rise} + t_{fall}) \cdot f_{sw}\).

   • MOSFET: Lower switching loss (fast).

   • IGBT: Higher switching loss (tail current).

   • SCR: Low switching loss (only turn-on controlled; turn-off by commutation).

3.0 Operational Amplifier (OP-AMP) Based Circuits

3.1 Basic OP-AMP Characteristics & Configurations

Ideal OP-AMP:

• \(A_{OL} \to \infty\), \(Z_{in} \to \infty\), \(Z_{out} = 0\), BW \(\to \infty\), CMRR \(\to \infty\), zero offset.

Inverting Amplifier:

• Gain: \(A_v = -\frac{R_f}{R_{in}}\) (virtual ground at inverting input).

• Input impedance ≈ \(R_{in}\).

Non-Inverting Amplifier:

• Gain: \(A_v = 1 + \frac{R_f}{R_{in}}\).

• Input impedance very high (≈ \(Z_{in}\) of op-amp).

Key Parameters:

• CMRR: \(CMRR = \frac{A_d}{A_c}\) (rejects common-mode signals).

• Slew Rate (SR): Max \(\frac{dV_{out}}{dt}\) (V/µs) – limits large-signal BW.

• Gain-Bandwidth Product (GBW): Constant for single-pole op-amp: \(A_v \cdot BW = \text{GBW}\).

[!TIP]

Derivation Focus: Use virtual ground and Kirchhoff’s current law (KCL) for inverting gain. For non-inverting, voltage divider.

3.2 OP-AMP as Signal Processing Circuits

Comparator:

• No feedback. Output saturates to \(+V_{sat}\) or \(-V_{sat}\) based on \(V_+ > V_-\).

• Hysteresis needed to avoid noise-induced switching (add positive feedback → Schmitt trigger).

Window Comparator:

• Two comparators: one for upper limit, one for lower.

• Output high only when \(V_{in}\) between \(V_{ref1}\) and \(V_{ref2}\).

Low-Pass Filter (Integrator):

• Feedback capacitor \(C_f\), input resistor \(R_{in}\).

• \(V_{out} = -\frac{1}{R_{in} C_f} \int V_{in} dt\) (for DC input, output ramps until saturation).

• Add \(R_f\) in parallel with \(C_f\) to limit low-frequency gain.

Function Generator (Sine, Square, Triangle):

• Wien Bridge Oscillator → Sine wave.

• Comparator (Schmitt trigger) → Square wave from triangle/sine.

• Integrator → Triangle from square.

• Cascade: Oscillator → Comparator → Integrator.

Wien Bridge Oscillator:

• Frequency: \(f = \frac{1}{2\pi RC}\) (for balanced bridge).

• Condition for Oscillation: Loop gain \(A\beta \geq 1\); for non-inverting amp, \(A \geq 3\) (since \(\beta = \frac{1}{3}\) at resonance).

• Amplitude Stabilization: Use nonlinear element (thermistor, diodes, FET) in feedback to reduce gain as amplitude increases.

[!TIP]

Short Note Focus: Wien bridge: RC series-parallel network in positive feedback. Explain why frequency selective? At \(f_0\), phase shift = 0°, \(\beta = 1/3\).

4.0 Programmable Logic Controllers (PLCs)

4.1 Fundamentals & Architecture

Functions: Logic control, sequencing, timing, counting, data handling, communication.
Applications: Assembly lines, process control, machine automation.

Functional Block Diagram:

1. Power Supply: AC/DC to power modules.

2. CPU: Executes user program, manages memory, communications.

3. I/O Modules:

   • Digital (discrete): ON/OFF (sensors, actuators).

   • Analog: Continuous signals (0–10V, 4–20mA).

4. Programming Device: PC/laptop with software.

Operating Modes:

• Program Mode: Edit/download program.

• Run Mode: Execute program, control process.

• Test/Monitor Mode: Run while monitoring/tweaking variables.

4.2 PLC Programming & Languages

Ladder Logic (LD):

• Rungs: Horizontal logic lines.

• Contacts: Input conditions (NO = —| |—, NC = —|/|—).

• Coils: Outputs (—( )—).

• Flow: Left to right, top to bottom (scan cycle).

Basic Examples:

1. Motor Start-Stop (Seal-in):

   Start PB (NO) in parallel with seal-in contact (auxiliary contact of motor relay) → coil. Stop PB (NC) in series.

2. Interlocking: NC contact of one output in series with another to prevent simultaneous activation.

3. Timers:

   • TON (On-Delay): Output ON after preset time if input persists.

   • TOF (Off-Delay): Output stays ON for preset time after input turns OFF.

4. Counters:

   • CTU (Count Up): Increment on each pulse; preset value triggers output.

   • CTD (Count Down).

IEC 61131-3 Languages:

• IL (Instruction List): Text-based (like assembly).

• FBD (Function Block Diagram): Graphical blocks (like logic gates).

• ST (Structured Text): High-level text (Pascal-like).

• SFC (Sequential Function Chart): Steps and transitions (for sequential processes).

4.3 PLC Systems & Integration

Communication Protocols:

• Modbus: Simple master-slave (RTU/ASCII/TCP).

• Profibus: DP for fast I/O, PA for process automation.

• Ethernet/IP: Industrial Ethernet (CIP protocol).

• DeviceNet: CAN-based for device-level networking.

Interface with Power Electronics:

• PLC output (low power) → Opto-isolator (galvanic isolation) → Gate driver (amplifies current/voltage) → SCR/IGBT gate.

• Protection: Snubber, current feedback to PLC analog input.

PLC vs. Relay Controllers:

Event-Driven Device:

• Concept: PLC responds to asynchronous events (interrupts) rather than cyclic scan.

• Implementation: High-speed counters (HSC) for precise pulse counting, interrupt inputs for immediate response (e.g., emergency stop).

• Use: Motion control, high-speed packaging, safety systems.

[!TIP]

Short Note Focus: For event-driven, contrast with cyclic scan. Mention HSC and interrupt tasks in PLCs like Siemens S7-1200/1500.

5.0 Important Short Note Topics (Frequently Asked)

5.1 Switch Mode Power Supply (SMPS)

• Definition: Switching regulator with high-frequency transformer/inductor for efficient AC/DC or DC-DC conversion.

• Topologies: Flyback, forward, half-bridge, full-bridge, buck, boost.

• Advantages: Small size, high efficiency (80–90%), wide input range.

• Disadvantages: EMI, complexity, cost.

• Applications: Computers, telecom, industrial controls.

5.2 Power MOSFET

• Structure: Vertical, with source/body tied (prevents parasitic thyristor).

• Ratings: \(V_{DS}\) up to 1000V, \(I_D\) up to 100A, \(R_{DS(on)}\) < 10 mΩ.

• Advantages over BJT: Voltage-controlled (high \(Z_{in}\)), fast switching (no charge storage), no secondary breakdown, easier parallel.

• Disadvantages: Higher on-resistance than IGBT at high voltage, sensitive to ESD.

• Applications: Switch-mode power supplies, DC-DC converters, low-voltage motor drives.

5.3 Wien Bridge Oscillator

• Circuit: Op-amp with positive feedback via Wien network (series RC || parallel RC).

• Frequency of Oscillation: \(f = \frac{1}{2\pi RC}\).

• Condition: Loop gain \(A\beta \geq 1\); for non-inverting op-amp, \(A \geq 3\) (since \(\beta = 1/3\) at \(f_0\)).

• Amplitude Stabilization: Use thermistor (NTC) in series with \(R_f\) or diodes in feedback to reduce gain as output increases.

• Output: Low-distortion sine wave.

5.4 Relaxation Oscillator (OP-AMP Based)

• Circuit: Op-amp as Schmitt trigger with RC feedback from output to inverting input.

• Operation: Capacitor charges/discharges through \(R\) until thresholds reached → output toggles → square wave.

• Frequency: \(f \approx \frac{1}{2RC \ln\left(\frac{V_{UT}}{V_{LT}}\right)}\), where \(V_{UT}, V_{LT}\) = upper/lower thresholds.

• Output: Square wave; capacitor voltage = triangle wave.

• Applications: Clock generation, pulse generation, function generator (as square wave source).

5.5 Electronic Crowbar Protection

• Purpose: Protect power devices (SCR, MOSFET, IGBT) from overcurrent.

• Circuit: SCR (or Triac) connected across supply output, triggered by overcurrent detection (current transformer, sense resistor).

• Operation: Overcurrent → trigger SCR → short circuit → supply current limited → fuse blows or supply shuts down.

• Advantage: Fast action (µs), isolates faulty device.

• Disadvantage: Requires fuse replacement; may cause voltage sag.

5.6 Active Power Line Conditioner (APLC)

• Purpose: Mitigate harmonics, correct power factor, regulate voltage (sags/swells).

• Configuration:

  • Shunt Active Filter: Injects compensating currents (parallel with load).

  • Series Active Filter: Inserted in line to cancel voltage disturbances (series with load).

• Principle: Sensors measure voltage/current → DSP calculates reference → PWM inverter injects corrective waveform.

• Applications: Sensitive loads (hospitals, data centers), renewable integration.

5.7 Event-Driven Device (PLC Context)

• Definition: Device that responds immediately to external events (interrupts) rather than waiting for cyclic scan.

• PLC Implementation:

  • High-Speed Counters (HSC): Count pulses independent of scan cycle (for encoders, tachometers).

  • Interrupt Inputs: Trigger a dedicated interrupt routine (e.g., emergency stop, high-speed pulse).

• Advantage: Deterministic response (µs latency), suitable for motion control, safety.

• Disadvantage: Requires careful programming to avoid conflicts with cyclic tasks.

• Example: Siemens S7-1200 HSC, Allen-Bradley GuardLogix safety interrupts.

Final Note: Always refer to past papers for question patterns. Focus on derivations (rectifiers, SCR model, op-amp gains), comparisons (devices, rectifiers, PLC vs relay), and diagram explanations (V-I curves, block diagrams, ladder logic). Use boxed formulas for quick revision.