CMOS DESIGN (EC-603 (B)) - Unit 5 Short Notes

UNIT 5: CMOS DESIGN (Based on EC-603(B) May 2023 Paper)

I. MOSFET FUNDAMENTALS & THRESHOLD VOLTAGE

Threshold Voltage (Vₜ)

• Definition: The minimum gate-to-source voltage ($$\displaystyle V_{GS} $$) required to create a conducting channel between source and drain, turning the MOSFET from OFF to ON.

• Physical Significance: Determines the switching point and power consumption of CMOS circuits.

Mathematical Expression

For an nMOS transistor in an p-type substrate:

$$V_{T} = V_{FB} + 2\phi_{F} + \frac{\sqrt{2q \varepsilon_{si} N_{A} \cdot 2\phi_{F}}}{C_{ox}}$$

Where:

• $$\displaystyle V_{FB} $$ = Flat-band voltage

• $$\displaystyle \phi_{F} $$ = Surface potential (≈ $$\displaystyle kT/q \cdot \ln(N_{A}/n_{i}) $$)

• $$\displaystyle N_{A} $$ = Substrate doping concentration

• $$\displaystyle C_{ox} = \varepsilon_{ox}/t_{ox} $$ = Oxide capacitance per unit area

Parameter Dependencies

[!TIP] Exam Focus: Be prepared to derive/explain the $$\displaystyle V_T $$ equation and qualitatively state how process variations (like $$\displaystyle t_{ox} $$ or $$\displaystyle N_A $$) affect it. The body effect ($$\displaystyle V_{SB} > 0 $$) increases $$\displaystyle V_T $$: $$\displaystyle V_T = V_{T0} + \gamma (\sqrt{|\phi_F + V_{SB}|} - \sqrt{|\phi_F|}) $$.

II. COMBINATIONAL LOGIC DESIGN

A. NMOS Logic Gates

• Realization: Uses a pull-down network (PDN) of series/parallel nMOS transistors to pull output LOW when the Boolean function is TRUE. A passive load (e.g., resistor or depletion-load nMOS) pulls output HIGH when PDN is OFF.

• Example: Z = A(D + C) + BE

  • Step 1: Write in sum-of-products: $$\displaystyle Z = A \cdot (D + C) + B \cdot E $$.

  • Step 2: Implement directly as PDN. Series = AND, Parallel = OR.

  • PDN: A in series with (D parallel C), in parallel with (B series E).

  • Logic: Z = 0 (LOW) when either [A AND (D OR C)] is TRUE OR [B AND E] is TRUE. Otherwise, Z = 1 (HIGH).

  • Pull-up: Simple load resistor or depletion nMOS.

  • Limitation: Logic inversion (PDN implements function in complement form for active-high output), slow HIGH-to-LOW transition (PDN resistance), static power dissipation (DC path from VDD to GND when output is HIGH with depletion load).

B. Transmission Gate Logic

• Structure & Operation: A parallel combination of an nMOS and pMOS transistor, controlled by complementary signals (C and $\overline{C}$). Acts as a bidirectional, low-resistance switch.

  • When C=1, $$\displaystyle \overline{C}=0 $$: Both transistors ON → Low $$\displaystyle R_{on} $$ path.

  • When C=0, $$\displaystyle \overline{C}=1 $$: Both transistors OFF → High impedance.

• Transient Analysis (Resistor Model):

  • Replace TG with equivalent resistance $$\displaystyle R_{eq} \approx R_{on,n} // R_{on,p} $$.

  • RC time constant $$\displaystyle \tau = R_{eq} \cdot C_{load} $$ determines propagation delay.

  • Advantage over single nMOS switch: Symmetric rise/fall times, no threshold voltage drop issue (full swing to rails).

• Ex-OR Gate using Transmission Gates:

  • Design: Use TG to pass either A or $\overline{A}$ to output based on B.

  • Circuit: Output node connected to A via TG controlled by B, and to $\overline{A}$ via TG controlled by $\overline{B}$. Requires an inverter to generate $\overline{A}$.

  • Operation: B=0 → Pass A; B=1 → Pass $\overline{A}$. Implements $$\displaystyle A \oplus B = A\overline{B} + \overline{A}B $$.

[!TIP] Common Pitfall: In NMOS logic, remember the PDN implements the complement of the desired function for a simple load. For complex functions, use De Morgan's to convert to PDN form. For TG-based design, ensure complementary controls are available.

III. SEQUENTIAL LOGIC DESIGN

A. State Diagram & Sequence Detection

• Sequence Detector for "101":

  • Overlap Allowed: Last bits of detected sequence can be start of new sequence.

  • States (S0, S1, S2):

    • S0: No match / initial state.

    • S1: Last input was 1.

    • S2: Last two inputs were 10.

  • Transitions:

    • S0 --1--> S1; S0 --0--> S0

    • S1 --0--> S2; S1 --1--> S1 (stay in S1 on consecutive 1s)

    • S2 --1--> S3 (Detected! Output=1); S2 --0--> S0

  • Output: Z=1 only on transition to S3 (which is S2 with input 1). Often S3 is merged with S1 for overlap.

B. Flow Tables for Sequential Circuits

• Fundamental Mode: Inputs change only when circuit is stable (no simultaneous changes).

• Minimum Row Reduced Flow Table Derivation:

  1. List all states and their present/next state/output entries for all input combinations.

  2. Group compatible states (states that can merge without causing conflict in outputs or next states for same inputs).

  3. Find maximum compatibles and form a prime compatibles table.

  4. Select minimal set of compatibles that cover all states and are closed (all next states are within the set).

  5. Assign state variables to each row of reduced table.

C. Asynchronous Sequential Circuits

• Analysis using Flow Tables: Follows the reduction process above. Identify races (multiple state changes) and critical races (leading to incorrect state). Use binary state assignment to avoid races (e.g., assign adjacent states to Gray-coded numbers).

• Toggle Circuit Behavior:

  • A simple circuit with one input X and one output Z that toggles (Z changes state) on each rising edge of X.

  • Flow Table: Two stable states (say a with Z=0, b with Z=1).

    • In a: X=0 → stay a; X=1 → go to b (unstable, then settles).

    • In b: X=0 → stay b; X=1 → go to a.

  • Analysis: Shows dynamic behavior and potential for hazards if input changes before circuit settles.

[!TIP] Exam Strategy: For flow table reduction, practice identifying compatible state pairs (same output for same inputs, next states compatible). The May 2023 question specified conditional output changes, so carefully note output dependencies on both current state and inputs.

IV. FABRICATION TECHNOLOGY & DEVICE STRUCTURES

A. NMOS Fabrication Process Steps

1. Substrate Preparation: p-type Si wafer.

2. Field Oxidation (LOCOS): Grow thick $$\displaystyle SiO_2 $$ (field oxide) to define active regions. Mask 1.

3. Gate Oxidation: Grow thin, high-quality $$\displaystyle SiO_2 $$ ($$\displaystyle t_{ox} \approx 100 $$ Å) in active region.

4. Poly-silicon Deposition & Patterning: Deposit poly-Si, pattern to form gate electrode. Mask 2.

5. Source/Drain Diffusion: Use gate as mask for ion implantation (As, P) to create n+ regions. Self-aligned.

6. Contact Opening: Etch $$\displaystyle SiO_2 $$ to expose S/D and gate for metallization. Mask 3.

7. Metallization: Deposit & pattern Al (or Cu) for interconnects. Mask 4.

B. BiCMOS Technology

• Circuit Diagram & Operation:

  • Inverter: Input drives bipolar npn base and nMOS gate.

  • Pull-up: pMOS transistor.

  • Pull-down: Bipolar npn transistor (emitter to output, collector to GND).

  • Operation:

    • IN=0: nMOS OFF, npn OFF (base low), pMOS ON → Output pulled HIGH to $$\displaystyle V_{DD} $$.

    • IN=1: nMOS ON provides base current to npn, turning it ON strongly. npn sinks current → Output pulled LOW.

• Advantages over CMOS:

  • Higher Speed: Bipolar transistor has much higher transconductance ($$\displaystyle g_m $$) and lower output resistance than MOS, driving capacitive loads faster.

  • Higher Drive Capability: Can source/sink larger currents.

  • Lower Power (vs. TTL): Still has static power (npn base current), but less than TTL.

C. Integrated Resistors

• Construction using MOS Transistor:

  • Operate a MOSFET in linear/triode region ($$\displaystyle V_{DS} < V_{GS} - V_T $$).

  • Treat channel as a voltage-controlled resistor: $$\displaystyle R_{on} \approx \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T - \frac{V_{DS}}{2})} $$.

  • Layout: Use a long, narrow nMOS (large L, small W) with source and drain connected to resistor terminals. Gate tied to a DC bias voltage ($$\displaystyle V_{GS} $$) to set resistance.

• Resistance Calculation: $$\displaystyle R = \frac{L}{\mu_n C_{ox} \frac{W}{V_{GS} - V_T}} $$ (for small $$\displaystyle V_{DS} $$). Precise value depends on process parameters and $$\displaystyle V_{GS} $$.

[!TIP] Key Point: BiCMOS combines CMOS input (low static power) with bipolar output (high speed/drive). NMOS fabrication uses self-aligned gate process. Resistors using MOS are voltage-dependent and non-linear unless $$\displaystyle V_{DS} $$ is very small.

V. ANALOG CMOS CIRCUITS & MODELS

A. Sub-threshold Region Operation

• Region: $$\displaystyle V_{GS} < V_T $$ (weak inversion). Channel exists but very thin; current dominated by diffusion.

• Sub-threshold MOS Model:

$$I_D \approx I_{D0} \cdot e^{\frac{V_{GS} - V_T}{nV_T}} \cdot \left(1 - e^{-\frac{V_{DS}}{V_T}}\right)$$

Where:

*   $$\displaystyle I_{D0} = \mu_n C_{ox} \frac{W}{L} (n-1) V_T^2 $$ (process-dependent current)

*   $$\displaystyle n = 1 + \frac{C_{dep}}{C_{ox}} $$ (sub-threshold slope factor, typically 1.2-1.5)

*   $$\displaystyle V_T = kT/q $$ (thermal voltage ≈ 26 mV at 300K)

• Exponential I-V: Current varies exponentially with $$\displaystyle V_{GS} $$. Very high transconductance efficiency ($$\displaystyle g_m/I_D $$) → ultra-low-power applications (IoT, biomedical).

• Drawback: High sensitivity to process, voltage, temperature (PVT); slower speed.

B. Voltage Reference Circuits

• High-Sensitivity Design: Often uses bandgap reference (BGR) core.

  • Principle: Combine a PTAT (proportional to absolute temperature) voltage with a CTAT (complementary to absolute temperature) voltage to get a temperature-independent reference.

  • Simplified Circuit: Two BJTs (or substrate pnp) at different current densities generate $$\displaystyle \Delta V_{BE} \propto T $$. This is amplified and added to $$\displaystyle V_{BE} $$ (which decreases with T).

  • High Sensitivity: Achieved by careful start-up circuit and low-noise design (large device sizes, filtering). Output voltage ≈ 1.25 V (silicon bandgap voltage).

• Temperature Compensation: The core BGR principle inherently cancels first-order T-dependence. Higher-order compensation uses curvature correction circuits.

C. CMOS Inverter DC Analysis

• Voltage Transfer Characteristic (VTC):

  • Region 1 (V_in LOW): M1 OFF, M2 ON → Output HIGH ($$\displaystyle V_{out} \approx V_{DD} $$).

  • Region 2 (Transition): Both MOSFETs in saturation (initially), then M1 enters linear. $$\displaystyle V_{in} = V_{out} = V_{M} $$ at switching point ($$\displaystyle V_{M} \approx V_{DD}/2 $$ for $$\displaystyle \beta_n = \beta_p $$).

  • Region 3 (V_in HIGH): M1 ON, M2 OFF → Output LOW ($$\displaystyle V_{out} \approx 0 $$).

• Effect of Channel Length Modulation (λ):

  • Causes finite output resistance in saturation.

  • In VTC: Makes transition region slightly less sharp, reduces gain (slope) in linear region.

  • In DC Load Line: Slight curvature in saturation regions.

• Gate Voltage Limits for Stable Operation (M1/M2 Conduction):

  • To ensure both transistors are never OFF simultaneously (which would cause output floating and high impedance), the input must be such that when one is just entering saturation, the other is still in linear region.

  • Condition for M1 just at edge of saturation: $$\displaystyle V_{GS1} = V_{in} > V_T $$ and $$\displaystyle V_{DS1} = V_{out} = V_{in} - V_T $$.

  • Condition for M2 still ON (linear): $$\displaystyle V_{GS2} = V_{DD} - V_{in} > V_T $$ and $$\displaystyle V_{DS2} = V_{out} < V_{GS2} - V_T $$.

  • Inference: For stable operation, input range must be $$\displaystyle V_T < V_{in} < V_{DD} - V_T $$. Within this, there is always a non-overlap region where both are ON, providing a definite DC path and stable output.

[!TIP] Critical Formula: Sub-threshold current is exponential in $$\displaystyle V_{GS} $$. For BGR, $$\displaystyle V_{ref} = V_{BE} + K \cdot \Delta V_{BE} $$. Inverter DC analysis, find $$\displaystyle V_M $$ by solving $$\displaystyle I_{Dn}(V_M) = I_{Dp}(V_{DD}-V_M) $$ with $$\displaystyle V_{DS} = V_{GS} $$ for both (in saturation at $$\displaystyle V_M $$).

BOXED KEY RESULTS:

• Threshold Voltage: \boxed{V_{T} = V_{FB} + 2\phi_{F} + \frac{\sqrt{2q \varepsilon_{si} N_{A} \cdot 2\phi_{F}}}{C_{ox}}}

• Sub-threshold Current: \boxed{I_D \approx I_{D0} \cdot e^{\frac{V_{GS} - V_T}{nV_T}} \cdot \left(1 - e^{-\frac{V_{DS}}{V_T}}\right)}

• Bandgap Reference Principle: \boxed{V_{ref} = V_{BE} + K \cdot \Delta V_{BE} \propto V_{BG} \text{ (T-independent)}}