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EC-603 (B) · CMOS DESIGN/Unsolved PYQ Paper

EC-603-B CMOS Design - May 2023 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

  1. 7 Marks
    aDefine Threshold Voltage. Express threshold voltage and discuss dependency of $V_T$ on various parameters.
    How to answer
    • Definition of threshold voltage VT as gate-source voltage for strong inversion onset
    • Expression for VT including flat-band, depletion charge and oxide terms
    • Dependence on substrate doping, oxide thickness, temperature, body bias, channel length
  2. 7 Marks
    bRealize NMOS complex logic gates using the Boolean function $Z = A(D + C) + BE$.
    How to answer
    • Write Boolean function $Z = A(D+C)+BE$ and its complement for pull-down
    • Series-parallel NMOS pull-down network design
    • Load / pull-up arrangement and complete complex gate schematic
  3. 7 Marks
    aThe output $Z$ of a fundamental mode, two input sequential circuit is to change from 0 to 1 only when $x_2$ changes from 0 to 1 while $x_1=1$. The output changes from 1 to 0 only when $x_1$ changes from 1 to 0 while $x_2=1$. Find a minimum row reduced flow table.
    How to answer
    • List input combinations and specified 0-to-1 and 1-to-0 transitions
    • Construct primitive flow table with stable states
    • Merge compatible rows to get minimum row reduced flow table
  4. 7 Marks
    bDraw the state diagrams of a sequence detector which can detect 101.
    How to answer
    • Define states for 0, 10, 101 detection
    • Draw state transition diagram with input labels
    • Mark reset/overlapping sequence handling for 101
  5. 14 Marks
    Analyze the behavior of an asynchronous sequential toggle circuit with flow table.
    How to answer
    • Describe asynchronous toggle circuit operation and excitation
    • Present flow table with present state, inputs and next state/output
    • Analyze races, cycles and stable states behavior
  6. 7 Marks
    aExplain with neat diagrams the various NMOS fabrication technology.
    How to answer
    • Outline NMOS fabrication steps: substrate, oxidation, diffusion, polysilicon
    • Provide neat cross-sectional diagrams for each step
    • Mention isolation, gate formation and metallization
  7. 7 Marks
    bDraw and explain BiCMOS inverter circuit.
    How to answer
    • Show BiCMOS inverter circuit combining MOS and bipolar devices
    • Explain pull-up/pull-down operation
    • Highlight advantages: high drive, low power
  8. 7 Marks
    aHow to construct a resistor using MOS transistor?
    How to answer
    • Principle of MOS as resistor in linear/saturation with gate bias
    • Connection types: diode-connected, gate-biased
    • Expression for equivalent resistance and limitations
  9. 7 Marks
    bWith the help of required expressions explain Sub-threshold MOS Model.
    How to answer
    • Define subthreshold conduction when VGS < VT
    • Give exponential IDS expression with subthreshold slope
    • Explain applications and effects on leakage
  10. 7 Marks
    aDiscuss the transient analysis of CMOS Transmission gate by replacing it with resistor equivalent circuit.
    How to answer
    • Replace CMOS transmission gate by ON-resistance equivalent
    • Set up RC charging/discharging model
    • Derive propagation delay and discuss rise/fall asymmetry
  11. 7 Marks
    bDesign an Ex-OR gate using Transmission gate Logic.
    How to answer
    • Show transmission gate structure with NMOS+PMOS in parallel
    • Connect gates to implement XOR logic
    • Explain operation for all input combinations
  12. 7 Marks
    aDraw and explain the circuit diagram for voltage reference with high sensitivity.
    How to answer
    • Present high-sensitivity voltage reference circuit diagram
    • Explain reference generation principle and sensitivity improvement
    • Discuss temperature/supply independence
  13. 7 Marks
    bExplain the Inverter DC characteristics and also give your inference on MOSFET channel length. Estimate the maximum and minimum voltage on the gate of M1 in Fig. that ensures that neither M1 or M2 shut off. (Assume the necessary data).
    Given: Differential pair with M1 and M2 drains to 5V through ID1, ID2 currents, sources common to stacked 20/2 NMOS tail with Vbias3, Vbias4 to ground carrying ISS=40mA downward. Gate of M1 is VI1, gate of M2 is VI2=2.5V connected via 2.5V source to ground.
    How to answer
    • Sketch inverter DC transfer characteristics and operating regions
    • Infer effect of MOSFET channel length on characteristics
    • Use given differential pair with $I_{SS}=40\,mA$ to estimate max/min $V_{I1}$ keeping M1,M2 ON
  14. 14 Marks
    Write a short note on the following:
    1. i)Mealy machine
    2. ii)Bipolar technology
    How to answer
    • Mealy machine: output depends on present state and input, features and diagram
    • Bipolar technology: NPN/PNP structure, fabrication and characteristics
    • Comparison relevance to CMOS
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