UNIT 4: CMOS DESIGN - EXAM-FOCUSED SHORT NOTES

(Based on EC-603(B) - May 2023 Exam Paper & Recurring Themes)

1.0 MOSFET FUNDAMENTALS & CHARACTERISTICS

1.1 Threshold Voltage (V_T)

• Definition: The minimum gate-to-source voltage (V_GS) required to create a conducting channel between source and drain, turning the MOSFET ON.

• Physical Significance: Determines the switching point of a logic gate. A higher V_T reduces leakage but slows switching; a lower V_T increases speed but raises static power.

• Long-Channel Expression:

$$V_T = V_{FB} + 2\phi_F + \frac{\sqrt{2q\varepsilon_{si} N_A 2\phi_F}}{C_{ox}}$$

Where:

*   V<sub>FB</sub> = Flat-band voltage

*   ϕ<sub>F</sub> = Fermi potential

*   N<sub>A</sub> = Substrate doping concentration

*   C<sub>ox</sub> = Oxide capacitance per unit area

• Key Dependencies:

  | Parameter | Effect on V_T | Reason | | :--- | :--- | :--- | | Oxide Thickness (t_ox) | ↑ t_ox → ↓ V_T | C_ox ∝ 1/t_ox | | Substrate Doping (N_A) | ↑ N_A → ↑ V_T | Increases depletion charge | | Gate Material Work Function | Difference from Si work function shifts V_FB | | | Fixed Oxide Charge | Positive charge → ↑ V_T | Shifts V_FB |

• Body Effect (Back-Gate Bias): V_T increases when source-to-substrate voltage (V_SB) > 0.

$$\boxed{V_T = V_{T0} + \gamma \left( \sqrt{|2\phi_F + V_{SB}|} - \sqrt{|2\phi_F|} \right)}$$

Where γ = Body effect coefficient.

[!TIP] Exam Focus: Be prepared to derive or explain the V_T expression. Questions often ask to "discuss dependency" – use the table format in your answer.

1.2 Sub-threshold Region & Model

• Operation: Region where V_GS < V_T. The channel is not strongly inverted, but a weak surface potential exists.

• Exponential I-V Characteristic:

$$I_D \approx I_0 e^{(V_{GS} - V_T)/nV_T} \left(1 - e^{-V_{DS}/V_T}\right)$$

Where:

*   I<sub>0</sub> = Current at V<sub>GS</sub> = V<sub>T</sub>

*   n = Sub-threshold swing factor (n ≥ 1)

*   V<sub>T</sub> (thermal) = kT/q ≈ 26 mV at 300K

• Sub-threshold Slope (SS): Measure of gate control efficiency.

$$\boxed{SS = \frac{d(\log_{10} I_D)}{d V_{GS}} = \frac{\ln(10) \cdot n kT}{q} \approx 60 \text{ mV/dec} \cdot n \text{ at 300K}}$$

*   **Ideal SS = 60 mV/dec** (at 300K, n=1).

*   **Significance:** Lower SS → steeper turn-off → lower leakage power for a given V<sub>T</sub> → critical for ultra-low-power design.

1.3 DC Characteristics & Channel Length Modulation

• CMOS Inverter DC Transfer Curve:

  • V_TC (Threshold/M Switching Point): V_in = V_out. For symmetric inverter (β_n = β_p), V_TC ≈ V_DD/2.

  • Noise Margins:

    • NM_L = V_IL - V_OL (Low)

    • NM_H = V_OH - V_IH (High)

    • Where V_IL, V_IH are points where slope = -1.

• Channel Length Modulation (λ): Output conductance due to finite drain-induced barrier lowering (DIBL) in short-channel devices.

$$I_D \propto (1 + \lambda V_{DS})$$

*   **Impact:** Reduces gain (A<sub>v</sub> = -g<sub>m</sub>/g<sub>ds</sub>), increases static power in ratioed logic.

• Inference on Channel Length from Circuit Behavior:

  • Long Channel (λ ≈ 0): High output resistance, sharp V_TC, ideal square-law I-V.

  • Short Channel: Lower output resistance (higher λ), V_T roll-off with L, increased DIBL, degraded noise margins.

  • Circuit Limit: If V_DSAT < V_GS - V_T, device may not stay in saturation → reduced gain.

[!TIP] Common Pitfall: Confusing channel length modulation (λ) with DIBL. λ is the effect (output conductance), DIBL is a cause (V_T reduction with V_DS).

2.0 COMBINATIONAL LOGIC DESIGN (NMOS/CMOS)

2.1 NMOS Logic & Complex Gate Realization

• Design Principle: Implement Boolean complement of function in Pull-Down Network (PDN). PDN connects output to V_SS (0) when function = 1.

  • Series → AND

  • Parallel → OR

  • De Morgan for complement: F = A·B → PDN = A series B; F = A+B → PDN = A || B.

• Realization of Z = A(D+C) + BE:

  1. Complement: Z' = (A(D+C) + BE)' = (A(D+C))' · (BE)' (De Morgan)

  2. = (A' + (D+C)') · (B' + E')

  3. = (A' + D'C') · (B' + E')

  4. PDN for Z' (Pull-Up Network, PUN): PUN implements Z' (since CMOS is complementary).

     • (A' + D'C') → A' in parallel with (D' series C')

     • (B' + E') → B' in parallel with E'

     • Final PUN: (A' || (D'·C')) · (B' || E') [Series of two parallel blocks]

  5. PDN: Complement of PUN → (A · (D+C)) + (B·E) → A series (D parallel C) in parallel with (B series E).

  DiagramCANVAS: NMOS PDN for Z = A(D+C)+BE. Show output node Z. PDN: Two parallel branches: Branch1: A in series with (D||C). Branch2: B in series with E. All transistors NMOS. Load is enhancement-mode NMOS or depletion-mode NMOS as pull-up.

• Ratioed vs. CMOS:

  | Feature | Ratioed Logic (e.g., NMOS with load) | CMOS | | :--- | :--- | :--- | | Static Power | High (DC path V_DD→GND) | Near Zero (no DC path) | | Noise Margin | Poor (V_TC not at V_DD/2) | Excellent (symmetric) | | Area | Smaller (no complementary network) | Larger (2x transistors) | | Speed | Faster (single network) | Slower (series stacks) |

2.2 CMOS Inverter & Gates

• Standard CMOS Inverter:

  DiagramCANVAS: CMOS Inverter. Input Vin to gates of PMOS (top, source to VDD) and NMOS (bottom, source to VSS). Drains connected to output Vout.

  • Operation:

    • Vin = 0 → PMOS ON, NMOS OFF → Vout = V_DD

    • Vin = V_DD → PMOS OFF, NMOS ON → Vout = 0

    • Vin ≈ V_TC → Both partially ON → high impedance.

  • Static Power: Only leakage (sub-threshold, junction leakage). No direct V_DD-GND path.

• Basic CMOS Gates:

  • NAND: PDN = 2-input series; PUN = 2-input parallel.

  • NOR: PDN = 2-input parallel; PUN = 2-input series.

  • XOR: Requires more transistors (~12T). Use transmission gates for efficiency.

2.3 Transmission Gate Logic

• Structure & Operation:

  DiagramCANVAS: CMOS Transmission Gate. Parallel combination of NMOS (gate controlled by C) and PMOS (gate controlled by C'). Source/Drain are bidirectional I/O.

  • C=1 → Both ON → low R_on, bidirectional pass.

  • C=0 → Both OFF → high impedance.

  • Advantage over single MOSFET: Passes both 0 and 1 well (NMOS degrades 1, PMOS degrades 0).

• Transient Analysis (Resistor Model):

  • Model TG as resistor R_on ≈ 1 / [μ_nC_ox(W/L)(V_DD-V_T)].

  • RC Delay: τ ≈ R_on · C_L.

  • Propagation Delay: t_pLH ≈ 0.69 R_on C_L (for pull-up via TG).

• EX-OR using TGs (4-TG design):

  DiagramCANVAS: 4-Transmission-Gate XOR. Inputs A, B. Output A⊕B. Two TGs in parallel: TG1 (A controls, passes B) and TG2 (B controls, passes A'). Inverters for A' and B'.

  • When A=0, TG1 ON → Out = B.

  • When A=1, TG2 ON → Out = B' = ¬B.

  • Hence Out = A⊕B.

[!TIP] Exam Trap: Realizing Z = A(D+C) + BE in NMOS PDN is NOT the same as CMOS PUN. Remember: NMOS PDN implements the true function (Z), not Z'. In CMOS, PUN implements Z'.

3.0 SEQUENTIAL CIRCUIT DESIGN (ASYNCHRONOUS & SYNCHRONOUS)

3.1 State Diagram & State Table (Synchronous)

• Sequence Detector for "101":

  • States: S₀ (no match), S₁ (last was '1'), S₂ (last was '10').

  • State Diagram:

    DiagramCANVAS: 3-state Moore machine for "101". S0 --1--> S1, S0 --0--> S0. S1 --0--> S2, S1 --1--> S1. S2 --1--> S0 (output=1), S2 --0--> S0. Output=1 only on S2->S0 transition.

  • Output: Moore (depends only on state) or Mealy (depends on state & input). For "101", Mealy can use 2 states.

3.2 Flow Table & Reduction (Asynchronous)

• Fundamental Mode: Inputs change only when circuit is stable; one input changes at a time.

• Primitive Flow Table: All states are distinct (no merging). Each row = stable state for a specific input combination.

• State Reduction (Merging Compatible States):

  1. Find Compatible Pairs: Two states can merge if for every input combination:

     • Their next states are compatible (or same).

     • Their outputs are identical.

  2. Find Maximal Compatible Set (MCS): Largest set of mutually compatible states.

  3. Merge Diagram: Find minimal set of MCS that covers all states.

  4. Minimum Row-Reduced Flow Table: Use MCS as merged states.

• Example (Q3, May 2023): "Output Z changes 0→1 only when x2:0→1 while x1=1; 1→0 only when x1:1→0 while x2=1."

  • Derive primitive flow table from specification.

  • Apply reduction → minimum row-reduced table.

3.3 Analysis of Asynchronous Circuits

• Toggle Flip-Flop Analysis (Q5, May 2023 - 14m):

  1. Given Flow Table: List all states (S1, S2, ...), inputs (x1, x2), next states, outputs.

  2. Identify Stable States: Entries where Next State = Current State (self-loop).

  3. Transition Rules: For unstable states (Next State ≠ Current), determine input change required.

  4. Critical Race: Two or more unstable states with same input → order of transition matters → hazard. Eliminate by adding extra states (state expansion).

  5. Hazards: Static (output glitch when should stay same) or Dynamic (output transitions through multiple states). Check using transition map or K-maps for each output.

[!TIP] Step-by-Step for Flow Table Reduction:

1. Write primitive table from spec.

2. Check all state pairs for compatibility (use table method).

3. Draw merging diagram (state as nodes, compatible pairs as edges).

4. Find all maximal cliques (complete subgraphs).

5. Choose minimal set of cliques covering all states.

6. Construct reduced flow table.

4.0 FABRICATION TECHNOLOGY & DEVICE STRUCTURES

4.1 NMOS Fabrication Technologies

• n-well, p-substrate Process (for CMOS):

  1. Start with p-type Si substrate.

  2. n-well formation: Implant/diffuse n-type dopant (As, P) through n-well mask.

  3. Active Area (Oxide Isolation): Grow field oxide (LOCOS) or use STI (Shallow Trench Isolation) to define active regions.

  4. Gate Oxide Growth: Grow thin SiO₂.

  5. Poly Deposition & Patterning: Deposit poly-Si, pattern to form gates.

  6. Source/Drain Implant: Light n- implant (LDD) → sidewall spacers → heavy n+ implant. (For p-sub, pMOS S/D formed in n-well).

  7. Contact Etch: Open contacts to S/D/gate.

  8. Metal Deposition & Patterning: Deposit Al/Cu, pattern interconnects.

  9. Passivation: Si₃N₄ layer.

• p-substrate vs. n-substrate: p-sub is cheaper, used for n-well CMOS. n-sub used for p-well process (older, less common).

4.2 MOS Resistor Implementation

• Linear/Triode Region Operation: V_DS < V_GS - V_T.

• Resistance Approximation:

$$R_{on} \approx \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)}$$

*   **Controlled by:** W/L ratio and overdrive (V<sub>GS</sub>-V<sub>T</sub>).

*   **Non-linearity:** R depends on V<sub>DS</sub> (due to channel length modulation) → not ideal resistor.

*   **Temperature Dependence:** μ<sub>n</sub> and V<sub>T</sub> vary with T.

• Advantages: Easy to fabricate, programmable via W/L.

• Limitations: Non-linear, large area for high R, temperature sensitive.

5.0 ADVANCED CIRCUITS & SPECIAL TOPICS

5.1 BiCMOS Circuits

• Structure: Combines CMOS (input stage, low static power) with Bipolar (output stage, high drive, low output impedance).

  DiagramCANVAS: BiCMOS Inverter. Input differential pair (BJT NPN) with active load (BJT PNP). Followed by CMOS inverter (PMOS/NMOS) driving output. Or simpler: CMOS input (PMOS/NMOS) driving a BJT emitter-follower output stage.

• Operation: CMOS provides high input impedance and low static power. Bipolar transistors provide high current drive (β) and fast switching (low C_be).

• Advantages over CMOS:

  • Higher Speed: Reduced RC delay (low R_out from BJT).

  • Higher Drive: Can drive large capacitive loads.

  • Low Static Power: Like CMOS.

• Disadvantages: More complex process, higher cost, increased leakage from BJTs.

5.2 Voltage Reference Circuits

• Goal: Generate stable V_ref independent of V_DD and temperature.

• High Sensitivity Design: Often uses sub-threshold MOSFETs or current mirrors.

  • Example: Sub-threshold MOSFET based reference:

    • Operate MOSFET in sub-threshold region: I_D ∝ e^{(V_GS-V_T)/nV_T}.

    • Use two transistors with different W/L or V_GS to generate a PTAT (proportional to absolute temperature) or CTAT (complementary to absolute temperature) voltage.

    • Combine to cancel temperature coefficient.

  • Bandgap Reference (BGR): Classic solution. Uses V_BE (CTAT) + V_T·ln(something) (PTAT) to get zero TC.

• Key Metrics: Temperature coefficient (ppm/°C), line regulation (ΔV_ref/ΔV_DD), PSRR.

5.3 Circuit Analysis & Problem Solving

• Estimating Voltage Ranges (Q13, May 2023): Given a multi-MOSFET circuit (e.g., stacked transistors), find min/max gate voltage to keep all transistors in desired region (ON/saturation).

  • Step 1: Identify all transistors and their connections.

  • Step 2: For each transistor, write condition for ON (V_GS > V_T) and Saturation (V_DS ≥ V_GS - V_T).

  • Step 3: Express V_GS, V_DS in terms of unknown gate voltage (e.g., V_G of M1).

  • Step 4: Solve inequalities simultaneously to find allowed range for V_G.

  • Example: For series stack M1-M2-M3 between V_DD and GND, with M1 gate = V_G:

    • M1 ON: V_G - V_DS1 > V_T1

    • M2 ON: V_DS1 - V_DS2 > V_T2

    • M3 ON: V_DS2 > V_T3

    • Also V_DS1 + V_DS2 + V_DS3 = V_DD.

    • Solve for V_G min/max.

6.0 HIGH-FREQUENCY EXAM TOPICS (RECURRING THEMES)

6.1 Logic Gate Realization (Q2)

• Step-by-Step Mapping:

  1. Given F(A,B,C,D,...), write complement F' using De Morgan.

  2. For NMOS PDN (Ratioed Logic): Implement F directly using series (AND) and parallel (OR) connections of NMOS.

  3. For CMOS: Implement F' in PUN (using PMOS: series=OR, parallel=AND), and F in PDN (using NMOS: series=AND, parallel=OR).

  4. Simplify using Boolean algebra before drawing.

6.2 Sequential Circuit Design & Analysis (Q3, Q4, Q5)

• Sequence Detector (Q4):

  • Choose Moore/Mealy.

  • Define states based on history of inputs needed to detect sequence.

  • Draw state diagram → state table → output equations.

  • State Assignment: Use binary encoding (e.g., S0=00, S1=01, S2=10).

• Flow Table Reduction (Q3):

  • Follow procedure in 3.2 exactly.

  • Key: Show compatibility table and merging diagram in answer.

• Asynchronous Toggle Analysis (Q5):

  • Given flow table, first reduce it if possible.

  • Identify stable states (self-loops).

  • For each unstable state, write transition condition (which input must change).

  • Check for races: two unstable states with same input → critical race.

  • Hazard analysis: For each output, see if it can glitch during state transitions.

6.3 Transmission Gate Applications (Q10, Q11)

• Transient Analysis (Q10):

  • Replace TG with R_on.

  • Charging: V_out(t) = V_DD(1 - e^-t/τ), τ = R_onC_L.

  • Discharging: V_out(t) = V_DD e^-t/τ.

  • Compute t_pLH, t_pHL as time to reach V_DD/2.

• EX-OR Design (Q11):

  • Use 4-TG structure (as in 2.3).

  • Explain operation for all input combinations (A=0/B=0, A=0/B=1, etc.).

6.4 MOSFET Parameter Dependency (Q1, Q13)

• V_T Dependencies (Q1): List all from 1.1 table. Explain physical reason for each.

• Inference on Channel Length (Q13):

  • From DC characteristics (V_TC shift, slope change, reduced gain), infer short-channel effects (DIBL, λ).

  • Estimate Voltage Range: Use ON/saturation conditions as in 5.3.

Final Exam Strategy:

1. For 7m questions: Provide definition, formula (boxed), diagram (describe), and 2-3 key points.

2. For 14m questions (like Q5): Detailed step-by-step analysis. Show all tables, diagrams, and reasoning.

3. Always connect theory to the specific question (e.g., "For the given Boolean function Z=...", "For the sequence detector...").

4. Draw neat schematics with clear labels (V_DD, GND, inputs, outputs).

5. Use standard notation: β for gain, λ for CLM, SS for sub-threshold slope.

Good Luck!