CMOS DESIGN (EC-603 (B)) Unit 3 Notes - RGPV

UNIT 3: CMOS DESIGN - Short Notes

1.0 MOSFET FUNDAMENTALS & PARAMETERS

1.1 Threshold Voltage (Vₜ)

Definition: Minimum gate-to-source voltage ($$\displaystyle V_{GS} $$) required to create a conductive channel between source and drain, turning the MOSFET ON.
Physical Significance: Determines the switching point and power consumption of a CMOS gate.
Long-Channel Expression:

$$V_{T} = V_{FB} + 2\phi_{F} + \frac{\sqrt{2q\epsilon_{si}N_{A}(2\phi_{F})}}{C_{ox}}$$

Where:

*   $$\displaystyle V_{FB} $$ = Flat-band voltage

*   $$\displaystyle \phi_{F} $$ = Fermi potential ($$\displaystyle \phi_{F} = (kT/q) \ln(N_{A}/n_{i}) $$)

*   $$\displaystyle N_{A} $$ = Substrate doping concentration

*   $$\displaystyle C_{ox} = \epsilon_{ox}/t_{ox} $$ = Oxide capacitance per unit area

Dependency on Parameters:
- Oxide Thickness ($$\displaystyle t_{ox} $$): $$\displaystyle V_T \propto 1/t_{ox} $$ (thinner oxide → lower $$\displaystyle V_T $$).
- Substrate Doping ($$\displaystyle N_A $$): $$\displaystyle V_T \propto \sqrt{N_A} $$ (heavier doping → higher $$\displaystyle V_T $$).
- Surface Potential ($$\displaystyle \phi_s $$): $$\displaystyle V_T $$ increases with $$\displaystyle \phi_s $$ (typically $$\displaystyle \phi_s \approx 2\phi_F $$).
- Work Function Difference: Between gate material and substrate.
- Flat-Band Voltage ($$\displaystyle V_{FB} $$): Depends on gate material and oxide charges.
Body Effect (Substrate Bias Effect): Applying a reverse-bias voltage to the source-body junction ($$\displaystyle V_{SB} > 0 $$) increases the depletion width, raising $$\displaystyle V_T $$.

$$V_T = V_{T0} + \gamma \left( \sqrt{|\phi_{F} + V_{SB}|} - \sqrt{|\phi_{F}|} \right)$$

Where $$\displaystyle \gamma = \sqrt{2q\epsilon_{si}N_A}/C_{ox} $$ (body effect coefficient).

[!TIP] Exam Focus: Be prepared to derive/explain each term in the $$\displaystyle V_T $$ equation. The body effect formula is frequently asked.

1.2 MOS Transistor Models

1.2.1 Strong Inversion Model (Triode & Saturation)
- Triode Region (Linear): $$\displaystyle V_{GS} > V_T $$, $$\displaystyle V_{DS} < V_{GS} - V_T $$

$$I_{DS} = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_T)V_{DS} - \frac{V_{DS}^2}{2} \right] (1 + \lambda V_{DS})$$

*   **Saturation Region:** $$\displaystyle V_{GS} > V_T $$, $$\displaystyle V_{DS} \geq V_{GS} - V_T $$

$$I_{DS} = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2 (1 + \lambda V_{DS})$$

    *   $\lambda$ = Channel Length Modulation (CLM) parameter.

1.2.2 Sub-threshold MOS Model (Weak Inversion)
- Operation: $$\displaystyle V_{GS} < V_T $$. Current flows due to diffusion of minority carriers, not drift.
- Exponential I-V:

$$I_{DS} \approx I_0 e^{(V_{GS} - V_T)/nV_T} \left(1 - e^{-V_{DS}/V_T}\right)$$

    Where:

    *   $$\displaystyle I_0 $$ = Process-dependent current.

    *   $n$ = Sub-threshold slope factor ($$\displaystyle n = 1 + C_{dep}/C_{ox} $$).

*   **Key Point:** $$\displaystyle I_{DS} $$ varies exponentially with $$\displaystyle V_{GS} $$, enabling ultra-low-power circuits but with poor noise margins.

1.2.3 Small-Signal Model
- Used for AC/transient analysis.
- Key Parameters:
  - $$\displaystyle g_m = \frac{\partial I_{DS}}{\partial V_{GS}} $$ (Transconductance)
  - $$\displaystyle g_{ds} = \frac{\partial I_{DS}}{\partial V_{DS}} = \lambda I_{DS} $$ (Output conductance)
  - $$\displaystyle r_o = 1/g_{ds} $$ (Output resistance)
- Model: Replace MOSFET with $$\displaystyle g_m V_{gs} $$ current source between drain and source, in parallel with $$\displaystyle r_o $$.

2.0 COMBINATIONAL LOGIC DESIGN USING CMOS/NMOS

2.1 NMOS Logic Gates & Networks

Concept: Use NMOS pull-down network (PDN) to ground. Load is a pull-up resistor (or active load).
Design Rule: PDN must conduct when output = 0. Implement Boolean function in complementary form (use De Morgan's theorem).
Example: Realize $$\displaystyle Z = A(D + C) + BE $$
1. Complement: $$\displaystyle \overline{Z} = \overline{A(D+C)+BE} = (\overline{A} + \overline{D}\cdot\overline{C}) \cdot (\overline{B} + \overline{E}) $$
2. PDN (conducts to pull Z low): Series-parallel network for $\overline{Z}$.
3. PDN Structure: $(\overline{A}$ in series with parallel combination of $\overline{D}$ and $\overline{C})$ in series with (parallel combination of $\overline{B}$ and $\overline{E})$.
Logic Effort & Sizing: To achieve equal rise/fall delays, size NMOS transistors in PDN. For a logic gate with effective input capacitance $$\displaystyle C_{in} $$, size factor $f$ is used.

2.2 CMOS Inverter & Gates

Static CMOS Inverter:
- Structure: PMOS (pull-up) + NMOS (pull-down) in complementary configuration.
- Operation:
  - $$\displaystyle V_{in} < V_T $$: PMOS ON, NMOS OFF → $$\displaystyle V_{out} = V_{DD} $$
  - $$\displaystyle V_{in} > V_{DD} - |V_{TP}| $$: NMOS ON, PMOS OFF → $$\displaystyle V_{out} = 0 $$
  - $$\displaystyle V_T < V_{in} < V_{DD}-|V_{TP}| $$: Both partially ON → $$\displaystyle V_{out} $$ determined by voltage division.
DC Transfer Characteristics:
- S-shaped curve due to different mobilities ($$\displaystyle \mu_n > \mu_p $$).
- Switching Point ($$\displaystyle V_M $$): $$\displaystyle V_{in} = V_{out} $$ (typically $$\displaystyle V_{DD}/2 $$ for symmetric sizing).
- Noise Margins:
  - $$\displaystyle NM_L = V_{IL} - V_{OL} $$ (Low noise margin)
  - $$\displaystyle NM_H = V_{OH} - V_{IH} $$ (High noise margin)
  - Where $$\displaystyle V_{IL}, V_{IH} $$ are points where $$\displaystyle dV_{out}/dV_{in} = -1 $$.
Inference on Channel Length Modulation: From DC curve, as $$\displaystyle V_{DS} $$ increases in saturation, slight upward slope in output indicates finite $$\displaystyle r_o $$ due to CLM ($$\displaystyle \lambda > 0 $$). Larger $\lambda$ → steeper slope → lower gain.
Standard Gates:
- NAND: Series NMOS PDN, parallel PMOS PUN.
- NOR: Parallel NMOS PDN, series PMOS PUN.
- XOR/XNOR: More complex; typically uses 6-transistor (6T) or 8-transistor (8T) designs.

2.3 Transmission Gate Logic (TG Logic)

Structure: Parallel combination of NMOS and PMOS, controlled by complementary signals ($C$ and $\overline{C}$).
Operation: Acts as a bidirectional switch with low on-resistance ($$\displaystyle R_{on} $$) and no threshold voltage drop issue (unlike single pass transistor).
Transient Analysis (Resistor Model):
- Replace TG with resistor $$\displaystyle R_{on} $$.
- RC Delay Model: $$\displaystyle t_p \approx 0.69 \cdot R_{on} \cdot C_L $$
- $$\displaystyle R_{on} $$ depends on $$\displaystyle V_{GS} $$ and transistor sizing.
Design Example: Ex-OR using TG
- Implementation: Use TGs to steer inputs to output based on control.
- Typical 4-TG XOR:
  - TG1: Connects B to output when A=0.
  - TG2: Connects $\overline{B}$ to output when A=1.
  - Inverters generate $\overline{A}$ and $\overline{B}$.

2.4 Pass Transistor Logic

Structure: Only NMOS (or only PMOS) transistors used as switches.
Issue: Voltage Drop Problem. NMOS pass transistor cannot pass a full $$\displaystyle V_{DD} $$ (max $$\displaystyle V_{DD} - V_T $$). PMOS pass transistor has slow operation (low mobility).
Comparison with TG:

| Feature | Pass Transistor (NMOS) | Transmission Gate | | :--- | :--- | :--- | | Area | Smaller (1 transistor) | Larger (2 transistors) | | Voltage Drop | Yes ($$\displaystyle V_{DD}-V_T $$) | No (full swing) | | Speed | Fast (NMOS) | Moderate | | Use Case | Non-critical paths, low-power | General-purpose, full-swing |

3.0 SEQUENTIAL LOGIC & ASYNCHRONOUS CIRCUITS

3.1 Synchronous Sequential Circuits

State Diagram & Table: Represent circuit behavior with states (S0, S1,...) and transitions based on inputs (X).
Example: Sequence Detector for "101"
- States:
  - S0: No match / initial.
  - S1: Last bit was '1'.
  - S2: Last two bits were '10'.
- Output Z=1 only in state S2 when input X=1 (detects "101").
- State Table:
  
  | Present State | Input X | Next State | Output Z | | :--- | :--- | :--- | :--- | | S0 | 0 | S0 | 0 | | S0 | 1 | S1 | 0 | | S1 | 0 | S2 | 0 | | S1 | 1 | S1 | 0 | | S2 | 0 | S0 | 0 | | S2 | 1 | S1 | 1 |
State Reduction:
- Row Reduction (Implication Table): Merge equivalent states (same future behavior).
- Goal: Minimize number of flip-flops and logic gates.

3.2 Asynchronous Sequential Circuits

Fundamental Mode Operation: Inputs change only when circuit is stable (no simultaneous input changes).
Flow Table Analysis:
- Primitive Flow Table: Each state is unique (all rows/columns distinct).
- Row Reduction: Merge compatible states (same output, next states compatible).
- Column Reduction: Merge equivalent columns.
Example: Asynchronous Toggle Circuit
- Function: Output toggles on each input pulse.
- Flow Table: Typically 2 states (Q=0, Q=1). Input X causes transition between states. Output is state variable.
- Analysis: Identify stable states (X=0), transitions on X=1.
Race Conditions & Hazards:
- Static Hazard: Unwanted transient when input changes but output should remain same.
- Dynamic Hazard: Output changes more than once before settling.
- Cause: Delays in different signal paths.
State Assignment: Use binary or Gray code to minimize races. Adjacent states (differ by 1 bit) reduce risk.

3.3 Basic Memory Elements

Latch: Level-sensitive (transparent when clock=1).
- SR Latch: Cross-coupled NOR/NAND gates. Invalid when S=R=1.
- D Latch: Adds inverter to avoid invalid state. $$\displaystyle Q = D $$ when clock=1.
Flip-Flop: Edge-triggered (samples on clock edge).
- D Flip-Flop: Master-slave or edge-triggered design. $$\displaystyle Q(t+\Delta) = D(t) $$ at clock edge.
- JK & T Flip-Flops: Derived from D FF with feedback.

4.0 CMOS FABRICATION TECHNOLOGY & DEVICE STRUCTURES

4.1 NMOS Fabrication Process (p-type substrate)

Substrate Preparation: p-type Si wafer.
Field Oxide (FOX) Growth: Thick $$\displaystyle SiO_2 $$ for isolation (LOCOS).
Active Area Mask & Etch: Define regions where transistors will be built.
Gate Oxide Growth: Thin $$\displaystyle SiO_2 $$ (gate dielectric).
Poly-silicon Deposition & Gate Mask: Define gate electrode.
Source/Drain Implant: n+ doping (using gate as mask → self-aligned).
Threshold Adjustment Implant: Adjust $$\displaystyle V_T $$ if needed.
Interlayer Oxide Deposition & Contact Etch: Open contacts to gate, source, drain.
Metal Deposition & Mask: Define interconnects (Al or Cu).
Passivation: Protective $$\displaystyle Si_3N_4 $$ layer.

Cross-Section (NMOS Inverter): Shows p-substrate, n+ source/drain, poly gate, metal contacts.

4.2 Passive Elements in CMOS

MOS Transistor as Resistor:
- Linear Region: $$\displaystyle V_{GS} > V_T $$, $$\displaystyle V_{DS} $$ small.

$$R_{on} \approx \frac{1}{\mu_n C_{ox} (W/L) (V_{GS} - V_T)}$$

*   **Saturation Region:** $$\displaystyle V_{GS} > V_T $$, $$\displaystyle V_{DS} \geq V_{GS} - V_T $$. $$\displaystyle R_{on} $$ increases slightly with $$\displaystyle V_{DS} $$.

*   **Layout:** Use minimum $W$, long $L$ for high resistance. **Drawback:** Large area, temperature-dependent, nonlinear.

*   **Typical Use:** Load in simple NMOS logic, biasing networks.

4.3 BiCMOS Technology

BiCMOS Inverter Circuit:
- Pull-up: PNP BJT (emitter to $$\displaystyle V_{DD} $$, collector to output).
- Pull-down: NMOS (drain to output, source to GND).
- Operation:
  - $$\displaystyle V_{in}=0 $$: NMOS OFF, base of PNP at $$\displaystyle V_{DD} $$ → PNP ON → $$\displaystyle V_{out}=V_{DD} $$.
  - $$\displaystyle V_{in}=V_{DD} $$: NMOS ON, PNP base at 0 → PNP OFF → $$\displaystyle V_{out}=0 $$.
Advantages over CMOS:
- High Speed: BJT has higher $$\displaystyle g_m $$ and lower $$\displaystyle r_o $$ → faster switching.
- High Drive: BJT provides large current → drives large capacitive loads.
- Low Static Power: Still complementary → no direct path $$\displaystyle V_{DD} $$ to GND.
Trade-offs:
- Complexity & Cost: More masks, process steps (bipolar and CMOS integration).
- Power: Higher dynamic power due to BJT charge storage.
- Area: Larger cell size.

5.0 ANALOG/DIGITAL INTERFACE & SPECIAL CIRCUITS

5.1 Voltage Reference Circuits

Bandgap Reference Principle: Combine voltages with opposite temperature coefficients (TC) to achieve near-zero net TC.
- $$\displaystyle V_{BE} $$ of BJT: Negative TC (~ -2 mV/°C).
- $$\displaystyle \Delta V_{BE} $$ (between two BJTs with different currents): Positive TC (~ +0.1 mV/°C).
Circuit Diagram & Explanation:
- Core: Op-amp (or CMOS amplifier) with feedback.
- Resistive Divider: Scales $$\displaystyle \Delta V_{BE} $$ to match magnitude of $$\displaystyle V_{BE} $$ TC.
- Summation: $$\displaystyle V_{ref} = V_{BE} + K \cdot \Delta V_{BE} $$.
- High Sensitivity: Achieved by careful matching of BJTs and precise resistor ratios. $$\displaystyle V_{ref} \approx 1.25 $$ V (for silicon).
- Role of Temperature Compensation: Adjust K so that $$\displaystyle dV_{ref}/dT \approx 0 $$ over desired range.

5.2 DC & Transient Analysis of CMOS Circuits

Inverter DC Characteristics:
- Plot: $$\displaystyle V_{out} $$ vs $$\displaystyle V_{in} $$ (log scale often used).
- Key Points:
  - $$\displaystyle V_{OH} \approx V_{DD} $$, $$\displaystyle V_{OL} \approx 0 $$.
  - $$\displaystyle V_{M} $$: Switching threshold (where $$\displaystyle V_{in}=V_{out} $$). For symmetric inverter ($$\displaystyle \beta_n = \beta_p $$), $$\displaystyle V_M \approx V_{DD}/2 $$.
  - Noise Margins: $$\displaystyle NM_H = V_{OH} - V_{IH} $$, $$\displaystyle NM_L = V_{IL} - V_{OL} $$.
  - Gain: $$\displaystyle |dV_{out}/dV_{in}| $$ max near $$\displaystyle V_M $$ (should be > 1 for noise immunity).
Inference on MOSFET Channel Length:
- From DC curve, slope in saturation region (especially near $$\displaystyle V_M $$) indicates CLM.
- Shorter Channel: Higher $\lambda$ (steeper slope) → lower gain, more CLM effect.
- Longer Channel: Lower $\lambda$ (flatter saturation) → higher gain, ideal current source behavior.
- Design Implication: For high gain (e.g., analog), use longer channels. For high speed (digital), shorter channels favored despite lower gain.
Transient Analysis (RC Delay Model):
- Propagation Delays:

$$t_{pLH} \approx 0.69 \cdot R_{p} \cdot C_L, \quad t_{pHL} \approx 0.69 \cdot R_{n} \cdot C_L$$

    Where $$\displaystyle R_p $$, $$\displaystyle R_n $$ are effective resistances of PMOS/NMOS in saturation.

*   **Average Propagation Delay:** $$\displaystyle t_p = (t_{pLH} + t_{pHL})/2 $$.

*   **Effect of Load Capacitance ($$\displaystyle C_L $$):** $$\displaystyle t_p \propto C_L $$. $$\displaystyle C_L $$ includes:

    *   Gate capacitance of next stage ($$\displaystyle C_{in} $$).

    *   Wire capacitance.

    *   Drain diffusion capacitance.

*   **Sizing for Speed:** Increase $W/L$ to reduce $$\displaystyle R_{on} $$ → lower delay. But increases input capacitance → trade-off in multi-stage gates.

[!TIP] Exam Focus: Be ready to sketch DC transfer curve, label $$\displaystyle V_M $$, $$\displaystyle V_{IH} $$, $$\displaystyle V_{IL} $$, and explain how channel length affects the saturation region slope. For transient analysis, remember $$\displaystyle t_p \propto R_{on} C_L $$.

Account

CMOS DESIGN (EC-603 (B)) - Unit 3 Short Notes