CMOS DESIGN (EC-603 (B)) - Unit 2 Short Notes

UNIT 2: CMOS Circuit Design and Analysis

I. Fabrication Technology

NMOS Fabrication Process

The NMOS fabrication process involves sequential steps to define active regions, gates, and interconnects on a silicon substrate.

Step-by-step process flow:

1. Substrate Preparation: Start with a p-type silicon wafer.

2. Field Oxidation: Grow a thick SiO₂ layer (field oxide) to isolate transistors.

3. Photolithography (Active Area): Define active regions (where transistors will be formed) by etching field oxide.

4. Gate Oxidation: Grow a thin, high-quality SiO₂ layer (gate oxide).

5. Polysilicon Deposition & Patterning: Deposit poly-Si, then pattern it to form the gate electrode.

6. Source/Drain Doping: Use the polysilicon gate as a mask for ion implantation (n⁺ doping) to create source and drain regions.

7. Contact Etching: Open contact windows to expose source, drain, and gate regions.

8. Metallization: Deposit and pattern aluminum (or copper) for interconnections.

9. Passivation: Deposit a protective layer (e.g., Si₃N₄) over the circuit.

Key Masks and Layer Definitions:

[!TIP] Exam Focus: Be prepared to sketch the cross-sectional view after key steps (e.g., after polysilicon patterning, after metallization). Understand the role of each mask.

Comparison with CMOS Fabrication (Brief):

• NMOS: Only n-channel transistors. Requires n⁺ doping for source/drain. Simpler process.

• CMOS: Both n-MOS and p-MOS transistors. Requires p-well (or n-well) creation for p-MOS devices. More masks (well, n⁺, p⁺ implants) but results in near-zero static power.

II. MOSFET Device Physics and Modeling

Threshold Voltage (Vₜ)

Definition: The minimum gate-to-source voltage ($$\displaystyle V_{GS} $$) required to create a conductive channel between source and drain, turning the MOSFET ON.

Mathematical Expression (Long-channel, nMOS):

$$ V_{T} = V_{FB} + 2\phi_F + \frac{\sqrt{2q\varepsilon_{si} N_a 2\phi_F}}{C_{ox}} $$

Where:

• $$\displaystyle V_{FB} $$: Flat-band voltage

• $$\displaystyle \phi_F $$: Fermi potential ($$\displaystyle \phi_F = (kT/q) \ln(N_a/n_i) $$)

• $$\displaystyle N_a $$: Substrate doping concentration

• $$\displaystyle C_{ox} $$: Oxide capacitance per unit area ($$\displaystyle \varepsilon_{ox}/t_{ox} $$)

Dependencies of Vₜ:

1. Body Effect (Substrate Bias): $$\displaystyle V_{T} = V_{T0} + \gamma (\sqrt{|\phi_F + V_{SB}|} - \sqrt{|\phi_F|}) $$, where $$\displaystyle \gamma = \sqrt{2q\varepsilon_{si} N_a}/C_{ox} $$. Vₜ increases with V_SB.

2. Channel Doping (Nₐ): Higher $$\displaystyle N_a $$ → higher $$\displaystyle V_T $$ (from $$\displaystyle \phi_F $$ and $\gamma$ terms).

3. Oxide Thickness (tₒₓ): Thinner $$\displaystyle t_{ox} $$ → higher $$\displaystyle C_{ox} $$ → lower $$\displaystyle V_T $$.

4. Temperature: $$\displaystyle V_T $$ typically decreases with temperature (~ -2 mV/°C) due to intrinsic carrier concentration ($$\displaystyle n_i $$) increase.

5. Supply Voltage & Process Variations: Manufacturing variations cause $$\displaystyle V_T $$ spread, impacting circuit performance and yield.

[!TIP] Common Pitfall: Forgetting the body effect term when source is not at substrate potential. In CMOS, p-MOS body is at VDD, n-MOS body at GND, so body effect is often zero for minimum-sized transistors.

Sub-threshold MOS Model

Operation: When $$\displaystyle V_{GS} < V_T $$, the channel is not strongly inverted. Current flows due to weak inversion (diffusion-dominated), similar to a bipolar transistor.

Sub-threshold Current (I_sub):

$$ I_{DS} \approx I_0 \cdot e^{\frac{V_{GS} - V_T}{nV_T}} \cdot \left(1 - e^{-\frac{V_{DS}}{V_T}}\right) $$

Where:

• $$\displaystyle I_0 $$: Process-dependent current scale factor ($\propto (W/L)$)

• $n$: Sub-threshold slope factor ($$\displaystyle n = 1 + C_{dep}/C_{ox} $$), typically 1.1–1.5.

• $$\displaystyle V_T $$: Thermal voltage ($kT/q \approx 26$ mV at 300K).

Sub-threshold Slope (S):

$$ S = \frac{d(\log_{10} I_{DS})}{dV_{GS}} = \frac{ln(10) \cdot nV_T}{1} \approx 60 \text{ mV/dec} \cdot n $$

• Ideal limit: 60 mV/dec at room temperature (n=1).

• Physical limit: Determined by $$\displaystyle C_{dep}/C_{ox} $$. Thinner $$\displaystyle t_{ox} $$ or lower $$\displaystyle N_a $$ improves slope.

Applications in Low-Power Design:

• Ultra-low-voltage circuits (< 0.5V).

• High $$\displaystyle V_T $$ transistors for reducing leakage in idle modes.

• Sub-threshold SRAM and ultra-low-power sensors.

[!TIP] Key Insight: Sub-threshold operation trades speed for power. The exponential current makes circuits sensitive to $$\displaystyle V_T $$ variations and temperature.

Channel Length Effects

1. Channel Length Modulation (CLM):

• In saturation, the depletion region extends towards source, reducing effective channel length ($$\displaystyle L_{eff} $$).

• Effect: Output conductance ($$\displaystyle g_{ds} $$) increases, $$\displaystyle I_{DS} $$ increases slightly with $$\displaystyle V_{DS} $$.

• Modeled by: $$\displaystyle I_{DS(sat)} = I_{D0}(1 + \lambda V_{DS}) $$, where $\lambda \propto 1/L$.

2. Short-Channel Effects (SCE):

• Drain-Induced Barrier Lowering (DIBL): High $$\displaystyle V_{DS} $$ lowers the potential barrier at the source end, reducing $$\displaystyle V_T $$ and increasing $$\displaystyle I_{DS} $$.

• Punch-through: For very short channels, source and drain depletion regions merge, causing a large current even at $$\displaystyle V_{GS}=0 $$.

• Velocity Saturation: At high lateral electric fields ($$\displaystyle E > E_{crit} $$), carrier velocity saturates ($$\displaystyle v_{sat} $$), causing $$\displaystyle I_{DS} $$ to become linear in $$\displaystyle V_{GS} $$ rather than quadratic.

Inference from Inverter DC Characteristics:

• Long Channel: Sharp switching transition, high gain in saturation region.

• Short Channel: Softer transition, reduced gain due to CLM/DIBL, increased leakage.

• Optimization: Channel length must balance speed (shorter is faster) vs. control (longer reduces SCE). Modern nodes use channel engineering (halo implants, retrograde wells) to mitigate SCE.

III. Digital CMOS/NMOS Logic Design

A. Combinational Logic Design (NMOS)

Pull-Down Network (PDN) Design:

• Realize Boolean function $F$ as a network of series (AND) and parallel (OR) NMOS transistors.

• Dual of PDN is Pull-Up Network (PUN) in static CMOS.

Load Devices:

Example: Realize $$\displaystyle Z = A(D + C) + BE $$

1. SOP form: $$\displaystyle Z = AD + AC + BE $$

2. PDN: Parallel combination of (A in series with D), (A in series with C), and (B in series with E).

3. Schematic:

   DiagramCANVAS: Draw NMOS gate with 3 parallel branches: top branch: A-D series, middle: A-C series, bottom: B-E series. All sources to GND. Output Z at common drain node. Load is depletion NMOS with gate at VDD, drain to Z, source to VDD.

Design Considerations:

• Transistor Sizing: Series transistors need larger W to match resistance of single parallel device (e.g., 2-series → 2xW).

• Noise Margins: NMOS logic has poor noise margins compared to static CMOS due to resistive load.

• Power Dissipation: Static power exists (current path from VDD to GND when output is LOW).

[!TIP] Exam Alert: You may be asked to realize a given Boolean function. Always convert to SOP, then map series=AND, parallel=OR.

B. Sequential Logic Design

Fundamental Mode Sequential Circuits:

• Flow Table: Tabular representation of state transitions based on input changes.

• Construction: Rows = states, columns = input combinations. Entries = next state and output.

• Row Reduction: Merge compatible rows (same next state/output for all inputs).

• State Assignment: Assign binary codes to reduced states (binary, one-hot, Gray).

Example Problem (from May 2023):

"Output Z changes 0→1 only when x₂: 0→1 while x₁=1. Z changes 1→0 only when x₁: 1→0 while x₂=1."

Minimum Row-Reduced Flow Table:

• States: a=0, b=1. Output depends on transition, not just state (fundamental mode).

State Diagrams & Sequence Detectors:

• Sequence Detector (101): Overlapping detection allowed.

• State Diagram:

  DiagramCANVAS: Draw 3 states: S0 (reset), S1 (got '1'), S2 (got '10'). Transitions: S0 --1--> S1, S0 --0--> S0; S1 --0--> S2, S1 --1--> S1; S2 --1--> S1 (output 1), S2 --0--> S0.

• State Minimization: Use implication table or row matching.

• Encoding: Binary (2 bits for 3 states) or One-hot (3 flip-flops).

Asynchronous Sequential Circuits:

• Analysis: Use flow table to derive state equations and identify stability.

• Hazards: Static (output glitch when input changes but output should remain same) and Dynamic (multiple transitions).

• Races: Critical race occurs when two state variables change simultaneously and order matters. Solution: Add extra states (common state) to ensure single-variable changes.

IV. Advanced CMOS Circuit Techniques

A. Transmission Gates

Structure & Operation:

• Parallel combination of n-MOS (gate driven by $\overline{C}$) and p-MOS (gate driven by C).

• Acts as a bidirectional switch controlled by C.

• ON: Low resistance ($$\displaystyle R_{on} \approx $$ few hundred $\Omega$).

• OFF: High resistance (leakage from body diode of n-MOS is main issue).

Transient Analysis (Resistor Model):

• Replace TG with equivalent resistor $$\displaystyle R_{eq} = R_{on,n} \parallel R_{on,p} $$.

• RC delay: $$\displaystyle t_{pd} \approx 0.69 \cdot R_{eq} \cdot C_L $$.

• Advantage over single MOSFET: Symmetric rise/fall times, reduced charge injection.

[!TIP] Key Point: For a single MOSFET switch, body diode conducts for negative $$\displaystyle V_{in} $$ → not bidirectional. TG solves this.

B. Transmission Gate Logic Design

Design Example: 2-input XOR

$$ Z = A\overline{B} + \overline{A}B $$

Implementation:

1. Use TG to implement product terms.

2. Schematic:

   DiagramCANVAS: Draw two parallel branches from output to GND. Top branch: A controls TG (source to VDD, drain to node X), B controls TG (source to X, drain to GND). Bottom branch: A' (inverter) controls TG (source to VDD, drain to node Y), B controls TG (source to Y, drain to GND). Then X and Y connected via inverter to output Z.

• Comparison with Static CMOS:

  | Feature | Static CMOS | TG Logic | | :--- | :--- | :--- | | Area | Larger (12 transistors for XOR) | Smaller (8 transistors) | | Speed | Faster (full swing, no series pass) | Slower (voltage drop across pass TG) | | Power | Low static power | Low static power, but possible contention |

C. BiCMOS Circuits

BiCMOS Inverter:

• Structure: Input drives n-MOS (M1) and p-MOS (M2). M1 source to GND, drain to base of NPN (Q1). M2 drain to VDD, source to base of PNP (Q2). Emitters of Q1 and Q2 tied to output.

  DiagramCANVAS: Show VDD -> p-MOS M2 -> base of PNP Q2 -> emitter (output) -> base of NPN Q1 -> n-MOS M1 -> GND. Input to gates of M1 and M2.

• Operation:

  • Input LOW: M1 OFF, M2 ON → Q2 base pulled to VDD → Q2 ON → Output pulled to VDD.

  • Input HIGH: M1 ON, M2 OFF → Q1 base pulled to GND → Q1 ON → Output pulled to GND.

• Advantages:

  • High Speed: BJT provides high current drive → fast rise/fall.

  • Low Static Power: No DC path VDD-GND.

  • Good Noise Immunity: High gain from BJT stage.

• Applications: High-performance drivers, bus interfaces, analog buffers.

D. MOS Resistor Implementation

Using MOSFET in Linear Region:

• Operate with $$\displaystyle V_{GS} > V_T $$ and $$\displaystyle V_{DS} < V_{GS} - V_T $$.

• Equivalent Resistance:

$$ R_{eq} = \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T - \frac{V_{DS}}{2})} $$

For small $$\displaystyle V_{DS} $$: $$\displaystyle R_{eq} \approx \frac{1}{\mu_n C_{ox} (W/L) (V_{GS} - V_T)} $$.

• Control: $$\displaystyle R_{eq} $$ is voltage-controlled via $$\displaystyle V_{GS} $$. Higher $$\displaystyle V_{GS} $$ → lower resistance.

• Applications:

  • Active loads in amplifiers.

  • Biasing networks (replaces large polysilicon resistors).

  • Tunable delay elements.

E. Voltage Reference Circuits

Bandgap Reference (BGR) Principle:

• Generates temperature-independent voltage by summing:

  • CTAT (Complementary to Absolute Temperature): $$\displaystyle V_{BE} $$ of BJT (decreases with T).

  • PTAT (Proportional to Absolute Temperature): $$\displaystyle \Delta V_{BE} $$ between two BJTs at different currents (increases with T).

• Key Circuit:

  DiagramCANVAS: Show two BJTs (Q1, Q2) with emitter currents I and nI. Their V_BE difference (ΔV_BE) across resistor R1 generates PTAT voltage. This voltage added to V_BE of Q1 (CTAT) via summing node. Amplifier forces equal currents.

• Output: $$\displaystyle V_{ref} = V_{BE1} + (kT/q) \ln(n) \cdot (R2/R1) $$.

• Performance Metrics:

  • Temperature Coefficient (TC): $$\displaystyle \frac{\Delta V_{ref}}{\Delta T} $$ (aim for < 5 ppm/°C).

  • Line Regulation: $$\displaystyle \frac{\Delta V_{ref}}{\Delta V_{DD}} $$ (should be low).

F. CMOS Inverter Analysis

DC Transfer Characteristics (VTC):

1. Region 1 (V_in LOW): M1 OFF, M2 linear → Output ≈ VDD.

2. Region 2 (Transition): Both transistors in saturation (ideal) or one in saturation, one in linear.

3. Region 3 (V_in HIGH): M1 linear, M2 OFF → Output ≈ 0V.

4. Switching Threshold (V_M): $$\displaystyle V_{in} = V_{out} $$. For symmetric inverter ($$\displaystyle \beta_n = \beta_p $$), $$\displaystyle V_M \approx V_{DD}/2 $$.

Noise Margins:

$$ NM_L = V_{IL} - V_{OL} \approx V_M - V_{OL} $$

$$ NM_H = V_{OH} - V_{IH} \approx V_{OH} - V_M $$

Where $$\displaystyle V_{IL}, V_{IH} $$ are max input LOW and min input HIGH for valid logic levels.

Effect of Device Parameters:

• W/L Ratio: $$\displaystyle \beta_n/\beta_p $$ ratio sets $$\displaystyle V_M $$. $$\displaystyle \beta_n > \beta_p $$ → $$\displaystyle V_M < V_{DD}/2 $$.

• Channel Length: Shorter L → higher current → steeper VTC but more SCE.

• Load Capacitance (C_L): Affects transient response, not DC VTC.

Condition for Both Transistors in Desired Region:

For maximum noise margin, during transition both should be in saturation:

$$ V_{DS,sat} \leq V_{GS} - V_T $$

For M1 (nMOS): $$\displaystyle V_{out} \leq V_{in} - V_{Tn} $$

For M2 (pMOS): $$\displaystyle V_{DD} - V_{out} \leq V_{DD} - V_{in} - |V_{Tp}| \Rightarrow V_{out} \geq V_{in} + V_{Tp} $$

Thus, valid switching region: $$\displaystyle V_{in} + V_{Tp} \leq V_{out} \leq V_{in} - V_{Tn} $$.

[!TIP] Inference: To ensure both transistors are ON during switching, $$\displaystyle V_{Tn} $$ and $$\displaystyle |V_{Tp}| $$ must be small and $$\displaystyle V_M $$ must be well-centered. This guides sizing and threshold voltage selection.