CMOS DESIGN (EC-603 (B)) Unit 1 Notes - RGPV

MOSFET FUNDAMENTALS & CHARACTERISTICS

Threshold Voltage (Vₜ)

Definition: Minimum gate-to-source voltage required to create a conductive channel between source and drain.
Physical Significance: Determines switching point and power consumption.
Expression (for nMOS on p-substrate):

$$V_T = V_{FB} + 2\phi_F + \frac{\sqrt{2q\epsilon_{si} N_a 2\phi_F}}{C_{ox}}$$

where:

$$\displaystyle V_{FB} $$ = flat-band voltage
$$\displaystyle 2\phi_F $$ = surface potential at strong inversion
$$\displaystyle N_a $$ = substrate doping concentration
$$\displaystyle C_{ox} = \frac{\epsilon_{ox}}{t_{ox}} $$ = oxide capacitance per unit area
Dependency on Parameters:

| Parameter | Effect on Vₜ | |-----------|--------------| | Oxide thickness ($$\displaystyle t_{ox} $$) | ↑ $$\displaystyle t_{ox} $$ → ↓ $$\displaystyle C_{ox} $$ → ↑ Vₜ | | Substrate doping ($$\displaystyle N_a $$) | ↑ $$\displaystyle N_a $$ → ↑ $$\displaystyle 2\phi_F $$ → ↑ Vₜ | | Flat-band voltage ($$\displaystyle V_{FB} $$) | Depends on metal-semiconductor workfunction difference and fixed oxide charges | | Surface potential ($$\displaystyle 2\phi_F $$) | Inherently tied to $$\displaystyle N_a $$ |
Body Effect: Vₜ increases with source-to-body bias ($$\displaystyle V_{SB} $$):

$$V_T = V_{T0} + \gamma \left( \sqrt{|2\phi_F + V_{SB}|} - \sqrt{|2\phi_F|} \right)$$

where $$\displaystyle \gamma = \frac{\sqrt{2q\epsilon_{si} N_a}}{C_{ox}} $$.

Channel-Length Modulation: Short-channel devices exhibit Vₜ roll-off due to drain-induced barrier lowering (DIBL).

[!TIP] Exam Focus: Vₜ expression derivation and parameter dependencies are frequently asked. Remember that $$\displaystyle V_{FB} $$ can be negative for nMOS on p⁺-poly gate.

Sub-threshold Region Operation

Sub-threshold MOS Model: For $$\displaystyle V_{GS} < V_T $$, current flows via diffusion:

$$I_D \approx I_{D0} e^{\frac{q(V_{GS} - V_T)}{nkT}} \left(1 - e^{-\frac{qV_{DS}}{kT}}\right)$$

where $$\displaystyle n = 1 + \frac{C_{dep}}{C_{ox}} $$ (sub-threshold swing factor), $$\displaystyle I_{D0} $$ is process-dependent.

Sub-threshold Slope (SS):

$$SS = \left( \frac{\partial \log_{10} I_D}{\partial V_{GS}} \right)^{-1} = \frac{kT}{q} \ln(10) \left(1 + \frac{C_{dep}}{C_{ox}}\right) \approx 60 \text{ mV/dec at 300K}$$

Dependence:
- Temperature: SS ∝ T
- Capacitance ratio: Lower $$\displaystyle C_{dep}/C_{ox} $$ → steeper SS (ideal ≈ 60 mV/dec)
Applications: Ultra-low-power circuits, biomedical implants, IoT sensors.

[!TIP] Common Pitfall: Sub-threshold current is exponential, not quadratic. SS cannot be below 60 mV/dec at room temperature due to thermodynamic limits.

DC Characteristics of CMOS Inverter

Voltage Transfer Characteristic (VTC):
- Three regions: (1) M₁ linear/M₂ cutoff, (2) both saturation, (3) M₁ cutoff/M₂ linear.
- Switching threshold $$\displaystyle V_M $$: $$\displaystyle V_{in} = V_{out} $$; for symmetric CMOS ($$\displaystyle \beta_n = \beta_p $$), $$\displaystyle V_M \approx V_{DD}/2 $$.
Noise Margins:

$$NM_L = V_{IL} - V_{OL}, \quad NM_H = V_{OH} - V_{IH}$$

where $$\displaystyle V_{IL}, V_{IH} $$ are low/high input voltage boundaries.

Inference on MOSFET Channel Length:
- Long-channel: Ideal square-law, sharp VTC transition, high noise margins.
- Short-channel:
  - Vₜ roll-off → shifts $$\displaystyle V_M $$.
  - DIBL → reduced gain, degraded noise margins.
  - Velocity saturation → lower drive current.
  - Punch-through → increased leakage.
Gate Voltage Limits for Stacked Devices (e.g., series nMOS):

To avoid cutoff in stacked nMOS (M₁, M₂), ensure:

$$V_{GS1} > V_T \quad \text{and} \quad V_{DS1} \geq V_{GS2} - V_T$$

For equal sizing, maximum input voltage $$\displaystyle V_{in,max} $$ such that M₂ remains in saturation/linear:

$$V_{in,max} \leq V_{DD} - V_T \quad (\text{for bottom device})$$

[!TIP] Exam Problem: Given a stacked pull-down network, calculate minimum $$\displaystyle V_{in} $$ to keep all transistors on. Use KVL and saturation conditions: $$\displaystyle V_{DS} \geq V_{GS} - V_T $$.

COMBINATIONAL LOGIC DESIGN

NMOS Logic Gates

Pull-Down Network (PDN) Design: Series = AND, parallel = OR. Implement Boolean function as PDN; pull-up is always resistive (load transistor or depletion load).
Realization of Z = A(D + C) + BE:
1. Complement: $$\displaystyle \overline{Z} = \overline{A(D+C) + BE} = \overline{A} \cdot \overline{(D+C)} \cdot \overline{B} \cdot \overline{E} $$ (De Morgan).
2. PDN: Series-parallel network for $\overline{Z}$.
3. Actual PDN for Z: Parallel combination of:
  - Series: A and (parallel of D and C)
  - Series: B and E
Ratioed Logic vs. Static CMOS:

| Feature | Ratioed NMOS | Static CMOS | |---------|--------------|-------------| | Pull-up | Load transistor (enhancement/depletion) | Complementary PDN | | Noise Margin | Low (voltage division) | High (rail-to-rail) | | Power | Static power present | Near-zero static power | | Area | Smaller | Larger (dual networks) |

[!TIP] Key Insight: NMOS logic uses only nMOS in PDN; pMOS is simple load. Static CMOS uses both nMOS and pMOS networks, complementary.

Transmission Gate Logic

Structure: Parallel nMOS and pMOS with common gate controls ($\overline{C}$ to nMOS, $C$ to pMOS).
Operation: Low resistance when $$\displaystyle C=1 $$ (nMOS on, pMOS on); high impedance when $$\displaystyle C=0 $$.
Transient Analysis (Resistor Model):
- On-resistance: $$\displaystyle R_{eq} \approx \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)} $$ for nMOS; pMOS has higher resistance.
- RC delay: $$\displaystyle \tau \approx R_{eq} C_L $$, where $$\displaystyle C_L $$ includes parasitic and load capacitances.
Advantages over Single MOSFET:
- Symmetric resistance for high/low signals.
- No threshold voltage drop (full $$\displaystyle V_{DD} $$ swing).
- Better charge transfer in both directions.

[!TIP] Common Mistake: Forgetting that transmission gate passes both 0 and 1 well, while single MOSFET passes strong 0 but weak 1 (threshold loss).

Transmission Gate-Based Design

Design Methodology: Use transmission gates as switches controlled by logic variables to connect/disconnect nodes.
Ex-OR Gate Implementation:
- $$\displaystyle Y = A \oplus B = A\overline{B} + \overline{A}B $$
- Circuit: Two parallel paths:
  - Path 1: A through TG controlled by $\overline{B}$.
  - Path 2: $\overline{A}$ through TG controlled by B.
- Output node precharged to 0 via weak pMOS.

[!TIP] Exam Tip: Draw transmission gate symbol clearly: parallel MOSFETs with inverted gate on pMOS.

BiCMOS Circuits

BiCMOS Inverter:
- Input: CMOS pair (nMOS/pMOS) drives base of bipolar npn.
- Pull-up: pMOS + npn emitter follower.
- Pull-down: nMOS + npn common-emitter.
Operation:
- Input low: nMOS on → npn on → output pulled down.
- Input high: pMOS on → npn off → output pulled up via pMOS and npn off.
Comparison with CMOS:

| Parameter | CMOS | BiCMOS | |-----------|------|--------| | Speed | Moderate (resistive load) | High (bipolar gain) | | Power | Low static | Higher static (bias currents) | | Noise Immunity | Good | Excellent (large noise margin) | | Area | Smaller | Larger (bipolar + CMOS) |
Applications: High-performance logic, drivers for large capacitive loads.

SEQUENTIAL LOGIC DESIGN (ASYNCHRONOUS)

Asynchronous Sequential Circuits

Fundamental Mode Operation:
- Assumptions: Inputs change only when circuit is stable; one input changes at a time.
- No clock; state changes triggered by input transitions.
State Table vs. Flow Table:
- State table: Explicit state encoding (binary).
- Flow table: States denoted by letters; shows next states for each input combination.
Primitive Flow Table: All states distinct (no merging).
Row Reduction Techniques:
1. Merging compatible states: Two states compatible if for all inputs, next states are same or one is "don't care" and outputs match.
2. Iterative merging: Combine rows to minimize state count.
3. Check for essential hazards: Ensure no two states in same row have adjacent next states differing in multiple variables.

State Diagram Design: Sequence Detector for "101"

Specification: Output 1 when last three bits are 101 (overlapping allowed).
States (based on recent history):
- S₀: no bits matched.
- S₁: last bit = 1.
- S₂: last two bits = 10.
- S₃: last three bits = 101 (output 1).

State Diagram:


S₀ --1--> S₁, S₀ --0--> S₀

S₁ --0--> S₂, S₁ --1--> S₁

S₂ --1--> S₃, S₂ --0--> S₀

S₃ --0--> S₂, S₃ --1--> S₁ (overlap: after 101, next 1 starts new sequence)

Output: Z=1 only in S₃.

[!TIP] Mnemonic: For overlapping sequence, after detecting "101", a trailing "1" becomes start of new "1".

Flow Table Analysis: Toggle Circuit

Behavior: Output toggles on each input pulse.
Flow Table (two states A/B, input X, output Z):

| Present State | X=0 | X=1 | |---------------|-----|-----| | A | A/0 | B/1 | | B | B/1 | A/0 |
Row Reduction: States A and B are compatible? Check:
- For X=0: A→A, B→B → different → not compatible.
- Cannot merge; two states necessary.
Stable States: In fundamental mode, state is stable if next state = present state for current input. Here, no stable states under input change (designed to toggle).

[!TIP] Exam Trap: In flow table, "—" means don't care, but in fundamental mode, only one input change allowed; ensure no adjacent states in same row cause race.

CIRCUIT IMPLEMENTATION & SPECIALIZED CIRCUITS

MOSFET as Passive Components

Linear Resistor:
- Operate MOSFET in ohmic region ($$\displaystyle V_{DS} < V_{GS} - V_T $$).
- Resistance: $$\displaystyle R_{DS} = \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T - \frac{V_{DS}}{2})} \approx \frac{1}{\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)} $$ for small $$\displaystyle V_{DS} $$.
Tuning:
- Gate voltage $$\displaystyle V_{GS} $$: ↑ $$\displaystyle V_{GS} $$ → ↓ $$\displaystyle R_{DS} $$.
- Sizing (W/L): ↑ W/L → ↓ $$\displaystyle R_{DS} $$.
Applications: Active loads, tunable RC networks.

Voltage Reference Circuits (High Sensitivity)

Design Principle: Generate voltage with positive temperature coefficient (PTC) and negative temperature coefficient (NTC) that cancel.
Circuit Topology (e.g., MOSFET-based with feedback):
- Use two MOSFETs: one in saturation (Vₜ has NTC), one in weak inversion (exponential I-V has PTC).
- Sum currents to produce reference with near-zero TC.
- Example: Bandgap reference core using BJTs, but MOSFET version uses sub-threshold operation.
Temperature Compensation: Choose bias currents such that $$\displaystyle \frac{\partial V_{ref}}{\partial T} = 0 $$.
Process Compensation: Use ratioed devices to minimize mismatch.

[!TIP] High Sensitivity: Means small change in reference per change in temperature/process. Achieved by careful biasing in sub-threshold or saturation regions with matched devices.

FABRICATION TECHNOLOGY & DEVICE STRUCTURES

NMOS Fabrication Process

Substrate: p-type silicon wafer.
Oxidation: Grow field oxide (FOX) for isolation.
Photolithography: Define active regions (where FOX removed).
Gate Oxide Growth: Thin oxide under gate.
Poly Deposition & Patterning: Form gate electrode.
Source/Drain Doping: n⁺ implantation using gate as mask (self-aligned).
Metallization: Deposit and pattern aluminum for contacts.
Passivation: Silicon nitride layer.

Key Features:
- n-well not needed (only nMOS).
- Source/drain formed by diffusion/implant.
Limitations vs. CMOS:
- No pMOS → no complementary pull-up → ratioed logic only.
- Higher power consumption.
- Poor noise margin.

BiCMOS Technology

Integration: Combine bipolar npn/pnp and CMOS on same chip.
Process Steps:
1. Start with p-substrate.
2. Define n-well for pMOS and npn collector.
3. Form bipolar base/emitter (deep diffusion).
4. CMOS gate oxide, poly, source/drain.
5. Metallization with multiple layers for bipolar base/emitter contacts.
Isolation: STI (shallow trench) or p⁺ guard rings.
Advantages:
- High speed (bipolar) + low power (CMOS).
- High gain, large fan-out.
- Ideal for analog/mixed-signal (ADCs, DACs, op-amps).

[!TIP] Exam Comparison: BiCMOS cost higher than pure CMOS but better for I/O drivers and high-frequency analog.

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CMOS DESIGN (EC-603 (B)) - Unit 1 Short Notes